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@@ -23,38 +23,38 @@
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#include "lowlevel.h"
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#include "lowlevel.h"
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#include "lowl-vcom.h"
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#include "lowl-vcom.h"
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#include "util.h"
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#include "util.h"
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-
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+#include <bwltc-commands.h>
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static const uint8_t futurebit_max_chips = 0x01;
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static const uint8_t futurebit_max_chips = 0x01;
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-#define FUTUREBIT_DEFAULT_FREQUENCY 104
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-#define FUTUREBIT_MIN_CLOCK 104
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-#define FUTUREBIT_MAX_CLOCK 400
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+#define FUTUREBIT_DEFAULT_FREQUENCY 600
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+#define FUTUREBIT_MIN_CLOCK 384
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+#define FUTUREBIT_MAX_CLOCK 1020
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// Number of seconds chip of 54 cores @ 352mhz takes to scan full range
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// Number of seconds chip of 54 cores @ 352mhz takes to scan full range
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-#define FUTUREBIT_HASH_SPEED 4090.0
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+#define FUTUREBIT_HASH_SPEED 1130.0
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#define FUTUREBIT_MAX_NONCE 0xffffffff
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#define FUTUREBIT_MAX_NONCE 0xffffffff
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#define FUTUREBIT_READ_SIZE 8
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#define FUTUREBIT_READ_SIZE 8
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-#define futurebit_max_clusters_per_chip 6
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-#define futurebit_max_cores_per_cluster 9
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-static const uint8_t futurebit_g_head[] = {
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- 0xd4, 0x59, 0x2d, 0x01, 0x1d, 0x01, 0x8e, 0xa7, 0x4e, 0xbb, 0x17, 0xb8, 0x06, 0x6b, 0x2a, 0x75,
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- 0x83, 0x99, 0xd5, 0xf1, 0x9b, 0x5c, 0x60, 0x73, 0xd0, 0x9b, 0x50, 0x0d, 0x92, 0x59, 0x82, 0xad,
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- 0xc4, 0xb3, 0xed, 0xd3, 0x52, 0xef, 0xe1, 0x46, 0x67, 0xa8, 0xca, 0x9f, 0x27, 0x9f, 0x63, 0x30,
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- 0xcc, 0xbb, 0xb9, 0x10, 0x3b, 0x9e, 0x3a, 0x53, 0x50, 0x76, 0x50, 0x52, 0x08, 0x1d, 0xdb, 0xae,
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- 0x89, 0x8f, 0x1e, 0xf6, 0xb8, 0xc6, 0x4f, 0x3b, 0xce, 0xf7, 0x15, 0xf6, 0, 0, 0, 1,
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- 0, 0, 0, 1, 0x8e, 0xa7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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- 0, 0, 0, 0, 0, 0, 0
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+//#define futurebit_max_clusters_per_chip 6
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+//#define futurebit_max_cores_per_cluster 9
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+unsigned char job2[] = {
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+0x3c, 0xff, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff,
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+0x07, 0x00, 0x00, 0x00, 0xd7, 0xa2, 0xea, 0xb0, 0xc2, 0xd7, 0x6f, 0x1e, 0x33, 0xa4, 0xb5, 0x3e,
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+0x0e, 0xb2, 0x84, 0x34, 0x89, 0x5a, 0x8b, 0x10, 0xfb, 0x19, 0x7d, 0x76, 0xe6, 0xe0, 0x38, 0x60,
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+0x15, 0x3f, 0x6a, 0x6e, 0x00, 0x00, 0x00, 0x04, 0xb5, 0x93, 0x93, 0x27, 0xf7, 0xc9, 0xfb, 0x26,
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+0xdf, 0x3b, 0xde, 0xc0, 0xa6, 0x6c, 0xae, 0x10, 0xb5, 0x53, 0xb7, 0x61, 0x5d, 0x67, 0xa4, 0x97,
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+0xe8, 0x7f, 0x06, 0xa6, 0x27, 0xfc, 0xd5, 0x57, 0x44, 0x38, 0xb8, 0x4d, 0xb1, 0xfe, 0x4f, 0x5f,
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+0x31, 0xaa, 0x47, 0x3d, 0x3d, 0xb4, 0xfc, 0x03, 0xa2, 0x78, 0x92, 0x44, 0xa1, 0x39, 0xb0, 0x35,
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+0xe1, 0x46, 0x04, 0x1e, 0x8c, 0x0a, 0xad, 0x28, 0x58, 0xec, 0x78, 0x3c, 0x1b, 0x00, 0xa4, 0x43
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};
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};
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+
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BFG_REGISTER_DRIVER(futurebit_drv)
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BFG_REGISTER_DRIVER(futurebit_drv)
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static const struct bfg_set_device_definition futurebit_set_device_funcs_probe[];
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static const struct bfg_set_device_definition futurebit_set_device_funcs_probe[];
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struct futurebit_chip {
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struct futurebit_chip {
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uint8_t chipid;
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uint8_t chipid;
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- uint8_t global_reg[8];
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- uint16_t chip_mask[futurebit_max_clusters_per_chip];
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- uint32_t clst_offset[futurebit_max_clusters_per_chip];
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unsigned active_cores;
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unsigned active_cores;
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unsigned freq;
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unsigned freq;
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};
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};
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@@ -64,10 +64,7 @@ void futurebit_chip_init(struct futurebit_chip * const chip, const uint8_t chipi
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{
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{
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*chip = (struct futurebit_chip){
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*chip = (struct futurebit_chip){
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.chipid = chipid,
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.chipid = chipid,
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- .global_reg = {0, 4, 0x40, 0, 0, 0, 0, 1},
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- .chip_mask = {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
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- .clst_offset = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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- .active_cores = 54,
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+ .active_cores = 64,
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.freq = FUTUREBIT_DEFAULT_FREQUENCY,
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.freq = FUTUREBIT_DEFAULT_FREQUENCY,
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};
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};
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}
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}
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@@ -75,109 +72,239 @@ void futurebit_chip_init(struct futurebit_chip * const chip, const uint8_t chipi
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static
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static
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void futurebit_reset_board(const int fd)
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void futurebit_reset_board(const int fd)
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{
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{
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-
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+
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if(set_serial_rts(fd, BGV_HIGH) == BGV_ERROR)
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if(set_serial_rts(fd, BGV_HIGH) == BGV_ERROR)
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applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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-
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- cgsleep_ms(100);
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-
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+
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+ cgsleep_ms(1000);
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+
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if(set_serial_rts(fd, BGV_LOW) == BGV_ERROR)
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if(set_serial_rts(fd, BGV_LOW) == BGV_ERROR)
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applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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}
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}
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+
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+int futurebit_write(const int fd, const void *buf, size_t buflen)
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+{
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+ int repeat = 0;
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+ int size = 0;
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+ int ret = 0;
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+ int nwrite = 0;
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+
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+ char output[(buflen * 2) + 1];
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+ bin2hex(output, buf, buflen);
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+ applog(LOG_DEBUG, "WRITE BUFFER %s", output);
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+
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+ while(size < buflen)
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+ {
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+ nwrite = write(fd, buf, buflen);
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+ //applog(LOG_DEBUG, "FutureBit Write SIZE: %u", nwrite);
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+ if (nwrite < 0)
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+ {
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+ applog(LOG_ERR, "FutureBit Write error: %s", strerror(errno));
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+ break;
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+ }
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+
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+ size += nwrite;
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+
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+ if (repeat++ > 1)
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+ {
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+ break;
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+ }
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+
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+ }
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+
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+ return 0;
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+}
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+
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static
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static
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-void futurebit_set_diag_mode(struct futurebit_chip * const chip, bool diag_enable)
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+bool futurebit_read (const int fd, unsigned char *buf, int read_amount)
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{
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{
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- if (diag_enable)
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- chip->global_reg[1] |= 1;
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- else
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- chip->global_reg[1] &= ~1;
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+
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+ ssize_t nread = 0;
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+ int size = 0;
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+ int repeat = 0;
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+
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+
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+
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+ while(size < read_amount)
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+ {
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+ nread = read(fd, buf, read_amount);
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+ if(nread < 0)
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+ return false;
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+
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+ size += nread;
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+
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+ //char output[(read_amount * 2) + 1];
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+ // bin2hex(output, buf, read_amount);
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+ //applog(LOG_DEBUG, "READ BUFFER %s", output);
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+
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+ if (repeat++ > 0)
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+ {
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+ break;
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+ }
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+ }
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+
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+#if 0
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+ int i;
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+ for (i=0; i<size; i++)
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+ {
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+ printf("0x%02x ", buf[i]);
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+ }
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+ printf("\n");
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+#endif
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+
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+ return true;
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}
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}
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static
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static
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-bool futurebit_write_global_reg(const int fd, const struct futurebit_chip * const chip)
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+char futurebit_read_register(const int fd, uint32_t chip, uint32_t moudle, uint32_t RegAddr)
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{
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{
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- uint8_t buf[112];
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- memset(&buf, 0, 102);
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- memcpy(&buf[102], &chip->global_reg[0], 8);
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- buf[110] = 0;
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- buf[111] = 0xff;
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-
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- if (write(fd, buf, sizeof(buf)) != sizeof(buf))
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- return false;
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- return true;
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+ uint8_t read_reg_data[8]={0};
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+ uint8_t read_reg_cmd[16]={0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0xc3};
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+
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+
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+ read_reg_cmd[1] = chip;
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+ read_reg_cmd[2] = moudle;
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+ read_reg_cmd[3] = 0x80|RegAddr; //read
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+
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+
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+ static int nonce=0;
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+ futurebit_write(fd, read_reg_cmd, 9);
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+
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+
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+ cgsleep_us(100000);
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+ if(!futurebit_read(fd, read_reg_data, 8))
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+ applog(LOG_DEBUG, "FutureBit read register fail");
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+
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+
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+ applog(LOG_DEBUG, "FutureBit Read Return:");
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+ for (int i=0; i<8; i++)
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+ {
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+ applog(LOG_DEBUG,"0x%02x ", read_reg_data[i]);
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+ }
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+ applog(LOG_DEBUG,"\n");
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+
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+ return read_reg_data[0];
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+}
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+
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+unsigned
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+int futurebit_write_register(const int fd, uint32_t chipId, uint32_t moudle, uint32_t Regaddr, uint32_t value)
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+{
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+ bool ret =true;
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+ uint8_t read_reg_cmd[16]={0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0xc3};
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+
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+ read_reg_cmd[1] = chipId;
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+ read_reg_cmd[2] = moudle;
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+ read_reg_cmd[3] = 0x7f&Regaddr; //&0x7f->write\BF\BFbit[7]:1 read, 0 write
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+ read_reg_cmd[4] = value&0xff;
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+ read_reg_cmd[5] = (value>>8)&0xff;
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+ read_reg_cmd[6] = (value>>16)&0xff;
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+ read_reg_cmd[7] = (value>>24)&0xff;
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+
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+
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+ futurebit_write(fd, read_reg_cmd, 9);
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+
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+ return ret;
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}
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}
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static
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static
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-bool futurebit_write_cluster_reg(const int fd, const struct futurebit_chip * const chip, const uint16_t cores_active, const uint32_t offset, const uint8_t clstid)
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+void futurebit_send_cmds(const int fd, const unsigned char *cmds[])
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{
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{
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- uint8_t buf[112];
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- memset(&buf, 0, 104);
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- pk_u16be(buf, 104, cores_active);
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- pk_u32be(buf, 106, offset);
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- buf[110] = clstid;
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- buf[111] = 0xfe;
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- //applog(LOG_DEBUG, " %u: %u: %u : %u", buf[106], buf[107], buf[108], buf[109]);
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- if (write(fd, buf, sizeof(buf)) != sizeof(buf))
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- return false;
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- return true;
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+ int i;
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+ for(i = 0; cmds[i] != NULL; i++)
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+ {
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+ futurebit_write(fd, cmds[i] + 1, cmds[i][0]);
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+ cgsleep_us(10000);
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+ }
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}
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}
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+//921600bps: 3C ff f8 20 1f 01 82 f6
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+static
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+void futurebit_set_baudrate(const int fd)
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+{
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+ const uint8_t cmd[] = {0x3C, 0xff, 0xf8, 0x20, 0x1f, 0x01, 0x82, 0xf6, 0xC3};
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+ futurebit_write(fd, cmd, 9);
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+ cgsleep_us(100000);
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+ serial_change_baud(fd, 921600);
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+}
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static
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static
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-bool futurebit_init_pll(const int fd, struct futurebit_chip * const chip)
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+void futurebit_set_frequency(const int fd, uint32_t freq)
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{
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{
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- unsigned freq = chip->freq;
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- uint8_t bytes1;
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- uint8_t bytes2;
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|
|
|
- uint8_t divider;
|
|
|
|
|
-
|
|
|
|
|
- if (freq <= 200){
|
|
|
|
|
- divider = (freq - 8)/8;
|
|
|
|
|
- divider <<= 1;
|
|
|
|
|
- bytes1 = 0x70 | ((divider & 0xf0) >> 4);
|
|
|
|
|
- bytes2 = 0x30 | ((divider & 0xf0) >> 4);
|
|
|
|
|
-
|
|
|
|
|
- }else {
|
|
|
|
|
- divider = (freq - 16)/16;
|
|
|
|
|
- divider <<= 1;
|
|
|
|
|
- bytes1 = 0x60 | ((divider & 0xf0) >> 4);
|
|
|
|
|
- bytes2 = 0x20 | ((divider & 0xf0) >> 4);
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
- uint8_t bytes3 = 0x00 | ((divider & 0x0f) << 4);
|
|
|
|
|
-
|
|
|
|
|
- pk_u16be(chip->global_reg, 2, 0x4000);
|
|
|
|
|
- chip->global_reg[1] |= 0xc;
|
|
|
|
|
- if (!futurebit_write_global_reg(fd, chip))
|
|
|
|
|
- return false;
|
|
|
|
|
-
|
|
|
|
|
- chip->global_reg[2] = bytes1;
|
|
|
|
|
- chip->global_reg[3] = bytes3;
|
|
|
|
|
- cgsleep_ms(50);
|
|
|
|
|
- if (!futurebit_write_global_reg(fd, chip))
|
|
|
|
|
- return false;
|
|
|
|
|
-
|
|
|
|
|
- chip->global_reg[2] = bytes2;
|
|
|
|
|
- chip->global_reg[1] &= ~8;
|
|
|
|
|
- cgsleep_ms(50);
|
|
|
|
|
- if (!futurebit_write_global_reg(fd, chip))
|
|
|
|
|
- return false;
|
|
|
|
|
-
|
|
|
|
|
- chip->global_reg[1] &= ~4;
|
|
|
|
|
- cgsleep_ms(50);
|
|
|
|
|
- if (!futurebit_write_global_reg(fd, chip))
|
|
|
|
|
- return false;
|
|
|
|
|
-
|
|
|
|
|
- return true;
|
|
|
|
|
|
|
+ struct frequecy *p;
|
|
|
|
|
+ unsigned char **cmd = cmd_set_600M;
|
|
|
|
|
+ int i;
|
|
|
|
|
+
|
|
|
|
|
+ for (i=0; i<ARRAY_LEN; i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ if (fre_array[i].freq == freq)
|
|
|
|
|
+ {
|
|
|
|
|
+ cmd = fre_array[i].cmd;
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_send_cmds(fd, cmd);
|
|
|
|
|
+
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+void futurebit_config_all_chip(const int fd, uint32_t freq)
|
|
|
|
|
+{
|
|
|
|
|
+ uint32_t reg_val;
|
|
|
|
|
+ int i;
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_reset_board(fd);
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_send_cmds(fd, cmd_auto_address);
|
|
|
|
|
+ cgsleep_us(100000);
|
|
|
|
|
+ //futurebit_set_baudrate(fd);
|
|
|
|
|
+ //cgsleep_us(100000);
|
|
|
|
|
+ futurebit_set_frequency(fd, freq);
|
|
|
|
|
+ cgsleep_us(100000);
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+#if 1
|
|
|
|
|
+ futurebit_write_register(fd, 0xff, 0xf8,0x22,0x11090005);//feed through
|
|
|
|
|
+ cgsleep_us(100000);
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
+ reg_val = 0xffffffff/futurebit_max_chips;
|
|
|
|
|
+ for (i=1; i<(futurebit_max_chips+1); i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ futurebit_write_register(fd, i, 0x40, 0x00, reg_val*(i-1));
|
|
|
|
|
+ cgsleep_us(100000);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_send_cmds(fd, gcp_cmd_reset);
|
|
|
|
|
+ cgsleep_us(100000);
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
+void futurebit_pull_up_payload(const int fd)
|
|
|
|
|
+{
|
|
|
|
|
+ char i;
|
|
|
|
|
+ unsigned int regval = 0;
|
|
|
|
|
+
|
|
|
|
|
+ //pull up payload by steps.
|
|
|
|
|
+ for (i=0; i<8; i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ regval |= (0x0f<<(4*i));
|
|
|
|
|
+ futurebit_write_register(fd, 0xff, 0xf8, 0x04, regval);
|
|
|
|
|
+ cgsleep_us(35000);
|
|
|
|
|
+ futurebit_write_register(fd, 0xff, 0xf8, 0x05, regval);
|
|
|
|
|
+ cgsleep_us(35000);
|
|
|
|
|
+ futurebit_write(fd, job2,144) ;
|
|
|
|
|
+ cgsleep_us(35000);
|
|
|
|
|
+ }
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
static
|
|
static
|
|
|
bool futurebit_send_golden(const int fd, const struct futurebit_chip * const chip, const void * const data, const void * const target_p)
|
|
bool futurebit_send_golden(const int fd, const struct futurebit_chip * const chip, const void * const data, const void * const target_p)
|
|
|
{
|
|
{
|
|
|
uint8_t buf[112];
|
|
uint8_t buf[112];
|
|
|
const uint8_t * const target = target_p;
|
|
const uint8_t * const target = target_p;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
memcpy(buf, data, 80);
|
|
memcpy(buf, data, 80);
|
|
|
if (target && !target[0x1f])
|
|
if (target && !target[0x1f])
|
|
|
memcpy(&buf[80], target, 0x20);
|
|
memcpy(&buf[80], target, 0x20);
|
|
@@ -186,11 +313,11 @@ bool futurebit_send_golden(const int fd, const struct futurebit_chip * const chi
|
|
|
memset(&buf[80], 0xff, 0x1f);
|
|
memset(&buf[80], 0xff, 0x1f);
|
|
|
buf[111] = 0;
|
|
buf[111] = 0;
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
//char output[(sizeof(buf) * 2) + 1];
|
|
//char output[(sizeof(buf) * 2) + 1];
|
|
|
//bin2hex(output, buf, sizeof(buf));
|
|
//bin2hex(output, buf, sizeof(buf));
|
|
|
//applog(LOG_DEBUG, "GOLDEN OUTPUT %s", output);
|
|
//applog(LOG_DEBUG, "GOLDEN OUTPUT %s", output);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (write(fd, buf, sizeof(buf)) != sizeof(buf))
|
|
if (write(fd, buf, sizeof(buf)) != sizeof(buf))
|
|
|
return false;
|
|
return false;
|
|
|
return true;
|
|
return true;
|
|
@@ -200,29 +327,83 @@ static
|
|
|
bool futurebit_send_work(const struct thr_info * const thr, struct work * const work)
|
|
bool futurebit_send_work(const struct thr_info * const thr, struct work * const work)
|
|
|
{
|
|
{
|
|
|
struct cgpu_info *device = thr->cgpu;
|
|
struct cgpu_info *device = thr->cgpu;
|
|
|
- uint8_t buf[112];
|
|
|
|
|
|
|
+
|
|
|
|
|
+ uint32_t *pdata = work->data;
|
|
|
|
|
+ uint32_t *midstate = work->midstate;
|
|
|
|
|
+ const uint32_t *ptarget = work->target;
|
|
|
|
|
+
|
|
|
|
|
+ int i, bpos;
|
|
|
|
|
+ unsigned char bin[156];
|
|
|
|
|
+ // swab for big endian
|
|
|
|
|
+ uint32_t midstate2[8];
|
|
|
|
|
+ uint32_t data2[20];
|
|
|
|
|
+ uint32_t target2[8];
|
|
|
|
|
+ for(i = 0; i < 19; i++)
|
|
|
|
|
+ {
|
|
|
|
|
+ data2[i] = htole32(pdata[i]);
|
|
|
|
|
+ if(i >= 8) continue;
|
|
|
|
|
+ target2[i] = htole32(ptarget[i]);
|
|
|
|
|
+ midstate2[i] = htole32(midstate[i]);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+ data2[19] = 0;
|
|
|
|
|
+
|
|
|
|
|
+ memset(bin, 0, sizeof(bin));
|
|
|
|
|
+ bpos = 0; memcpy(bin, "\x3c\xff\x40\x01", 4);
|
|
|
|
|
+ // bpos += 4; memcpy(bin + bpos, "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xff\xff\xff\xff\x00\x00", 32); //target
|
|
|
|
|
+ bpos += 4; memcpy(bin + bpos, (unsigned char *)target2, 32); memset(bin + bpos, 0, 24);
|
|
|
|
|
+ bpos += 32; memcpy(bin + bpos, (unsigned char *)midstate2, 32); //midstateno
|
|
|
|
|
+ bpos += 32; memcpy(bin + bpos, (unsigned char *)data2, 76); //blockheader 76 bytes (ignore last 4bytes nounce)
|
|
|
|
|
+ bpos += 76;
|
|
|
|
|
+
|
|
|
|
|
+ /* char szVal[] = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x80\xff\x7f\x00\x00\x00fb357fbeda2ee2a93b841afac3e58173d4a97a400a84a4ec27c47ef5e9322ca620000000b99512c06534b34f62d0a88a5f90ac1857f0c02a1b6e6bb3185aec323b0eb79d2983a6d34c0e59272444dc28b1041e6114939ca8cdbd99f4058ef4965e293ba7598b98cc1a25e34f"; // source string
|
|
|
|
|
+
|
|
|
|
|
+ char szOutput[144];
|
|
|
|
|
+
|
|
|
|
|
+ size_t nLen = strlen(szVal);
|
|
|
|
|
+ // Make sure it is even.
|
|
|
|
|
+ if ((nLen % 2) == 1)
|
|
|
|
|
+ {
|
|
|
|
|
+ printf("Error string must be even number of digits %s", szVal);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ // Process each set of characters as a single character.
|
|
|
|
|
+ nLen >>= 1;
|
|
|
|
|
+ for (size_t idx = 0; idx < nLen; idx++)
|
|
|
|
|
+ {
|
|
|
|
|
+ char acTmp[3];
|
|
|
|
|
+ sscanf(szVal + (idx << 1), "%2s", acTmp);
|
|
|
|
|
+ szOutput[idx] = (char)strtol(acTmp, NULL, 16);
|
|
|
|
|
+ }
|
|
|
|
|
+ */
|
|
|
|
|
+ futurebit_write(device->device_fd, bin, 144);//144bytes
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+ /* uint8_t buf[112];
|
|
|
uint8_t cmd[112];
|
|
uint8_t cmd[112];
|
|
|
const uint8_t * const target = work->target;
|
|
const uint8_t * const target = work->target;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
unsigned char swpdata[80];
|
|
unsigned char swpdata[80];
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
//buf[0] = 0;
|
|
//buf[0] = 0;
|
|
|
//memset(&buf[1], 0xff, 0x1f);
|
|
//memset(&buf[1], 0xff, 0x1f);
|
|
|
memset(&buf[0], 0, 0x18);
|
|
memset(&buf[0], 0, 0x18);
|
|
|
memcpy(&buf[24], &target[24], 0x8);
|
|
memcpy(&buf[24], &target[24], 0x8);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
swap32tobe(swpdata, work->data, 80/4);
|
|
swap32tobe(swpdata, work->data, 80/4);
|
|
|
memcpy(&buf[32], swpdata, 80);
|
|
memcpy(&buf[32], swpdata, 80);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
for (int i = 0; i<112; i++) {
|
|
for (int i = 0; i<112; i++) {
|
|
|
cmd[i] = buf[111 - i];
|
|
cmd[i] = buf[111 - i];
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (write(device->device_fd, cmd, sizeof(cmd)) != sizeof(cmd))
|
|
if (write(device->device_fd, cmd, sizeof(cmd)) != sizeof(cmd))
|
|
|
return false;
|
|
return false;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
|
|
+*/
|
|
|
work->blk.nonce = FUTUREBIT_MAX_NONCE;
|
|
work->blk.nonce = FUTUREBIT_MAX_NONCE;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -231,57 +412,68 @@ bool futurebit_detect_one(const char * const devpath)
|
|
|
{
|
|
{
|
|
|
struct futurebit_chip *chips = NULL;
|
|
struct futurebit_chip *chips = NULL;
|
|
|
unsigned total_cores = 0;
|
|
unsigned total_cores = 0;
|
|
|
-
|
|
|
|
|
|
|
+ uint32_t regval = 0;
|
|
|
|
|
+
|
|
|
const int fd = serial_open(devpath, 115200, 1, true);
|
|
const int fd = serial_open(devpath, 115200, 1, true);
|
|
|
if (fd < 0)
|
|
if (fd < 0)
|
|
|
return_via_applog(err, , LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Failed to open", devpath);
|
|
return_via_applog(err, , LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Failed to open", devpath);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
applog(LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Successfully opened", devpath);
|
|
applog(LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Successfully opened", devpath);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
futurebit_reset_board(fd);
|
|
futurebit_reset_board(fd);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
|
|
+ if(futurebit_read_register(fd, 0xff, 0xf8, 0xa6) != 0x3c)
|
|
|
|
|
+ return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "find chip", devpath);
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
// Init chips, setup PLL, and scan for good cores
|
|
// Init chips, setup PLL, and scan for good cores
|
|
|
chips = malloc(futurebit_max_chips * sizeof(*chips));
|
|
chips = malloc(futurebit_max_chips * sizeof(*chips));
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
struct futurebit_chip * const dummy_chip = &chips[0];
|
|
struct futurebit_chip * const dummy_chip = &chips[0];
|
|
|
futurebit_chip_init(dummy_chip, 0);
|
|
futurebit_chip_init(dummy_chip, 0);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
// pick up any user-defined settings passed in via --set
|
|
// pick up any user-defined settings passed in via --set
|
|
|
drv_set_defaults(&futurebit_drv, futurebit_set_device_funcs_probe, dummy_chip, devpath, detectone_meta_info.serial, 1);
|
|
drv_set_defaults(&futurebit_drv, futurebit_set_device_funcs_probe, dummy_chip, devpath, detectone_meta_info.serial, 1);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
unsigned freq = dummy_chip->freq;
|
|
unsigned freq = dummy_chip->freq;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
applog(LOG_DEBUG, "%s: %s %u mhz", futurebit_drv.dname, "Core clock set to", freq);
|
|
applog(LOG_DEBUG, "%s: %s %u mhz", futurebit_drv.dname, "Core clock set to", freq);
|
|
|
-
|
|
|
|
|
- {
|
|
|
|
|
- uint8_t buf[8];
|
|
|
|
|
- for (unsigned i = 0; i < futurebit_max_chips; ++i)
|
|
|
|
|
- {
|
|
|
|
|
- struct futurebit_chip * const chip = &chips[i];
|
|
|
|
|
- futurebit_chip_init(chip, i);
|
|
|
|
|
- chip->freq = freq;
|
|
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+ struct futurebit_chip * const chip = &chips[0];
|
|
|
|
|
+ futurebit_chip_init(chip, 0);
|
|
|
|
|
+ chip->freq = freq;
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_config_all_chip(fd, freq);
|
|
|
|
|
+
|
|
|
|
|
+ futurebit_pull_up_payload(fd);
|
|
|
|
|
+
|
|
|
//chip->global_reg[1] = 0x05;
|
|
//chip->global_reg[1] = 0x05;
|
|
|
//if (!futurebit_write_global_reg(fd, chip))
|
|
//if (!futurebit_write_global_reg(fd, chip))
|
|
|
// return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
|
|
// return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
|
|
|
//cgsleep_ms(50);
|
|
//cgsleep_ms(50);
|
|
|
- futurebit_set_diag_mode(chip, true);
|
|
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+
|
|
|
|
|
+ /*futurebit_set_diag_mode(chip, true);
|
|
|
if (!futurebit_init_pll(fd, chip))
|
|
if (!futurebit_init_pll(fd, chip))
|
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
|
|
|
cgsleep_ms(50);
|
|
cgsleep_ms(50);
|
|
|
if (!futurebit_send_golden(fd, chip, futurebit_g_head, NULL))
|
|
if (!futurebit_send_golden(fd, chip, futurebit_g_head, NULL))
|
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send scan job", devpath);
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send scan job", devpath);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
while (serial_read(fd, buf, 8) == 8)
|
|
while (serial_read(fd, buf, 8) == 8)
|
|
|
{
|
|
{
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
const uint8_t clsid = buf[7];
|
|
const uint8_t clsid = buf[7];
|
|
|
if (clsid >= futurebit_max_clusters_per_chip)
|
|
if (clsid >= futurebit_max_clusters_per_chip)
|
|
|
applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "cluster", clsid, devpath, i);
|
|
applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "cluster", clsid, devpath, i);
|
|
|
const uint8_t coreid = buf[6];
|
|
const uint8_t coreid = buf[6];
|
|
|
if (coreid >= futurebit_max_cores_per_cluster)
|
|
if (coreid >= futurebit_max_cores_per_cluster)
|
|
|
applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "core", coreid, devpath, i);
|
|
applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "core", coreid, devpath, i);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (buf[0] != 0xd9 || buf[1] != 0xeb || buf[2] != 0x86 || buf[3] != 0x63) {
|
|
if (buf[0] != 0xd9 || buf[1] != 0xeb || buf[2] != 0x86 || buf[3] != 0x63) {
|
|
|
//chips[i].chip_good[clsid][coreid] = false;
|
|
//chips[i].chip_good[clsid][coreid] = false;
|
|
|
applog(LOG_DEBUG, "%s: Bad %s at core (%u) during scan of %s chip %u cluster %u", futurebit_drv.dname, "nonce", coreid, devpath, i, clsid);
|
|
applog(LOG_DEBUG, "%s: Bad %s at core (%u) during scan of %s chip %u cluster %u", futurebit_drv.dname, "nonce", coreid, devpath, i, clsid);
|
|
@@ -292,24 +484,24 @@ bool futurebit_detect_one(const char * const devpath)
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
applog(LOG_DEBUG, "%s: Identified %d cores on %s", futurebit_drv.dname, total_cores, devpath);
|
|
applog(LOG_DEBUG, "%s: Identified %d cores on %s", futurebit_drv.dname, total_cores, devpath);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (total_cores == 0)
|
|
if (total_cores == 0)
|
|
|
goto err;
|
|
goto err;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
futurebit_reset_board(fd);
|
|
futurebit_reset_board(fd);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
// config nonce ranges per cluster based on core responses
|
|
// config nonce ranges per cluster based on core responses
|
|
|
unsigned mutiple = FUTUREBIT_MAX_NONCE / total_cores;
|
|
unsigned mutiple = FUTUREBIT_MAX_NONCE / total_cores;
|
|
|
uint32_t n_offset = 0x00000000;
|
|
uint32_t n_offset = 0x00000000;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
for (unsigned i = 0; i < futurebit_max_chips; ++i)
|
|
for (unsigned i = 0; i < futurebit_max_chips; ++i)
|
|
|
{
|
|
{
|
|
|
struct futurebit_chip * const chip = &chips[i];
|
|
struct futurebit_chip * const chip = &chips[i];
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
chips[i].active_cores = total_cores;
|
|
chips[i].active_cores = total_cores;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
//chip->global_reg[1] = 0x04;
|
|
//chip->global_reg[1] = 0x04;
|
|
|
//if (!futurebit_write_global_reg(fd, chip))
|
|
//if (!futurebit_write_global_reg(fd, chip))
|
|
|
//return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
|
|
//return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
|
|
@@ -318,33 +510,34 @@ bool futurebit_detect_one(const char * const devpath)
|
|
|
if (!futurebit_init_pll(fd, chip))
|
|
if (!futurebit_init_pll(fd, chip))
|
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
|
|
|
cgsleep_ms(50);
|
|
cgsleep_ms(50);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
for (unsigned x = 0; x < futurebit_max_clusters_per_chip; ++x) {
|
|
for (unsigned x = 0; x < futurebit_max_clusters_per_chip; ++x) {
|
|
|
unsigned gc = 0;
|
|
unsigned gc = 0;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
uint16_t core_mask = chips[i].chip_mask[x];
|
|
uint16_t core_mask = chips[i].chip_mask[x];
|
|
|
chips[i].clst_offset[x] = n_offset;
|
|
chips[i].clst_offset[x] = n_offset;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
applog(LOG_DEBUG, "OFFSET %u MASK %u CHIP %u CLUSTER %u", n_offset, core_mask, i, x);
|
|
applog(LOG_DEBUG, "OFFSET %u MASK %u CHIP %u CLUSTER %u", n_offset, core_mask, i, x);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (!futurebit_write_cluster_reg(fd, chip, core_mask, n_offset, x))
|
|
if (!futurebit_write_cluster_reg(fd, chip, core_mask, n_offset, x))
|
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send config register", devpath);
|
|
return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send config register", devpath);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
for (unsigned z = 0; z < 15; ++z) {
|
|
for (unsigned z = 0; z < 15; ++z) {
|
|
|
if (core_mask & 0x0001)
|
|
if (core_mask & 0x0001)
|
|
|
gc += 1;
|
|
gc += 1;
|
|
|
core_mask >>= 1;
|
|
core_mask >>= 1;
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
n_offset += mutiple * gc;
|
|
n_offset += mutiple * gc;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
cgsleep_ms(50);
|
|
cgsleep_ms(50);
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+ */
|
|
|
|
|
+
|
|
|
if (serial_claim_v(devpath, &futurebit_drv))
|
|
if (serial_claim_v(devpath, &futurebit_drv))
|
|
|
goto err;
|
|
goto err;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
//serial_close(fd);
|
|
//serial_close(fd);
|
|
|
struct cgpu_info * const cgpu = malloc(sizeof(*cgpu));
|
|
struct cgpu_info * const cgpu = malloc(sizeof(*cgpu));
|
|
|
*cgpu = (struct cgpu_info){
|
|
*cgpu = (struct cgpu_info){
|
|
@@ -357,9 +550,9 @@ bool futurebit_detect_one(const char * const devpath)
|
|
|
};
|
|
};
|
|
|
// NOTE: Xcode's clang has a bug where it cannot find fields inside anonymous unions (more details in fpgautils)
|
|
// NOTE: Xcode's clang has a bug where it cannot find fields inside anonymous unions (more details in fpgautils)
|
|
|
cgpu->device_fd = fd;
|
|
cgpu->device_fd = fd;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
return add_cgpu(cgpu);
|
|
return add_cgpu(cgpu);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
err:
|
|
err:
|
|
|
if (fd >= 0)
|
|
if (fd >= 0)
|
|
|
serial_close(fd);
|
|
serial_close(fd);
|
|
@@ -376,29 +569,38 @@ void futurebit_submit_nonce(struct thr_info * const thr, const uint8_t buf[8], s
|
|
|
{
|
|
{
|
|
|
struct cgpu_info *device = thr->cgpu;
|
|
struct cgpu_info *device = thr->cgpu;
|
|
|
struct futurebit_chip *chips = device->device_data;
|
|
struct futurebit_chip *chips = device->device_data;
|
|
|
-
|
|
|
|
|
- uint32_t nonce = *(uint32_t *)buf;
|
|
|
|
|
- nonce = bswap_32(nonce);
|
|
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
|
|
+ uint32_t nonce;
|
|
|
|
|
+
|
|
|
|
|
+ // swab for big endian
|
|
|
|
|
+ memcpy((unsigned char *)&nonce, buf+4, 4);
|
|
|
|
|
+ nonce = htole32(nonce);
|
|
|
|
|
+
|
|
|
|
|
+ char output[(8 * 2) + 1];
|
|
|
|
|
+ bin2hex(output, buf, 8);
|
|
|
|
|
+ applog(LOG_DEBUG, "NONCE %s", output);
|
|
|
|
|
+
|
|
|
submit_nonce(thr, work, nonce);
|
|
submit_nonce(thr, work, nonce);
|
|
|
-
|
|
|
|
|
- // hashrate calc
|
|
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
|
|
+ /* hashrate calc
|
|
|
|
|
+
|
|
|
const uint8_t clstid = buf[7];
|
|
const uint8_t clstid = buf[7];
|
|
|
uint32_t range = chips[0].clst_offset[clstid];
|
|
uint32_t range = chips[0].clst_offset[clstid];
|
|
|
|
|
|
|
|
struct timeval now_tv;
|
|
struct timeval now_tv;
|
|
|
timer_set_now(&now_tv);
|
|
timer_set_now(&now_tv);
|
|
|
int elapsed_ms = ms_tdiff(&now_tv, &start_tv);
|
|
int elapsed_ms = ms_tdiff(&now_tv, &start_tv);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
double total_hashes = ((nonce - range)/9.0) * chips[0].active_cores;
|
|
double total_hashes = ((nonce - range)/9.0) * chips[0].active_cores;
|
|
|
double hashes_per_ms = total_hashes/elapsed_ms;
|
|
double hashes_per_ms = total_hashes/elapsed_ms;
|
|
|
uint64_t hashes = hashes_per_ms * ms_tdiff(&now_tv, &thr->_tv_last_hashes_done_call);
|
|
uint64_t hashes = hashes_per_ms * ms_tdiff(&now_tv, &thr->_tv_last_hashes_done_call);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if(hashes_per_ms < 1500 && hashes < 100000000)
|
|
if(hashes_per_ms < 1500 && hashes < 100000000)
|
|
|
hashes_done2(thr, hashes, NULL);
|
|
hashes_done2(thr, hashes, NULL);
|
|
|
else
|
|
else
|
|
|
hashes_done2(thr, 100000, NULL);
|
|
hashes_done2(thr, 100000, NULL);
|
|
|
|
|
+
|
|
|
|
|
+ */
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
// send work to the device
|
|
// send work to the device
|
|
@@ -409,46 +611,46 @@ int64_t futurebit_scanhash(struct thr_info *thr, struct work *work, int64_t __ma
|
|
|
int fd = device->device_fd;
|
|
int fd = device->device_fd;
|
|
|
struct futurebit_chip *chips = device->device_data;
|
|
struct futurebit_chip *chips = device->device_data;
|
|
|
struct timeval start_tv, nonce_range_tv;
|
|
struct timeval start_tv, nonce_range_tv;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
// amount of time it takes this device to scan a nonce range:
|
|
// amount of time it takes this device to scan a nonce range:
|
|
|
uint32_t nonce_full_range_sec = FUTUREBIT_HASH_SPEED * 352.0 / FUTUREBIT_DEFAULT_FREQUENCY * 54.0 / chips[0].active_cores;
|
|
uint32_t nonce_full_range_sec = FUTUREBIT_HASH_SPEED * 352.0 / FUTUREBIT_DEFAULT_FREQUENCY * 54.0 / chips[0].active_cores;
|
|
|
// timer to break out of scanning should we close in on an entire nonce range
|
|
// timer to break out of scanning should we close in on an entire nonce range
|
|
|
// should break out before the range is scanned, so we are doing 95% of the range
|
|
// should break out before the range is scanned, so we are doing 95% of the range
|
|
|
uint64_t nonce_near_range_usec = (nonce_full_range_sec * 1000000. * 0.95);
|
|
uint64_t nonce_near_range_usec = (nonce_full_range_sec * 1000000. * 0.95);
|
|
|
timer_set_delay_from_now(&nonce_range_tv, nonce_near_range_usec);
|
|
timer_set_delay_from_now(&nonce_range_tv, nonce_near_range_usec);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
// start the job
|
|
// start the job
|
|
|
timer_set_now(&start_tv);
|
|
timer_set_now(&start_tv);
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (!futurebit_send_work(thr, work)) {
|
|
if (!futurebit_send_work(thr, work)) {
|
|
|
applog(LOG_DEBUG, "Failed to start job");
|
|
applog(LOG_DEBUG, "Failed to start job");
|
|
|
dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
- uint8_t buf[8];
|
|
|
|
|
|
|
+
|
|
|
|
|
+ unsigned char buf[12];
|
|
|
int read = 0;
|
|
int read = 0;
|
|
|
bool range_nearly_scanned = false;
|
|
bool range_nearly_scanned = false;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
while (!thr->work_restart // true when new work is available (miner.c)
|
|
while (!thr->work_restart // true when new work is available (miner.c)
|
|
|
- && ((read = serial_read(fd, buf, 8)) >= 0) // only check for failure - allow 0 bytes
|
|
|
|
|
|
|
+ && ((read = serial_read(fd, buf, 8)) >= 0) // only check for failure - allow 0 bytes
|
|
|
&& !(range_nearly_scanned = timer_passed(&nonce_range_tv, NULL))) // true when we've nearly scanned a nonce range
|
|
&& !(range_nearly_scanned = timer_passed(&nonce_range_tv, NULL))) // true when we've nearly scanned a nonce range
|
|
|
{
|
|
{
|
|
|
if (read == 0)
|
|
if (read == 0)
|
|
|
continue;
|
|
continue;
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (read == 8) {
|
|
if (read == 8) {
|
|
|
futurebit_submit_nonce(thr, buf, work, start_tv);
|
|
futurebit_submit_nonce(thr, buf, work, start_tv);
|
|
|
}
|
|
}
|
|
|
else
|
|
else
|
|
|
applog(LOG_ERR, "%"PRIpreprv": Unrecognized response", device->proc_repr);
|
|
applog(LOG_ERR, "%"PRIpreprv": Unrecognized response", device->proc_repr);
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
if (read == -1)
|
|
if (read == -1)
|
|
|
{
|
|
{
|
|
|
applog(LOG_ERR, "%s: Failed to read result", device->dev_repr);
|
|
applog(LOG_ERR, "%s: Failed to read result", device->dev_repr);
|
|
|
dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
|
|
+
|
|
|
return 0;
|
|
return 0;
|
|
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}
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}
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@@ -466,9 +668,9 @@ static
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void futurebit_thread_shutdown(struct thr_info *thr)
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void futurebit_thread_shutdown(struct thr_info *thr)
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{
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{
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struct cgpu_info *device = thr->cgpu;
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struct cgpu_info *device = thr->cgpu;
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-
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+
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futurebit_reset_board(device->device_fd);
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futurebit_reset_board(device->device_fd);
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-
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+
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serial_close(device->device_fd);
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serial_close(device->device_fd);
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}
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}
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@@ -486,14 +688,14 @@ const char *futurebit_set_clock(struct cgpu_info * const device, const char * co
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{
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{
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struct futurebit_chip * const chip = device->device_data;
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struct futurebit_chip * const chip = device->device_data;
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int val = atoi(setting);
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int val = atoi(setting);
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-
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- if (val < FUTUREBIT_MIN_CLOCK || val > FUTUREBIT_MAX_CLOCK || (val%8)) {
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+
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+ if (val < FUTUREBIT_MIN_CLOCK || val > FUTUREBIT_MAX_CLOCK ) {
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sprintf(replybuf, "invalid clock: '%s' valid range %d-%d. Clock must be a mutiple of 8 between 104-200mhz, and a mutiple of 16 between 208-400mhz",
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sprintf(replybuf, "invalid clock: '%s' valid range %d-%d. Clock must be a mutiple of 8 between 104-200mhz, and a mutiple of 16 between 208-400mhz",
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setting, FUTUREBIT_MIN_CLOCK, FUTUREBIT_MAX_CLOCK);
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setting, FUTUREBIT_MIN_CLOCK, FUTUREBIT_MAX_CLOCK);
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return replybuf;
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return replybuf;
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} else
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} else
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chip->freq = val;
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chip->freq = val;
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-
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+
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return NULL;
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return NULL;
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}
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}
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@@ -511,10 +713,10 @@ struct device_drv futurebit_drv = {
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.lowl_probe = futurebit_lowl_probe,
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.lowl_probe = futurebit_lowl_probe,
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// specify mining type - scanhash
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// specify mining type - scanhash
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.minerloop = minerloop_scanhash,
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.minerloop = minerloop_scanhash,
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-
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+
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// scanhash mining hooks
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// scanhash mining hooks
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.scanhash = futurebit_scanhash,
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.scanhash = futurebit_scanhash,
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-
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+
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// teardown device
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// teardown device
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.thread_shutdown = futurebit_thread_shutdown,
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.thread_shutdown = futurebit_thread_shutdown,
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};
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};
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