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@@ -265,6 +265,15 @@ static int avalon_read(int fd, char *buf, ssize_t len)
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return AVA_GETS_OK;
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}
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+/* Wait until the ftdi chip returns a CTS saying we can send more data. The
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+ * status is updated every 40ms. */
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+static void wait_avalon_ready(int fd)
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+{
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+ while (avalon_buffer_full(fd) == AVA_BUFFER_FULL) {
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+ nmsleep(40);
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+ }
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+}
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+
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static int avalon_reset(struct cgpu_info *avalon, int fd)
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{
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struct avalon_result ar;
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@@ -281,6 +290,8 @@ static int avalon_reset(struct cgpu_info *avalon, int fd)
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AVALON_DEFAULT_MINER_NUM,
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0, 0,
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AVALON_DEFAULT_FREQUENCY);
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+
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+ wait_avalon_ready(fd);
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ret = avalon_send_task(fd, &at, NULL);
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if (unlikely(ret == AVA_SEND_ERROR))
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return -1;
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@@ -460,13 +471,6 @@ static void get_options(int this_option_offset, int *baud, int *miner_count,
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}
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}
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-static void wait_avalon_ready(int fd)
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-{
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- while (avalon_buffer_full(fd) == AVA_BUFFER_FULL) {
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- nmsleep(40);
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- }
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-}
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-
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static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info,
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int fd)
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{
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