driver-avalon.c 30 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. static int option_offset = -1;
  41. struct device_drv avalon_drv;
  42. static int avalon_init_task(struct avalon_task *at,
  43. uint8_t reset, uint8_t ff, uint8_t fan,
  44. uint8_t timeout, uint8_t asic_num,
  45. uint8_t miner_num, uint8_t nonce_elf,
  46. uint8_t gate_miner, int frequency)
  47. {
  48. uint8_t *buf;
  49. static bool first = true;
  50. if (unlikely(!at))
  51. return -1;
  52. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  53. return -1;
  54. memset(at, 0, sizeof(struct avalon_task));
  55. if (unlikely(reset)) {
  56. at->reset = 1;
  57. at->fan_eft = 1;
  58. at->timer_eft = 1;
  59. first = true;
  60. }
  61. at->flush_fifo = (ff ? 1 : 0);
  62. at->fan_eft = (fan ? 1 : 0);
  63. if (unlikely(first && !at->reset)) {
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = false;
  67. }
  68. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  69. at->timeout_data = timeout;
  70. at->asic_num = asic_num;
  71. at->miner_num = miner_num;
  72. at->nonce_elf = nonce_elf;
  73. at->gate_miner_elf = 1;
  74. at->asic_pll = 1;
  75. if (unlikely(gate_miner)) {
  76. at-> gate_miner = 1;
  77. at->asic_pll = 0;
  78. }
  79. buf = (uint8_t *)at;
  80. buf[5] = 0x00;
  81. buf[8] = 0x74;
  82. buf[9] = 0x01;
  83. buf[10] = 0x00;
  84. buf[11] = 0x00;
  85. switch (frequency) {
  86. case 256:
  87. buf[6] = 0x03;
  88. buf[7] = 0x08;
  89. break;
  90. default:
  91. case 270:
  92. buf[6] = 0x73;
  93. buf[7] = 0x08;
  94. break;
  95. case 282:
  96. buf[6] = 0xd3;
  97. buf[7] = 0x08;
  98. break;
  99. case 300:
  100. buf[6] = 0x63;
  101. buf[7] = 0x09;
  102. break;
  103. case 325:
  104. buf[6] = 0x28;
  105. buf[7] = 0x0a;
  106. break;
  107. case 350:
  108. buf[6] = 0xf0;
  109. buf[7] = 0x0a;
  110. break;
  111. case 375:
  112. buf[6] = 0xb8;
  113. buf[7] = 0x0b;
  114. break;
  115. }
  116. return 0;
  117. }
  118. static inline void avalon_create_task(struct avalon_task *at,
  119. struct work *work)
  120. {
  121. memcpy(at->midstate, work->midstate, 32);
  122. memcpy(at->data, work->data + 64, 12);
  123. }
  124. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  125. {
  126. int err, amount;
  127. err = usb_write(avalon, buf, len, &amount, ep);
  128. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  129. avalon->device_id, err);
  130. if (unlikely(err != 0)) {
  131. applog(LOG_WARNING, "usb_write error on avalon_write");
  132. return AVA_SEND_ERROR;
  133. }
  134. if (amount != len) {
  135. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  136. return AVA_SEND_ERROR;
  137. }
  138. return AVA_SEND_OK;
  139. }
  140. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  141. {
  142. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  143. int delay, ret, i, ep = C_AVALON_TASK;
  144. struct avalon_info *info;
  145. uint32_t nonce_range;
  146. size_t nr_len;
  147. if (at->nonce_elf)
  148. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  149. else
  150. nr_len = AVALON_WRITE_SIZE;
  151. memcpy(buf, at, AVALON_WRITE_SIZE);
  152. if (at->nonce_elf) {
  153. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  154. for (i = 0; i < at->asic_num; i++) {
  155. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  156. (i * nonce_range & 0xff000000) >> 24;
  157. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  158. (i * nonce_range & 0x00ff0000) >> 16;
  159. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  160. (i * nonce_range & 0x0000ff00) >> 8;
  161. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  162. (i * nonce_range & 0x000000ff) >> 0;
  163. }
  164. }
  165. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  166. uint8_t tt = 0;
  167. tt = (buf[0] & 0x0f) << 4;
  168. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  169. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  170. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  171. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  172. buf[0] = tt;
  173. tt = (buf[4] & 0x0f) << 4;
  174. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  175. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  176. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  177. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  178. buf[4] = tt;
  179. #endif
  180. info = avalon->device_data;
  181. delay = nr_len * 10 * 1000000;
  182. delay = delay / info->baud;
  183. if (at->reset) {
  184. ep = C_AVALON_RESET;
  185. nr_len = 1;
  186. }
  187. if (opt_debug) {
  188. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  189. hexdump(buf, nr_len);
  190. }
  191. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  192. delay += 4000;
  193. nusleep(delay);
  194. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  195. return ret;
  196. }
  197. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  198. struct avalon_info *info, struct avalon_result *ar,
  199. struct work *work)
  200. {
  201. uint32_t nonce;
  202. info = avalon->device_data;
  203. info->matching_work[work->subid]++;
  204. nonce = htole32(ar->nonce);
  205. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  206. return submit_nonce(thr, work, nonce);
  207. }
  208. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  209. static void wait_avalon_ready(struct cgpu_info *avalon)
  210. {
  211. while (avalon_buffer_full(avalon)) {
  212. nmsleep(40);
  213. }
  214. }
  215. #define AVALON_CTS (1 << 4)
  216. static inline bool avalon_cts(char c)
  217. {
  218. return (c & AVALON_CTS);
  219. }
  220. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  221. size_t bufsize, int timeout, int ep)
  222. {
  223. struct avalon_info *info = avalon->device_data;
  224. size_t total = 0, readsize = bufsize + 2;
  225. char readbuf[AVALON_READBUF_SIZE];
  226. int err, amount, ofs = 2, cp;
  227. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  228. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  229. avalon->drv->name, avalon->device_id, err);
  230. if (amount < 2)
  231. goto out;
  232. /* Use the fact that we're reading the status with the buffer to tell
  233. * the write thread it should send more work without needing to call
  234. * avalon_buffer_full directly. */
  235. if (avalon_cts(buf[0]))
  236. cgsem_post(&info->write_sem);
  237. /* The first 2 of every 64 bytes are status on FTDIRL */
  238. while (amount > 2) {
  239. cp = amount - 2;
  240. if (cp > 62)
  241. cp = 62;
  242. memcpy(&buf[total], &readbuf[ofs], cp);
  243. total += cp;
  244. amount -= cp + 2;
  245. ofs += 64;
  246. }
  247. out:
  248. return total;
  249. }
  250. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  251. {
  252. struct avalon_result ar;
  253. int ret, i, spare;
  254. struct avalon_task at;
  255. uint8_t *buf, *tmp;
  256. struct timespec p;
  257. /* Send reset, then check for result */
  258. avalon_init_task(&at, 1, 0,
  259. AVALON_DEFAULT_FAN_MAX_PWM,
  260. AVALON_DEFAULT_TIMEOUT,
  261. AVALON_DEFAULT_ASIC_NUM,
  262. AVALON_DEFAULT_MINER_NUM,
  263. 0, 0,
  264. AVALON_DEFAULT_FREQUENCY);
  265. wait_avalon_ready(avalon);
  266. ret = avalon_send_task(&at, avalon);
  267. if (unlikely(ret == AVA_SEND_ERROR))
  268. return -1;
  269. if (!initial) {
  270. applog(LOG_ERR, "AVA%d reset sequence sent", avalon->device_id);
  271. return 0;
  272. }
  273. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  274. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  275. /* What do these sleeps do?? */
  276. p.tv_sec = 0;
  277. p.tv_nsec = AVALON_RESET_PITCH;
  278. nanosleep(&p, NULL);
  279. /* Look for the first occurrence of 0xAA, the reset response should be:
  280. * AA 55 AA 55 00 00 00 00 00 00 */
  281. spare = ret - 10;
  282. buf = tmp = (uint8_t *)&ar;
  283. if (opt_debug) {
  284. applog(LOG_DEBUG, "AVA%d reset: get:", avalon->device_id);
  285. hexdump(tmp, AVALON_READ_SIZE);
  286. }
  287. for (i = 0; i <= spare; i++) {
  288. buf = &tmp[i];
  289. if (buf[0] == 0xAA)
  290. break;
  291. }
  292. i = 0;
  293. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  294. buf[2] == 0xAA && buf[3] == 0x55) {
  295. for (i = 4; i < 11; i++)
  296. if (buf[i] != 0)
  297. break;
  298. }
  299. if (i != 11) {
  300. applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
  301. " (%d: %02x %02x %02x %02x)", avalon->device_id,
  302. i, buf[0], buf[1], buf[2], buf[3]);
  303. /* FIXME: return 1; */
  304. } else
  305. applog(LOG_WARNING, "AVA%d: Reset succeeded",
  306. avalon->device_id);
  307. return 0;
  308. }
  309. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  310. int *asic_count, int *timeout, int *frequency)
  311. {
  312. char buf[BUFSIZ+1];
  313. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  314. size_t max;
  315. int i, tmp;
  316. if (opt_avalon_options == NULL)
  317. buf[0] = '\0';
  318. else {
  319. ptr = opt_avalon_options;
  320. for (i = 0; i < this_option_offset; i++) {
  321. comma = strchr(ptr, ',');
  322. if (comma == NULL)
  323. break;
  324. ptr = comma + 1;
  325. }
  326. comma = strchr(ptr, ',');
  327. if (comma == NULL)
  328. max = strlen(ptr);
  329. else
  330. max = comma - ptr;
  331. if (max > BUFSIZ)
  332. max = BUFSIZ;
  333. strncpy(buf, ptr, max);
  334. buf[max] = '\0';
  335. }
  336. if (!(*buf))
  337. return false;
  338. colon = strchr(buf, ':');
  339. if (colon)
  340. *(colon++) = '\0';
  341. tmp = atoi(buf);
  342. switch (tmp) {
  343. case 115200:
  344. *baud = 115200;
  345. break;
  346. case 57600:
  347. *baud = 57600;
  348. break;
  349. case 38400:
  350. *baud = 38400;
  351. break;
  352. case 19200:
  353. *baud = 19200;
  354. break;
  355. default:
  356. quit(1, "Invalid avalon-options for baud (%s) "
  357. "must be 115200, 57600, 38400 or 19200", buf);
  358. }
  359. if (colon && *colon) {
  360. colon2 = strchr(colon, ':');
  361. if (colon2)
  362. *(colon2++) = '\0';
  363. if (*colon) {
  364. tmp = atoi(colon);
  365. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  366. *miner_count = tmp;
  367. } else {
  368. quit(1, "Invalid avalon-options for "
  369. "miner_count (%s) must be 1 ~ %d",
  370. colon, AVALON_DEFAULT_MINER_NUM);
  371. }
  372. }
  373. if (colon2 && *colon2) {
  374. colon3 = strchr(colon2, ':');
  375. if (colon3)
  376. *(colon3++) = '\0';
  377. tmp = atoi(colon2);
  378. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  379. *asic_count = tmp;
  380. else {
  381. quit(1, "Invalid avalon-options for "
  382. "asic_count (%s) must be 1 ~ %d",
  383. colon2, AVALON_DEFAULT_ASIC_NUM);
  384. }
  385. if (colon3 && *colon3) {
  386. colon4 = strchr(colon3, ':');
  387. if (colon4)
  388. *(colon4++) = '\0';
  389. tmp = atoi(colon3);
  390. if (tmp > 0 && tmp <= 0xff)
  391. *timeout = tmp;
  392. else {
  393. quit(1, "Invalid avalon-options for "
  394. "timeout (%s) must be 1 ~ %d",
  395. colon3, 0xff);
  396. }
  397. if (colon4 && *colon4) {
  398. tmp = atoi(colon4);
  399. switch (tmp) {
  400. case 256:
  401. case 270:
  402. case 282:
  403. case 300:
  404. case 325:
  405. case 350:
  406. case 375:
  407. *frequency = tmp;
  408. break;
  409. default:
  410. quit(1, "Invalid avalon-options for "
  411. "frequency must be 256/270/282/300/325/350/375");
  412. }
  413. }
  414. }
  415. }
  416. }
  417. return true;
  418. }
  419. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  420. {
  421. int i;
  422. info->idle = true;
  423. wait_avalon_ready(avalon);
  424. /* Send idle to all miners */
  425. for (i = 0; i < info->miner_count; i++) {
  426. struct avalon_task at;
  427. if (unlikely(avalon_buffer_full(avalon)))
  428. break;
  429. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  430. info->asic_count, info->miner_count, 1, 1,
  431. info->frequency);
  432. avalon_send_task(&at, avalon);
  433. }
  434. applog(LOG_WARNING, "AVA%i: Idling %d miners", avalon->device_id, i);
  435. wait_avalon_ready(avalon);
  436. }
  437. static void avalon_initialise(struct cgpu_info *avalon)
  438. {
  439. int err, interface;
  440. if (avalon->usbinfo.nodev)
  441. return;
  442. interface = avalon->usbdev->found->interface;
  443. // Reset
  444. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  445. FTDI_VALUE_RESET, interface, C_RESET);
  446. applog(LOG_DEBUG, "%s%i: reset got err %d",
  447. avalon->drv->name, avalon->device_id, err);
  448. if (avalon->usbinfo.nodev)
  449. return;
  450. // Set latency
  451. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  452. AVALON_LATENCY, interface, C_LATENCY);
  453. applog(LOG_DEBUG, "%s%i: latency got err %d",
  454. avalon->drv->name, avalon->device_id, err);
  455. if (avalon->usbinfo.nodev)
  456. return;
  457. // Set data
  458. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  459. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  460. applog(LOG_DEBUG, "%s%i: data got err %d",
  461. avalon->drv->name, avalon->device_id, err);
  462. if (avalon->usbinfo.nodev)
  463. return;
  464. // Set the baud
  465. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  466. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  467. C_SETBAUD);
  468. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  469. avalon->drv->name, avalon->device_id, err);
  470. if (avalon->usbinfo.nodev)
  471. return;
  472. // Set Modem Control
  473. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  474. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  475. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  476. avalon->drv->name, avalon->device_id, err);
  477. if (avalon->usbinfo.nodev)
  478. return;
  479. // Set Flow Control
  480. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  481. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  482. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  483. avalon->drv->name, avalon->device_id, err);
  484. if (avalon->usbinfo.nodev)
  485. return;
  486. /* Avalon repeats the following */
  487. // Set Modem Control
  488. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  489. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  490. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  491. avalon->drv->name, avalon->device_id, err);
  492. if (avalon->usbinfo.nodev)
  493. return;
  494. // Set Flow Control
  495. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  496. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  497. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  498. avalon->drv->name, avalon->device_id, err);
  499. }
  500. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  501. {
  502. int baud, miner_count, asic_count, timeout, frequency = 0;
  503. int this_option_offset = ++option_offset;
  504. struct avalon_info *info;
  505. struct cgpu_info *avalon;
  506. bool configured;
  507. int ret;
  508. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  509. configured = get_options(this_option_offset, &baud, &miner_count,
  510. &asic_count, &timeout, &frequency);
  511. if (!usb_init(avalon, dev, found))
  512. goto shin;
  513. /* Even though this is an FTDI type chip, we want to do the parsing
  514. * all ourselves so set it to std usb type */
  515. avalon->usbdev->usb_type = USB_TYPE_STD;
  516. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  517. /* We have a real Avalon! */
  518. avalon_initialise(avalon);
  519. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  520. if (unlikely(!(avalon->device_data)))
  521. quit(1, "Failed to calloc avalon_info data");
  522. info = avalon->device_data;
  523. if (configured) {
  524. info->baud = baud;
  525. info->miner_count = miner_count;
  526. info->asic_count = asic_count;
  527. info->timeout = timeout;
  528. info->frequency = frequency;
  529. } else {
  530. info->baud = AVALON_IO_SPEED;
  531. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  532. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  533. info->timeout = AVALON_DEFAULT_TIMEOUT;
  534. info->frequency = AVALON_DEFAULT_FREQUENCY;
  535. }
  536. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  537. info->temp_max = 0;
  538. /* This is for check the temp/fan every 3~4s */
  539. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  540. if (info->temp_history_count <= 0)
  541. info->temp_history_count = 1;
  542. info->temp_history_index = 0;
  543. info->temp_sum = 0;
  544. info->temp_old = 0;
  545. if (!add_cgpu(avalon))
  546. goto unshin;
  547. ret = avalon_reset(avalon, true);
  548. if (ret && !configured)
  549. goto unshin;
  550. update_usb_stats(avalon);
  551. avalon_idle(avalon, info);
  552. applog(LOG_DEBUG, "Avalon Detected: %s "
  553. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  554. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  555. info->frequency);
  556. return true;
  557. unshin:
  558. usb_uninit(avalon);
  559. shin:
  560. free(avalon->device_data);
  561. avalon->device_data = NULL;
  562. avalon = usb_free_cgpu(avalon);
  563. return false;
  564. }
  565. static void avalon_detect(void)
  566. {
  567. usb_detect(&avalon_drv, avalon_detect_one);
  568. }
  569. static void avalon_init(struct cgpu_info *avalon)
  570. {
  571. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  572. }
  573. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  574. {
  575. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  576. (char *)ar->data, 64, 12);
  577. }
  578. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  579. struct avalon_result *ar);
  580. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  581. {
  582. if (unlikely(info->idle))
  583. return;
  584. applog(LOG_INFO, "%s%d: No matching work - HW error",
  585. thr->cgpu->drv->name, thr->cgpu->device_id);
  586. inc_hw_errors(thr);
  587. info->no_matching_work++;
  588. }
  589. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  590. struct thr_info *thr, char *buf, int *offset)
  591. {
  592. int i, spare = *offset - AVALON_READ_SIZE;
  593. bool found = false;
  594. for (i = 0; i <= spare; i++) {
  595. struct avalon_result *ar;
  596. struct work *work;
  597. ar = (struct avalon_result *)&buf[i];
  598. work = avalon_valid_result(avalon, ar);
  599. if (work) {
  600. bool gettemp = false;
  601. found = true;
  602. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  603. mutex_lock(&info->lock);
  604. if (!info->nonces++)
  605. gettemp = true;
  606. mutex_unlock(&info->lock);
  607. }
  608. if (gettemp)
  609. avalon_update_temps(avalon, info, ar);
  610. break;
  611. }
  612. }
  613. if (!found) {
  614. spare = *offset - AVALON_READ_SIZE;
  615. /* We are buffering and haven't accumulated one more corrupt
  616. * work result. */
  617. if (spare < (int)AVALON_READ_SIZE)
  618. return;
  619. avalon_inc_nvw(info, thr);
  620. } else {
  621. spare = AVALON_READ_SIZE + i;
  622. if (i) {
  623. if (i >= (int)AVALON_READ_SIZE)
  624. avalon_inc_nvw(info, thr);
  625. else
  626. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  627. }
  628. }
  629. *offset -= spare;
  630. memmove(buf, buf + spare, *offset);
  631. }
  632. static void avalon_running_reset(struct cgpu_info *avalon,
  633. struct avalon_info *info)
  634. {
  635. avalon_reset(avalon, false);
  636. avalon_idle(avalon, info);
  637. avalon->results = 0;
  638. info->reset = false;
  639. }
  640. static void *avalon_get_results(void *userdata)
  641. {
  642. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  643. struct avalon_info *info = avalon->device_data;
  644. int offset = 0, read_delay = 0, ret = 0;
  645. const int rsize = AVALON_FTDI_READSIZE;
  646. char readbuf[AVALON_READBUF_SIZE];
  647. struct thr_info *thr = info->thr;
  648. struct timeval tv_start, tv_end;
  649. char threadname[24];
  650. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  651. RenameThread(threadname);
  652. while (likely(!avalon->shutdown)) {
  653. unsigned char buf[rsize];
  654. struct timeval tv_diff;
  655. int us_diff;
  656. if (offset >= (int)AVALON_READ_SIZE)
  657. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  658. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  659. /* This should never happen */
  660. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  661. offset = 0;
  662. }
  663. if (unlikely(info->reset)) {
  664. avalon_running_reset(avalon, info);
  665. /* Discard anything in the buffer */
  666. offset = 0;
  667. }
  668. /* As the usb read returns after just 1ms, sleep long enough
  669. * to leave the interface idle for writes to occur, but do not
  670. * sleep if we have been receiving data as more may be coming. */
  671. if (ret < 1) {
  672. cgtime(&tv_end);
  673. timersub(&tv_end, &tv_start, &tv_diff);
  674. /* Assume it has not been > 1 second so ignore tv_sec */
  675. us_diff = tv_diff.tv_usec;
  676. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  677. if (likely(read_delay >= 1000))
  678. nusleep(read_delay);
  679. }
  680. cgtime(&tv_start);
  681. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  682. C_AVALON_READ);
  683. if (ret < 1)
  684. continue;
  685. if (opt_debug) {
  686. applog(LOG_DEBUG, "Avalon: get:");
  687. hexdump((uint8_t *)buf, ret);
  688. }
  689. memcpy(&readbuf[offset], &buf, ret);
  690. offset += ret;
  691. }
  692. return NULL;
  693. }
  694. static void avalon_rotate_array(struct cgpu_info *avalon)
  695. {
  696. avalon->queued = 0;
  697. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  698. avalon->work_array = 0;
  699. }
  700. static void *avalon_send_tasks(void *userdata)
  701. {
  702. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  703. struct avalon_info *info = avalon->device_data;
  704. const int avalon_get_work_count = info->miner_count;
  705. char threadname[24];
  706. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  707. RenameThread(threadname);
  708. while (likely(!avalon->shutdown)) {
  709. int start_count, end_count, i, j, ret;
  710. struct avalon_task at;
  711. int idled = 0;
  712. while (avalon_buffer_full(avalon))
  713. cgsem_wait(&info->write_sem);
  714. mutex_lock(&info->qlock);
  715. start_count = avalon->work_array * avalon_get_work_count;
  716. end_count = start_count + avalon_get_work_count;
  717. for (i = start_count, j = 0; i < end_count; i++, j++) {
  718. if (avalon_buffer_full(avalon)) {
  719. applog(LOG_INFO,
  720. "AVA%i: Buffer full after only %d of %d work queued",
  721. avalon->device_id, j, avalon_get_work_count);
  722. break;
  723. }
  724. if (likely(j < avalon->queued)) {
  725. info->idle = false;
  726. avalon_init_task(&at, 0, 0, info->fan_pwm,
  727. info->timeout, info->asic_count,
  728. info->miner_count, 1, 0, info->frequency);
  729. avalon_create_task(&at, avalon->works[i]);
  730. } else {
  731. idled++;
  732. avalon_init_task(&at, 0, 0, info->fan_pwm,
  733. info->timeout, info->asic_count,
  734. info->miner_count, 1, 1, info->frequency);
  735. }
  736. ret = avalon_send_task(&at, avalon);
  737. if (unlikely(ret == AVA_SEND_ERROR)) {
  738. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  739. avalon->device_id);
  740. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  741. info->reset = true;
  742. break;
  743. }
  744. }
  745. avalon_rotate_array(avalon);
  746. pthread_cond_signal(&info->qcond);
  747. mutex_unlock(&info->qlock);
  748. if (unlikely(idled && !info->idle)) {
  749. info->idle = true;
  750. applog(LOG_WARNING, "AVA%i: Idled %d miners",
  751. avalon->device_id, idled);
  752. }
  753. }
  754. return NULL;
  755. }
  756. static bool avalon_prepare(struct thr_info *thr)
  757. {
  758. struct cgpu_info *avalon = thr->cgpu;
  759. struct avalon_info *info = avalon->device_data;
  760. struct timeval now;
  761. free(avalon->works);
  762. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  763. AVALON_ARRAY_SIZE);
  764. if (!avalon->works)
  765. quit(1, "Failed to calloc avalon works in avalon_prepare");
  766. info->thr = thr;
  767. mutex_init(&info->lock);
  768. mutex_init(&info->qlock);
  769. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  770. quit(1, "Failed to pthread_cond_init avalon qcond");
  771. cgsem_init(&info->write_sem);
  772. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  773. quit(1, "Failed to create avalon read_thr");
  774. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  775. quit(1, "Failed to create avalon write_thr");
  776. avalon_init(avalon);
  777. cgtime(&now);
  778. get_datestamp(avalon->init, &now);
  779. return true;
  780. }
  781. static void do_avalon_close(struct thr_info *thr)
  782. {
  783. struct cgpu_info *avalon = thr->cgpu;
  784. struct avalon_info *info = avalon->device_data;
  785. pthread_join(info->read_thr, NULL);
  786. pthread_join(info->write_thr, NULL);
  787. avalon_running_reset(avalon, info);
  788. info->no_matching_work = 0;
  789. cgsem_destroy(&info->write_sem);
  790. }
  791. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  792. {
  793. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  794. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  795. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  796. info->temp0 = ar->temp0;
  797. info->temp1 = ar->temp1;
  798. info->temp2 = ar->temp2;
  799. if (ar->temp0 & 0x80) {
  800. ar->temp0 &= 0x7f;
  801. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  802. }
  803. if (ar->temp1 & 0x80) {
  804. ar->temp1 &= 0x7f;
  805. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  806. }
  807. if (ar->temp2 & 0x80) {
  808. ar->temp2 &= 0x7f;
  809. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  810. }
  811. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  812. if (info->temp0 > info->temp_max)
  813. info->temp_max = info->temp0;
  814. if (info->temp1 > info->temp_max)
  815. info->temp_max = info->temp1;
  816. if (info->temp2 > info->temp_max)
  817. info->temp_max = info->temp2;
  818. }
  819. static void temp_rise(struct avalon_info *info, int temp)
  820. {
  821. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  822. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  823. return;
  824. }
  825. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  826. info->fan_pwm += 10;
  827. else if (temp > opt_avalon_temp)
  828. info->fan_pwm += 5;
  829. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  830. info->fan_pwm += 1;
  831. else
  832. return;
  833. if (info->fan_pwm > AVALON_DEFAULT_FAN_MAX_PWM)
  834. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  835. }
  836. static void temp_drop(struct avalon_info *info, int temp)
  837. {
  838. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  839. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  840. return;
  841. }
  842. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  843. info->fan_pwm -= 10;
  844. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  845. info->fan_pwm -= 5;
  846. else if (temp < opt_avalon_temp)
  847. info->fan_pwm -= 1;
  848. if (info->fan_pwm < AVALON_DEFAULT_FAN_MIN_PWM)
  849. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  850. }
  851. static inline void adjust_fan(struct avalon_info *info)
  852. {
  853. int temp_new;
  854. temp_new = info->temp_sum / info->temp_history_count;
  855. if (temp_new > info->temp_old)
  856. temp_rise(info, temp_new);
  857. else if (temp_new < info->temp_old)
  858. temp_drop(info, temp_new);
  859. else {
  860. /* temp_new == info->temp_old */
  861. if (temp_new > opt_avalon_temp)
  862. temp_rise(info, temp_new);
  863. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  864. temp_drop(info, temp_new);
  865. }
  866. info->temp_old = temp_new;
  867. }
  868. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  869. struct avalon_result *ar)
  870. {
  871. record_temp_fan(info, ar, &(avalon->temp));
  872. applog(LOG_INFO,
  873. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  874. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  875. info->fan0, info->fan1, info->fan2,
  876. info->temp0, info->temp1, info->temp2, info->temp_max);
  877. info->temp_history_index++;
  878. info->temp_sum += avalon->temp;
  879. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  880. info->temp_history_index, info->temp_history_count, info->temp_old);
  881. if (info->temp_history_index == info->temp_history_count) {
  882. adjust_fan(info);
  883. info->temp_history_index = 0;
  884. info->temp_sum = 0;
  885. }
  886. }
  887. static void get_avalon_statline_before(char *buf, struct cgpu_info *avalon)
  888. {
  889. struct avalon_info *info = avalon->device_data;
  890. int lowfan = 10000;
  891. /* Find the lowest fan speed of the ASIC cooling fans. */
  892. if (info->fan1 >= 0 && info->fan1 < lowfan)
  893. lowfan = info->fan1;
  894. if (info->fan2 >= 0 && info->fan2 < lowfan)
  895. lowfan = info->fan2;
  896. tailsprintf(buf, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  897. }
  898. /* We use a replacement algorithm to only remove references to work done from
  899. * the buffer when we need the extra space for new work. */
  900. static bool avalon_fill(struct cgpu_info *avalon)
  901. {
  902. struct avalon_info *info = avalon->device_data;
  903. int subid, slot, mc;
  904. struct work *work;
  905. bool ret = true;
  906. mc = info->miner_count;
  907. mutex_lock(&info->qlock);
  908. if (avalon->queued >= mc)
  909. goto out_unlock;
  910. work = get_queued(avalon);
  911. if (unlikely(!work)) {
  912. ret = false;
  913. goto out_unlock;
  914. }
  915. subid = avalon->queued++;
  916. work->subid = subid;
  917. slot = avalon->work_array * mc + subid;
  918. if (likely(avalon->works[slot]))
  919. work_completed(avalon, avalon->works[slot]);
  920. avalon->works[slot] = work;
  921. if (avalon->queued < mc)
  922. ret = false;
  923. out_unlock:
  924. mutex_unlock(&info->qlock);
  925. return ret;
  926. }
  927. static int64_t avalon_scanhash(struct thr_info *thr)
  928. {
  929. struct cgpu_info *avalon = thr->cgpu;
  930. struct avalon_info *info = avalon->device_data;
  931. const int miner_count = info->miner_count;
  932. struct timeval now, then, tdiff;
  933. int64_t hash_count, us_timeout;
  934. struct timespec abstime;
  935. /* Half nonce range */
  936. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  937. tdiff.tv_sec = us_timeout / 1000000;
  938. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  939. cgtime(&now);
  940. timeradd(&now, &tdiff, &then);
  941. abstime.tv_sec = then.tv_sec;
  942. abstime.tv_nsec = then.tv_usec * 1000;
  943. /* Wait until avalon_send_tasks signals us that it has completed
  944. * sending its work or a full nonce range timeout has occurred */
  945. mutex_lock(&info->qlock);
  946. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  947. mutex_unlock(&info->qlock);
  948. mutex_lock(&info->lock);
  949. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  950. avalon->results += info->nonces;
  951. if (avalon->results > miner_count)
  952. avalon->results = miner_count;
  953. if (!info->idle && !info->reset)
  954. avalon->results -= miner_count / 3;
  955. else
  956. avalon->results = miner_count;
  957. info->nonces = 0;
  958. mutex_unlock(&info->lock);
  959. /* Check for nothing but consecutive bad results or consistently less
  960. * results than we should be getting and reset the FPGA if necessary */
  961. if (avalon->results < -miner_count && !info->reset) {
  962. applog(LOG_ERR, "AVA%d: Result return rate low, resetting!",
  963. avalon->device_id);
  964. info->reset = true;
  965. }
  966. if (unlikely(avalon->usbinfo.nodev)) {
  967. applog(LOG_ERR, "AVA%d: Device disappeared, shutting down thread",
  968. avalon->device_id);
  969. avalon->shutdown = true;
  970. }
  971. /* This hashmeter is just a utility counter based on returned shares */
  972. return hash_count;
  973. }
  974. static void avalon_flush_work(struct cgpu_info *avalon)
  975. {
  976. struct avalon_info *info = avalon->device_data;
  977. mutex_lock(&info->qlock);
  978. /* Will overwrite any work queued */
  979. avalon->queued = 0;
  980. pthread_cond_signal(&info->qcond);
  981. mutex_unlock(&info->qlock);
  982. }
  983. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  984. {
  985. struct api_data *root = NULL;
  986. struct avalon_info *info = cgpu->device_data;
  987. int i;
  988. root = api_add_int(root, "baud", &(info->baud), false);
  989. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  990. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  991. root = api_add_int(root, "timeout", &(info->timeout), false);
  992. root = api_add_int(root, "frequency", &(info->frequency), false);
  993. root = api_add_int(root, "fan1", &(info->fan0), false);
  994. root = api_add_int(root, "fan2", &(info->fan1), false);
  995. root = api_add_int(root, "fan3", &(info->fan2), false);
  996. root = api_add_int(root, "temp1", &(info->temp0), false);
  997. root = api_add_int(root, "temp2", &(info->temp1), false);
  998. root = api_add_int(root, "temp3", &(info->temp2), false);
  999. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1000. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1001. for (i = 0; i < info->miner_count; i++) {
  1002. char mcw[24];
  1003. sprintf(mcw, "match_work_count%d", i + 1);
  1004. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1005. }
  1006. return root;
  1007. }
  1008. static void avalon_shutdown(struct thr_info *thr)
  1009. {
  1010. do_avalon_close(thr);
  1011. }
  1012. struct device_drv avalon_drv = {
  1013. .drv_id = DRIVER_AVALON,
  1014. .dname = "avalon",
  1015. .name = "AVA",
  1016. .drv_detect = avalon_detect,
  1017. .thread_prepare = avalon_prepare,
  1018. .hash_work = hash_queued_work,
  1019. .queue_full = avalon_fill,
  1020. .scanwork = avalon_scanhash,
  1021. .flush_work = avalon_flush_work,
  1022. .get_api_stats = avalon_api_stats,
  1023. .get_statline_before = get_avalon_statline_before,
  1024. .reinit_device = avalon_init,
  1025. .thread_shutdown = avalon_shutdown,
  1026. };