driver-avalon.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857
  1. /*
  2. * Copyright 2012 Luke Dashjr
  3. * Copyright 2012 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. /*
  12. * Those code should be works fine with V2 and V3 bitstream of Avalon.
  13. * Operation:
  14. * No detection implement.
  15. * Input: 64B = 32B midstate + 20B fill bytes + last 12 bytes of block head.
  16. * Return: send back 32bits immediately when Avalon found a valid nonce.
  17. * no query protocol implemented here, if no data send back in ~11.3
  18. * seconds (full cover time on 32bit nonce range by 380MH/s speed)
  19. * just send another work.
  20. * Notice:
  21. * 1. Avalon will start calculate when you push a work to them, even they
  22. * are busy.
  23. * 2. The 2 FPGAs on Avalon will distribute the job, one will calculate the
  24. * 0 ~ 7FFFFFFF, another one will cover the 80000000 ~ FFFFFFFF.
  25. * 3. It's possible for 2 FPGAs both find valid nonce in the meantime, the 2
  26. * valid nonce will all be send back.
  27. * 4. Avalon will stop work when: a valid nonce has been found or 32 bits
  28. * nonce range is completely calculated.
  29. */
  30. #include "config.h"
  31. #include <limits.h>
  32. #include <pthread.h>
  33. #include <stdio.h>
  34. #include <sys/time.h>
  35. #include <sys/types.h>
  36. #include <dirent.h>
  37. #include <unistd.h>
  38. #ifndef WIN32
  39. #include <termios.h>
  40. #include <sys/stat.h>
  41. #include <fcntl.h>
  42. #ifndef O_CLOEXEC
  43. #define O_CLOEXEC 0
  44. #endif
  45. #else
  46. #include <windows.h>
  47. #include <io.h>
  48. #endif
  49. #include "elist.h"
  50. #include "miner.h"
  51. #include "fpgautils.h"
  52. #include "driver-avalon.h"
  53. static struct timeval history_sec = { HISTORY_SEC, 0 };
  54. static const char *MODE_DEFAULT_STR = "default";
  55. static const char *MODE_SHORT_STR = "short";
  56. static const char *MODE_LONG_STR = "long";
  57. static const char *MODE_VALUE_STR = "value";
  58. static const char *MODE_UNKNOWN_STR = "unknown";
  59. // One for each possible device
  60. static struct AVALON_INFO **avalon_info;
  61. // Looking for options in --avalon-timing and --avalon-options:
  62. //
  63. // Code increments this each time we start to look at a device
  64. // However, this means that if other devices are checked by
  65. // the Avalon code (e.g. BFL) they will count in the option offset
  66. //
  67. // This, however, is deterministic so that's OK
  68. //
  69. // If we were to increment after successfully finding an Avalon
  70. // that would be random since an Avalon may fail and thus we'd
  71. // not be able to predict the option order
  72. //
  73. // This also assumes that serial_detect() checks them sequentially
  74. // and in the order specified on the command line
  75. //
  76. static int option_offset = -1;
  77. struct device_api avalon_api;
  78. static void rev(uint8_t *s, size_t l)
  79. {
  80. size_t i, j;
  81. uint8_t t;
  82. for (i = 0, j = l - 1; i < j; i++, j--) {
  83. t = s[i];
  84. s[i] = s[j];
  85. s[j] = t;
  86. }
  87. }
  88. static inline void avalon_create_task(uint8_t *ob_bin, struct work *work)
  89. {
  90. memset(ob_bin, 0, sizeof(ob_bin));
  91. memcpy(ob_bin, work->midstate, 32);
  92. memcpy(ob_bin + 52, work->data + 64, 12);
  93. rev(ob_bin, 32);
  94. rev(ob_bin + 52, 12);
  95. }
  96. static int avalon_gets(uint8_t *buf, int fd, struct timeval *tv_finish,
  97. struct thr_info *thr, int read_count)
  98. {
  99. ssize_t ret = 0;
  100. int rc = 0;
  101. int read_amount = AVALON_READ_SIZE;
  102. bool first = true;
  103. int cts = get_serial_cts(fd);
  104. if (opt_debug)
  105. applog(LOG_DEBUG, "Avalon bulk task statue: %d", cts);
  106. if (cts) {
  107. /* TODO return here. and tell avalon all task are done */
  108. }
  109. // Read reply 1 byte at a time to get earliest tv_finish
  110. while (true) {
  111. ret = read(fd, buf, 1);
  112. if (ret < 0)
  113. return AVA_GETS_ERROR;
  114. if (first)
  115. gettimeofday(tv_finish, NULL);
  116. if (ret >= read_amount)
  117. return AVA_GETS_OK;
  118. if (ret > 0) {
  119. buf += ret;
  120. read_amount -= ret;
  121. first = false;
  122. continue;
  123. }
  124. rc++;
  125. if (rc >= read_count) {
  126. if (opt_debug) {
  127. applog(LOG_DEBUG,
  128. "Avalon Read: No data in %.2f seconds",
  129. (float)rc/(float)TIME_FACTOR);
  130. }
  131. return AVA_GETS_TIMEOUT;
  132. }
  133. if (thr && thr->work_restart) {
  134. if (opt_debug) {
  135. applog(LOG_DEBUG,
  136. "Avalon Read: Work restart at %.2f seconds",
  137. (float)(rc)/(float)TIME_FACTOR);
  138. }
  139. return AVA_GETS_RESTART;
  140. }
  141. }
  142. }
  143. static int avalon_read_work(uint8_t *nonce_bin, int fd,
  144. struct timeval *tv_finish, struct thr_info *thr)
  145. {
  146. /* TODO: create a globle buffer match that buffer retrun the work*/
  147. struct cgpu_info *avalon = thr->cgpu;
  148. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  149. int ret;
  150. memset(nonce_bin, 0, AVALON_READ_SIZE);
  151. ret = avalon_gets(nonce_bin, fd, tv_finish, thr, info->read_count);
  152. return ret;
  153. }
  154. static int avalon_submit_nonce(uint8_t *ob_bin)
  155. {
  156. return 0;
  157. }
  158. static int avalon_send_task(int fd, const void *buf, size_t bufLen)
  159. {
  160. size_t ret;
  161. ret = write(fd, buf, bufLen);
  162. if (unlikely(ret != bufLen))
  163. return 1;
  164. return 0;
  165. }
  166. #define avalon_close(fd) close(fd)
  167. static void do_avalon_close(struct thr_info *thr)
  168. {
  169. struct cgpu_info *avalon = thr->cgpu;
  170. avalon_close(avalon->device_fd);
  171. avalon->device_fd = -1;
  172. }
  173. static const char *timing_mode_str(enum timing_mode timing_mode)
  174. {
  175. switch(timing_mode) {
  176. case MODE_DEFAULT:
  177. return MODE_DEFAULT_STR;
  178. case MODE_SHORT:
  179. return MODE_SHORT_STR;
  180. case MODE_LONG:
  181. return MODE_LONG_STR;
  182. case MODE_VALUE:
  183. return MODE_VALUE_STR;
  184. default:
  185. return MODE_UNKNOWN_STR;
  186. }
  187. }
  188. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  189. {
  190. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  191. double Hs;
  192. char buf[BUFSIZ+1];
  193. char *ptr, *comma, *eq;
  194. size_t max;
  195. int i;
  196. if (opt_icarus_timing == NULL)
  197. buf[0] = '\0';
  198. else {
  199. ptr = opt_icarus_timing;
  200. for (i = 0; i < this_option_offset; i++) {
  201. comma = strchr(ptr, ',');
  202. if (comma == NULL)
  203. break;
  204. ptr = comma + 1;
  205. }
  206. comma = strchr(ptr, ',');
  207. if (comma == NULL)
  208. max = strlen(ptr);
  209. else
  210. max = comma - ptr;
  211. if (max > BUFSIZ)
  212. max = BUFSIZ;
  213. strncpy(buf, ptr, max);
  214. buf[max] = '\0';
  215. }
  216. info->Hs = 0;
  217. info->read_count = 0;
  218. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  219. info->Hs = AVALON_REV3_HASH_TIME;
  220. info->read_count = AVALON_READ_COUNT_TIMING;
  221. info->timing_mode = MODE_SHORT;
  222. info->do_avalon_timing = true;
  223. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  224. info->Hs = AVALON_REV3_HASH_TIME;
  225. info->read_count = AVALON_READ_COUNT_TIMING;
  226. info->timing_mode = MODE_LONG;
  227. info->do_avalon_timing = true;
  228. } else if ((Hs = atof(buf)) != 0) {
  229. info->Hs = Hs / NANOSEC;
  230. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  231. if ((eq = strchr(buf, '=')) != NULL)
  232. info->read_count = atoi(eq+1);
  233. if (info->read_count < 1)
  234. info->read_count =
  235. (int)(info->fullnonce * TIME_FACTOR) - 1;
  236. if (unlikely(info->read_count < 1))
  237. info->read_count = 1;
  238. info->timing_mode = MODE_VALUE;
  239. info->do_avalon_timing = false;
  240. } else {
  241. // Anything else in buf just uses DEFAULT mode
  242. info->Hs = AVALON_REV3_HASH_TIME;
  243. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  244. if ((eq = strchr(buf, '=')) != NULL)
  245. info->read_count = atoi(eq+1);
  246. if (info->read_count < 1)
  247. info->read_count =
  248. (int)(info->fullnonce * TIME_FACTOR) - 1;
  249. info->timing_mode = MODE_DEFAULT;
  250. info->do_avalon_timing = false;
  251. }
  252. info->min_data_count = MIN_DATA_COUNT;
  253. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  254. avalon->device_id, timing_mode_str(info->timing_mode),
  255. info->read_count, info->Hs);
  256. }
  257. static uint32_t mask(int work_division)
  258. {
  259. char err_buf[BUFSIZ+1];
  260. uint32_t nonce_mask = 0x7fffffff;
  261. // yes we can calculate these,
  262. // but this way it's easy to see what they are
  263. switch (work_division) {
  264. case 1:
  265. nonce_mask = 0xffffffff;
  266. break;
  267. case 2:
  268. nonce_mask = 0x7fffffff;
  269. break;
  270. case 4:
  271. nonce_mask = 0x3fffffff;
  272. break;
  273. case 8:
  274. nonce_mask = 0x1fffffff;
  275. break;
  276. default:
  277. sprintf(err_buf,
  278. "Invalid2 avalon-options for work_division (%d)"
  279. " must be 1, 2, 4 or 8", work_division);
  280. quit(1, err_buf);
  281. }
  282. return nonce_mask;
  283. }
  284. static void get_options(int this_option_offset, int *baud, int *work_division,
  285. int *asic_count)
  286. {
  287. char err_buf[BUFSIZ+1];
  288. char buf[BUFSIZ+1];
  289. char *ptr, *comma, *colon, *colon2;
  290. size_t max;
  291. int i, tmp;
  292. if (opt_icarus_options == NULL)
  293. buf[0] = '\0';
  294. else {
  295. ptr = opt_icarus_options;
  296. for (i = 0; i < this_option_offset; i++) {
  297. comma = strchr(ptr, ',');
  298. if (comma == NULL)
  299. break;
  300. ptr = comma + 1;
  301. }
  302. comma = strchr(ptr, ',');
  303. if (comma == NULL)
  304. max = strlen(ptr);
  305. else
  306. max = comma - ptr;
  307. if (max > BUFSIZ)
  308. max = BUFSIZ;
  309. strncpy(buf, ptr, max);
  310. buf[max] = '\0';
  311. }
  312. *baud = AVALON_IO_SPEED;
  313. *work_division = 2;
  314. *asic_count = 2;
  315. if (*buf) {
  316. colon = strchr(buf, ':');
  317. if (colon)
  318. *(colon++) = '\0';
  319. if (*buf) {
  320. tmp = atoi(buf);
  321. switch (tmp) {
  322. case 115200:
  323. *baud = 115200;
  324. break;
  325. case 57600:
  326. *baud = 57600;
  327. break;
  328. default:
  329. sprintf(err_buf,
  330. "Invalid avalon-options for baud (%s) "
  331. "must be 115200 or 57600", buf);
  332. quit(1, err_buf);
  333. }
  334. }
  335. if (colon && *colon) {
  336. colon2 = strchr(colon, ':');
  337. if (colon2)
  338. *(colon2++) = '\0';
  339. if (*colon) {
  340. tmp = atoi(colon);
  341. if (tmp == 1 || tmp == 2 ||
  342. tmp == 4 || tmp == 8) {
  343. *work_division = tmp;
  344. // default to the same
  345. *asic_count = tmp;
  346. } else {
  347. sprintf(err_buf,
  348. "Invalid avalon-options for "
  349. "work_division (%s) must be 1,"
  350. " 2, 4 or 8", colon);
  351. quit(1, err_buf);
  352. }
  353. }
  354. if (colon2 && *colon2) {
  355. tmp = atoi(colon2);
  356. if (tmp > 0 && tmp <= *work_division)
  357. *asic_count = tmp;
  358. else {
  359. sprintf(err_buf,
  360. "Invalid avalon-options for "
  361. "asic_count (%s) must be >0 "
  362. "and <=work_division (%d)",
  363. colon2, *work_division);
  364. quit(1, err_buf);
  365. }
  366. }
  367. }
  368. }
  369. }
  370. static bool avalon_detect_one(const char *devpath)
  371. {
  372. int this_option_offset = ++option_offset;
  373. struct AVALON_INFO *info;
  374. struct timeval tv_start, tv_finish;
  375. int fd;
  376. // Block 171874 nonce = (0xa2870100) = 0x000187a2
  377. // N.B. golden_ob MUST take less time to calculate
  378. // than the timeout set in avalon_open()
  379. // This one takes ~0.53ms on Rev3 Avalon
  380. const char golden_ob[] =
  381. "4679ba4ec99876bf4bfe086082b40025"
  382. "4df6c356451471139a3afa71e48f544a"
  383. "00000000000000000000000000000000"
  384. "0000000087320b1a1426674f2fa722ce";
  385. const char golden_nonce[] = "000187a2";
  386. const uint32_t golden_nonce_val = 0x000187a2;
  387. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  388. char *nonce_hex;
  389. int baud, work_division, asic_count;
  390. get_options(this_option_offset, &baud, &work_division, &asic_count);
  391. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  392. fd = avalon_open2(devpath, baud, true);
  393. if (unlikely(fd == -1)) {
  394. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  395. return false;
  396. }
  397. hex2bin(ob_bin, golden_ob, sizeof(ob_bin));
  398. avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  399. gettimeofday(&tv_start, NULL);
  400. memset(nonce_bin, 0, sizeof(nonce_bin));
  401. avalon_gets(nonce_bin, fd, &tv_finish, NULL, 1);
  402. avalon_close(fd);
  403. nonce_hex = bin2hex(nonce_bin, sizeof(nonce_bin));
  404. if (strncmp(nonce_hex, golden_nonce, 8)) {
  405. applog(LOG_ERR,
  406. "Avalon Detect: "
  407. "Test failed at %s: get %s, should: %s",
  408. devpath, nonce_hex, golden_nonce);
  409. free(nonce_hex);
  410. return false;
  411. }
  412. applog(LOG_DEBUG,
  413. "Avalon Detect: "
  414. "Test succeeded at %s: got %s",
  415. devpath, nonce_hex);
  416. free(nonce_hex);
  417. /* We have a real Avalon! */
  418. struct cgpu_info *avalon;
  419. avalon = calloc(1, sizeof(struct cgpu_info));
  420. avalon->api = &avalon_api;
  421. avalon->device_path = strdup(devpath);
  422. avalon->device_fd = -1;
  423. avalon->threads = AVALON_MINER_THREADS;
  424. add_cgpu(avalon);
  425. avalon_info = realloc(avalon_info,
  426. sizeof(struct AVALON_INFO *) *
  427. (total_devices + 1));
  428. applog(LOG_INFO, "Found Avalon at %s, mark as %d",
  429. devpath, avalon->device_id);
  430. applog(LOG_DEBUG,
  431. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  432. avalon->device_id, baud, work_division, asic_count);
  433. // Since we are adding a new device on the end it
  434. // needs to always be allocated
  435. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  436. malloc(sizeof(struct AVALON_INFO));
  437. if (unlikely(!(avalon_info[avalon->device_id])))
  438. quit(1, "Failed to malloc AVALON_INFO");
  439. info = avalon_info[avalon->device_id];
  440. // Initialise everything to zero for a new device
  441. memset(info, 0, sizeof(struct AVALON_INFO));
  442. info->baud = baud;
  443. info->work_division = work_division;
  444. info->asic_count = asic_count;
  445. info->nonce_mask = mask(work_division);
  446. info->golden_hashes = (golden_nonce_val & info->nonce_mask) *
  447. asic_count;
  448. timersub(&tv_finish, &tv_start, &(info->golden_tv));
  449. set_timing_mode(this_option_offset, avalon);
  450. return true;
  451. }
  452. static void avalon_detect()
  453. {
  454. serial_detect(&avalon_api, avalon_detect_one);
  455. }
  456. static bool avalon_prepare(struct thr_info *thr)
  457. {
  458. struct cgpu_info *avalon = thr->cgpu;
  459. struct timeval now;
  460. avalon->device_fd = -1;
  461. int fd = avalon_open(avalon->device_path,
  462. avalon_info[avalon->device_id]->baud);
  463. if (unlikely(-1 == fd)) {
  464. applog(LOG_ERR, "Failed to open Avalon on %s",
  465. avalon->device_path);
  466. return false;
  467. }
  468. avalon->device_fd = fd;
  469. applog(LOG_INFO, "Opened Avalon on %s", avalon->device_path);
  470. gettimeofday(&now, NULL);
  471. get_datestamp(avalon->init, &now);
  472. return true;
  473. }
  474. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  475. __maybe_unused int64_t max_nonce)
  476. {
  477. struct cgpu_info *avalon;
  478. int fd;
  479. int ret;
  480. struct AVALON_INFO *info;
  481. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  482. char *ob_hex;
  483. uint32_t nonce;
  484. int64_t hash_count;
  485. struct timeval tv_start, tv_finish, elapsed;
  486. struct timeval tv_history_start, tv_history_finish;
  487. double Ti, Xi;
  488. int curr_hw_errors, i;
  489. bool was_hw_error;
  490. struct AVALON_HISTORY *history0, *history;
  491. int count;
  492. double Hs, W, fullnonce;
  493. int read_count;
  494. int64_t estimate_hashes;
  495. uint32_t values;
  496. int64_t hash_count_range;
  497. elapsed.tv_sec = elapsed.tv_usec = 0;
  498. info = avalon_info[avalon->device_id];
  499. avalon = thr->cgpu;
  500. if (avalon->device_fd == -1)
  501. if (!avalon_prepare(thr)) {
  502. applog(LOG_ERR, "AVA%i: Comms error",
  503. avalon->device_id);
  504. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  505. // fail the device if the reopen attempt fails
  506. return -1;
  507. }
  508. fd = avalon->device_fd;
  509. #ifndef WIN32
  510. tcflush(fd, TCOFLUSH);
  511. #endif
  512. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  513. avalon_create_task(ob_bin, work[i]);
  514. ret = avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  515. if (ret) {
  516. do_avalon_close(thr);
  517. applog(LOG_ERR, "AVA%i: Comms error",
  518. avalon->device_id);
  519. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  520. return 0; /* This should never happen */
  521. }
  522. }
  523. if (opt_debug) {
  524. ob_hex = bin2hex(ob_bin, sizeof(ob_bin));
  525. applog(LOG_DEBUG, "Avalon %d sent: %s",
  526. avalon->device_id, ob_hex);
  527. free(ob_hex);
  528. }
  529. gettimeofday(&tv_start, NULL);
  530. /* FIXME: all read should be in another function
  531. Avalon return: reserved_nonce_midstate_data,
  532. count != AVALON_GET_WORK_COUNT */
  533. ret = avalon_read_work(nonce_bin, fd, &tv_finish, thr);
  534. if (ret == AVA_GETS_ERROR ) {
  535. do_avalon_close(thr);
  536. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  537. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  538. return 0;
  539. }
  540. work[0]->blk.nonce = 0xffffffff;
  541. // aborted before becoming idle, get new work
  542. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  543. timersub(&tv_finish, &tv_start, &elapsed);
  544. // ONLY up to just when it aborted
  545. // We didn't read a reply so we don't subtract AVALON_READ_TIME
  546. estimate_hashes = ((double)(elapsed.tv_sec) +
  547. ((double)(elapsed.tv_usec)) /
  548. ((double)1000000)) / info->Hs;
  549. // If some Serial-USB delay allowed the full nonce range to
  550. // complete it can't have done more than a full nonce
  551. if (unlikely(estimate_hashes > 0xffffffff))
  552. estimate_hashes = 0xffffffff;
  553. if (opt_debug) {
  554. applog(LOG_DEBUG,
  555. "Avalon %d no nonce = 0x%08llx hashes "
  556. "(%ld.%06lds)",
  557. avalon->device_id, estimate_hashes,
  558. elapsed.tv_sec, elapsed.tv_usec);
  559. }
  560. return estimate_hashes;
  561. }
  562. memcpy((char *)&nonce, nonce_bin, sizeof(nonce_bin));
  563. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  564. nonce = swab32(nonce);
  565. #endif
  566. curr_hw_errors = avalon->hw_errors;
  567. submit_nonce(thr, work[0], nonce);
  568. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  569. // Force a USB close/reopen on any hw error
  570. if (was_hw_error)
  571. do_avalon_close(thr);
  572. hash_count = (nonce & info->nonce_mask);
  573. hash_count++;
  574. hash_count *= info->asic_count;
  575. if (opt_debug || info->do_avalon_timing)
  576. timersub(&tv_finish, &tv_start, &elapsed);
  577. if (opt_debug) {
  578. applog(LOG_DEBUG,
  579. "Avalon %d nonce = 0x%08x = 0x%08llx hashes "
  580. "(%ld.%06lds)",
  581. avalon->device_id, nonce, hash_count,
  582. elapsed.tv_sec, elapsed.tv_usec);
  583. }
  584. // ignore possible end condition values ... and hw errors
  585. if (info->do_avalon_timing
  586. && !was_hw_error
  587. && ((nonce & info->nonce_mask) > END_CONDITION)
  588. && ((nonce & info->nonce_mask) <
  589. (info->nonce_mask & ~END_CONDITION))) {
  590. gettimeofday(&tv_history_start, NULL);
  591. history0 = &(info->history[0]);
  592. if (history0->values == 0)
  593. timeradd(&tv_start, &history_sec, &(history0->finish));
  594. Ti = (double)(elapsed.tv_sec)
  595. + ((double)(elapsed.tv_usec))/((double)1000000)
  596. - ((double)AVALON_READ_TIME(info->baud));
  597. Xi = (double)hash_count;
  598. history0->sumXiTi += Xi * Ti;
  599. history0->sumXi += Xi;
  600. history0->sumTi += Ti;
  601. history0->sumXi2 += Xi * Xi;
  602. history0->values++;
  603. if (history0->hash_count_max < hash_count)
  604. history0->hash_count_max = hash_count;
  605. if (history0->hash_count_min > hash_count ||
  606. history0->hash_count_min == 0)
  607. history0->hash_count_min = hash_count;
  608. if (history0->values >= info->min_data_count
  609. && timercmp(&tv_start, &(history0->finish), >)) {
  610. for (i = INFO_HISTORY; i > 0; i--)
  611. memcpy(&(info->history[i]),
  612. &(info->history[i-1]),
  613. sizeof(struct AVALON_HISTORY));
  614. // Initialise history0 to zero for summary calculation
  615. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  616. // We just completed a history data set
  617. // So now recalc read_count based on the
  618. // whole history thus we will
  619. // initially get more accurate until it
  620. // completes INFO_HISTORY
  621. // total data sets
  622. count = 0;
  623. for (i = 1 ; i <= INFO_HISTORY; i++) {
  624. history = &(info->history[i]);
  625. if (history->values >= MIN_DATA_COUNT) {
  626. count++;
  627. history0->sumXiTi += history->sumXiTi;
  628. history0->sumXi += history->sumXi;
  629. history0->sumTi += history->sumTi;
  630. history0->sumXi2 += history->sumXi2;
  631. history0->values += history->values;
  632. if (history0->hash_count_max < history->hash_count_max)
  633. history0->hash_count_max = history->hash_count_max;
  634. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  635. history0->hash_count_min = history->hash_count_min;
  636. }
  637. }
  638. // All history data
  639. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  640. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  641. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  642. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  643. values = history0->values;
  644. // Initialise history0 to zero for next data set
  645. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  646. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  647. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  648. info->Hs = Hs;
  649. info->read_count = read_count;
  650. info->fullnonce = fullnonce;
  651. info->count = count;
  652. info->W = W;
  653. info->values = values;
  654. info->hash_count_range = hash_count_range;
  655. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  656. info->min_data_count *= 2;
  657. else if (info->timing_mode == MODE_SHORT)
  658. info->do_avalon_timing = false;
  659. // applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);
  660. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  661. avalon->device_id, Hs, W, read_count, fullnonce);
  662. }
  663. info->history_count++;
  664. gettimeofday(&tv_history_finish, NULL);
  665. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  666. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  667. }
  668. return hash_count;
  669. }
  670. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  671. {
  672. struct api_data *root = NULL;
  673. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  674. // Warning, access to these is not locked - but we don't really
  675. // care since hashing performance is way more important than
  676. // locking access to displaying API debug 'stats'
  677. // If locking becomes an issue for any of them, use copy_data=true also
  678. root = api_add_int(root, "read_count", &(info->read_count), false);
  679. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  680. root = api_add_int(root, "count", &(info->count), false);
  681. root = api_add_hs(root, "Hs", &(info->Hs), false);
  682. root = api_add_double(root, "W", &(info->W), false);
  683. root = api_add_uint(root, "total_values", &(info->values), false);
  684. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  685. root = api_add_uint64(root, "history_count", &(info->history_count),
  686. false);
  687. root = api_add_timeval(root, "history_time", &(info->history_time),
  688. false);
  689. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  690. false);
  691. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  692. false);
  693. root = api_add_const(root, "timing_mode",
  694. timing_mode_str(info->timing_mode), false);
  695. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  696. false);
  697. root = api_add_int(root, "baud", &(info->baud), false);
  698. root = api_add_int(root, "work_division", &(info->work_division),
  699. false);
  700. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  701. return root;
  702. }
  703. static void avalon_shutdown(struct thr_info *thr)
  704. {
  705. do_avalon_close(thr);
  706. }
  707. struct device_api avalon_api = {
  708. .dname = "avalon",
  709. .name = "AVA",
  710. .api_detect = avalon_detect,
  711. .get_api_stats = avalon_api_stats,
  712. .thread_prepare = avalon_prepare,
  713. .scanhash_queue = avalon_scanhash,
  714. .thread_shutdown = avalon_shutdown,
  715. };