driver-bitmain.c 72 KB

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  1. /*
  2. * Copyright 2012-2014 Lingchao Xu
  3. * Copyright 2015 Luke Dashjr
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <math.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <sys/select.h>
  21. #include <termios.h>
  22. #include <sys/stat.h>
  23. #include <fcntl.h>
  24. #ifndef O_CLOEXEC
  25. #define O_CLOEXEC 0
  26. #endif
  27. #else
  28. #include "compat.h"
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include <uthash.h>
  33. #include "deviceapi.h"
  34. #include "miner.h"
  35. #include "driver-bitmain.h"
  36. #include "lowl-vcom.h"
  37. #include "util.h"
  38. const bool opt_bitmain_hwerror = true;
  39. BFG_REGISTER_DRIVER(bitmain_drv)
  40. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[];
  41. static inline unsigned int bfg_work_block(struct work * const work)
  42. {
  43. return *((unsigned int*)(&work->data[4]));
  44. }
  45. #define htole8(x) (x)
  46. struct cgpu_info *btm_alloc_cgpu(struct device_drv *drv, int threads)
  47. {
  48. struct cgpu_info *cgpu = calloc(1, sizeof(*cgpu));
  49. if (unlikely(!cgpu))
  50. quit(1, "Failed to calloc cgpu for %s in usb_alloc_cgpu", drv->dname);
  51. cgpu->drv = drv;
  52. cgpu->deven = DEV_ENABLED;
  53. cgpu->threads = threads;
  54. cgpu->device_fd = -1;
  55. struct bitmain_info *info = malloc(sizeof(*info));
  56. if (unlikely(!info))
  57. quit(1, "Failed to calloc bitmain_info data");
  58. cgpu->device_data = info;
  59. *info = (struct bitmain_info){
  60. .baud = BITMAIN_IO_SPEED,
  61. .chain_num = BITMAIN_DEFAULT_CHAIN_NUM,
  62. .asic_num = BITMAIN_DEFAULT_ASIC_NUM,
  63. .timeout = BITMAIN_DEFAULT_TIMEOUT,
  64. .frequency = BITMAIN_DEFAULT_FREQUENCY,
  65. .voltage[0] = BITMAIN_DEFAULT_VOLTAGE0,
  66. .voltage[1] = BITMAIN_DEFAULT_VOLTAGE1,
  67. };
  68. sprintf(info->frequency_t, "%d", BITMAIN_DEFAULT_FREQUENCY),
  69. strcpy(info->voltage_t, BITMAIN_DEFAULT_VOLTAGE_T);
  70. return cgpu;
  71. }
  72. struct cgpu_info *btm_free_cgpu(struct cgpu_info *cgpu)
  73. {
  74. if(cgpu->device_path) {
  75. free((char*)cgpu->device_path);
  76. }
  77. free(cgpu);
  78. return NULL;
  79. }
  80. bool btm_init(struct cgpu_info *cgpu, const char * devpath)
  81. {
  82. applog(LOG_DEBUG, "btm_init cgpu->device_fd=%d", cgpu->device_fd);
  83. int fd = -1;
  84. if(cgpu->device_fd >= 0) {
  85. return false;
  86. }
  87. fd = serial_open(devpath, 115200, 1, true);
  88. if(fd == -1) {
  89. applog(LOG_DEBUG, "%s open %s error %d",
  90. cgpu->drv->dname, devpath, errno);
  91. return false;
  92. }
  93. cgpu->device_path = strdup(devpath);
  94. cgpu->device_fd = fd;
  95. applog(LOG_DEBUG, "btm_init open device fd = %d", cgpu->device_fd);
  96. return true;
  97. }
  98. void btm_uninit(struct cgpu_info *cgpu)
  99. {
  100. applog(LOG_DEBUG, "BTM uninit %s%i", cgpu->drv->name, cgpu->device_fd);
  101. // May have happened already during a failed initialisation
  102. // if release_cgpu() was called due to a USB NODEV(err)
  103. if (cgpu->device_fd >= 0) {
  104. serial_close(cgpu->device_fd);
  105. cgpu->device_fd = -1;
  106. }
  107. if(cgpu->device_path) {
  108. free((char*)cgpu->device_path);
  109. cgpu->device_path = NULL;
  110. }
  111. }
  112. int btm_read(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  113. {
  114. int err = 0;
  115. //applog(LOG_DEBUG, "btm_read ----- %d -----", bufsize);
  116. err = read(cgpu->device_fd, buf, bufsize);
  117. return err;
  118. }
  119. int btm_write(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  120. {
  121. int err = 0;
  122. //applog(LOG_DEBUG, "btm_write ----- %d -----", bufsize);
  123. err = write(cgpu->device_fd, buf, bufsize);
  124. return err;
  125. }
  126. #define BITMAIN_CALC_DIFF1 1
  127. #ifdef WIN32
  128. #define BITMAIN_TEST
  129. #endif
  130. #define BITMAIN_TEST_PRINT_WORK 0
  131. #ifdef BITMAIN_TEST
  132. #define BITMAIN_TEST_NUM 19
  133. #define BITMAIN_TEST_USENUM 1
  134. int g_test_index = 0;
  135. const char btm_work_test_data[BITMAIN_TEST_NUM][256] = {
  136. "00000002ddc1ce5579dbec17f17fbb8f31ae218a814b2a0c1900f0d90000000100000000b58aa6ca86546b07a5a46698f736c7ca9c0eedc756d8f28ac33c20cc24d792675276f879190afc85b6888022000000800000000000000000000000000000000000000000000000000000000000000000",
  137. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000eb2d45233c5b02de50ddcb9049ba16040e0ba00e9750a474eec75891571d925b52dfda4a190266667145b02f000000800000000000000000000000000000000000000000000000000000000000000000",
  138. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000090c7d3743e0b0562e4f56d3dd35cece3c5e8275d0abb21bf7e503cb72bd7ed3b52dfda4a190266667bbb58d7000000800000000000000000000000000000000000000000000000000000000000000000",
  139. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000006e0561da06022bfbb42c5ecd74a46bfd91934f201b777e9155cc6c3674724ec652dfda4a19026666a0cd827b000000800000000000000000000000000000000000000000000000000000000000000000",
  140. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000000312f42ce4964cc23f2d8c039f106f25ddd58e10a1faed21b3bba4b0e621807b52dfda4a1902666629c9497d000000800000000000000000000000000000000000000000000000000000000000000000",
  141. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000033093a6540dbe8f7f3d19e3d2af05585ac58dafad890fa9a942e977334a23d6e52dfda4a190266665ae95079000000800000000000000000000000000000000000000000000000000000000000000000",
  142. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000bd7893057d06e69705bddf9a89c7bac6b40c5b32f15e2295fc8c5edf491ea24952dfda4a190266664b89b4d3000000800000000000000000000000000000000000000000000000000000000000000000",
  143. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000075e66f533e53837d14236a793ee4e493985642bc39e016b9e63adf14a584a2aa52dfda4a19026666ab5d638d000000800000000000000000000000000000000000000000000000000000000000000000",
  144. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d936f90c5db5f0fe1d017344443854fbf9e40a07a9b7e74fedc8661c23162bff52dfda4a19026666338e79cb000000800000000000000000000000000000000000000000000000000000000000000000",
  145. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d2c1a7d279a4355b017bc0a4b0a9425707786729f21ee18add3fda4252a31a4152dfda4a190266669bc90806000000800000000000000000000000000000000000000000000000000000000000000000",
  146. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000ad36d19f33d04ca779942843890bc3b083cec83a4b60b6c45cf7d21fc187746552dfda4a1902666675d81ab7000000800000000000000000000000000000000000000000000000000000000000000000",
  147. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000093b809cf82b76082eacb55bc35b79f31882ed0976fd102ef54783cd24341319b52dfda4a1902666642ab4e42000000800000000000000000000000000000000000000000000000000000000000000000",
  148. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000007411ff315430a7bbf41de8a685d457e82d5177c05640d6a4436a40f39e99667852dfda4a190266662affa4b5000000800000000000000000000000000000000000000000000000000000000000000000",
  149. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000001ad0db5b9e1e2b57c8d3654c160f5a51067521eab7e340a270639d97f00a3fa252dfda4a1902666601a47bb6000000800000000000000000000000000000000000000000000000000000000000000000",
  150. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000022e055c442c46bbe16df68603a26891f6e4cf85b90102b39fd7cadb602b4e34552dfda4a1902666695d33cea000000800000000000000000000000000000000000000000000000000000000000000000",
  151. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000009c8baf5a8a1e16de2d6ae949d5fec3ed751f10dcd4c99810f2ce08040fb9e31d52dfda4a19026666fe78849d000000800000000000000000000000000000000000000000000000000000000000000000",
  152. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000e5655532b414887f35eb4652bc7b11ebac12891f65bc08cbe0ce5b277b9e795152dfda4a19026666fcc0d1d1000000800000000000000000000000000000000000000000000000000000000000000000",
  153. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000f272c5508704e2b62dd1c30ea970372c40bf00f9203f9bf69d456b4a7fbfffe352dfda4a19026666c03d4399000000800000000000000000000000000000000000000000000000000000000000000000",
  154. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000fca3b4531ba627ad9b0e23cdd84c888952c23810df196e9c6db0bcecba6a830952dfda4a19026666c14009cb000000800000000000000000000000000000000000000000000000000000000000000000"
  155. };
  156. const char btm_work_test_midstate[BITMAIN_TEST_NUM][256] = {
  157. "2d8738e7f5bcf76dcb8316fec772e20e240cd58c88d47f2d3f5a6a9547ed0a35",
  158. "d31b6ce09c0bfc2af6f3fe3a03475ebefa5aa191fa70a327a354b2c22f9692f1",
  159. "84a8c8224b80d36caeb42eff2a100f634e1ff873e83fd02ef1306a34abef9dbe",
  160. "059882159439b9b32968c79a93c5521e769dbea9d840f56c2a17b9ad87e530b8",
  161. "17fa435d05012574f8f1da26994cc87b6cb9660b5e82072dc6a0881cec150a0d",
  162. "92a28cc5ec4ba6a2688471dfe2032b5fe97c805ca286c503e447d6749796c6af",
  163. "1677a03516d6e9509ac37e273d2482da9af6e077abe8392cdca6a30e916a7ae9",
  164. "50bbe09f1b8ac18c97aeb745d5d2c3b5d669b6ac7803e646f65ac7b763a392d1",
  165. "e46a0022ebdc303a7fb1a0ebfa82b523946c312e745e5b8a116b17ae6b4ce981",
  166. "8f2f61e7f5b4d76d854e6d266acfff4d40347548216838ccc4ef3b9e43d3c9ea",
  167. "0a450588ae99f75d676a08d0326e1ea874a3497f696722c78a80c7b6ee961ea6",
  168. "3c4c0fc2cf040b806c51b46de9ec0dcc678a7cc5cf3eff11c6c03de3bc7818cc",
  169. "f6c7c785ab5daddb8f98e5f854f2cb41879fcaf47289eb2b4196fefc1b28316f",
  170. "005312351ccb0d0794779f5023e4335b5cad221accf0dfa3da7b881266fa9f5a",
  171. "7b26d189c6bba7add54143179aadbba7ccaeff6887bd8d5bec9597d5716126e6",
  172. "a4718f4c801e7ddf913a9474eb71774993525684ffea1915f767ab16e05e6889",
  173. "6b6226a8c18919d0e55684638d33a6892a00d22492cc2f5906ca7a4ac21c74a7",
  174. "383114dccd1cb824b869158aa2984d157fcb02f46234ceca65943e919329e697",
  175. "d4d478df3016852b27cb1ae9e1e98d98617f8d0943bf9dc1217f47f817236222"
  176. };
  177. #endif
  178. bool opt_bitmain_checkall = false;
  179. bool opt_bitmain_nobeeper = false;
  180. bool opt_bitmain_notempoverctrl = false;
  181. bool opt_bitmain_homemode = false;
  182. int opt_bitmain_temp = BITMAIN_TEMP_TARGET;
  183. int opt_bitmain_overheat = BITMAIN_TEMP_OVERHEAT;
  184. int opt_bitmain_fan_min = BITMAIN_DEFAULT_FAN_MIN_PWM;
  185. int opt_bitmain_fan_max = BITMAIN_DEFAULT_FAN_MAX_PWM;
  186. int opt_bitmain_freq_min = BITMAIN_MIN_FREQUENCY;
  187. int opt_bitmain_freq_max = BITMAIN_MAX_FREQUENCY;
  188. bool opt_bitmain_auto;
  189. // --------------------------------------------------------------
  190. // CRC16 check table
  191. // --------------------------------------------------------------
  192. const uint8_t chCRCHTalbe[] = // CRC high byte table
  193. {
  194. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  195. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  196. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  197. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  198. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  199. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  200. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  201. 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  202. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  203. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  204. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  205. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  206. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  207. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  208. 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  209. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  210. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  211. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  212. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  213. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  214. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  215. 0x00, 0xC1, 0x81, 0x40
  216. };
  217. const uint8_t chCRCLTalbe[] = // CRC low byte table
  218. {
  219. 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
  220. 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
  221. 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
  222. 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
  223. 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
  224. 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
  225. 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
  226. 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
  227. 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
  228. 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
  229. 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
  230. 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
  231. 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
  232. 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
  233. 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
  234. 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
  235. 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
  236. 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
  237. 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
  238. 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
  239. 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
  240. 0x41, 0x81, 0x80, 0x40
  241. };
  242. static uint16_t CRC16(const uint8_t* p_data, uint16_t w_len)
  243. {
  244. uint8_t chCRCHi = 0xFF; // CRC high byte initialize
  245. uint8_t chCRCLo = 0xFF; // CRC low byte initialize
  246. uint16_t wIndex = 0; // CRC cycling index
  247. while (w_len--) {
  248. wIndex = chCRCLo ^ *p_data++;
  249. chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
  250. chCRCHi = chCRCLTalbe[wIndex];
  251. }
  252. return ((chCRCHi << 8) | chCRCLo);
  253. }
  254. static uint32_t num2bit(int num) {
  255. switch(num) {
  256. case 0: return 0x80000000;
  257. case 1: return 0x40000000;
  258. case 2: return 0x20000000;
  259. case 3: return 0x10000000;
  260. case 4: return 0x08000000;
  261. case 5: return 0x04000000;
  262. case 6: return 0x02000000;
  263. case 7: return 0x01000000;
  264. case 8: return 0x00800000;
  265. case 9: return 0x00400000;
  266. case 10: return 0x00200000;
  267. case 11: return 0x00100000;
  268. case 12: return 0x00080000;
  269. case 13: return 0x00040000;
  270. case 14: return 0x00020000;
  271. case 15: return 0x00010000;
  272. case 16: return 0x00008000;
  273. case 17: return 0x00004000;
  274. case 18: return 0x00002000;
  275. case 19: return 0x00001000;
  276. case 20: return 0x00000800;
  277. case 21: return 0x00000400;
  278. case 22: return 0x00000200;
  279. case 23: return 0x00000100;
  280. case 24: return 0x00000080;
  281. case 25: return 0x00000040;
  282. case 26: return 0x00000020;
  283. case 27: return 0x00000010;
  284. case 28: return 0x00000008;
  285. case 29: return 0x00000004;
  286. case 30: return 0x00000002;
  287. case 31: return 0x00000001;
  288. default: return 0x00000000;
  289. }
  290. }
  291. static int bitmain_set_txconfig(struct bitmain_txconfig_token *bm,
  292. uint8_t reset, uint8_t fan_eft, uint8_t timeout_eft, uint8_t frequency_eft,
  293. uint8_t voltage_eft, uint8_t chain_check_time_eft, uint8_t chip_config_eft, uint8_t hw_error_eft,
  294. uint8_t beeper_ctrl, uint8_t temp_over_ctrl,uint8_t fan_home_mode,
  295. uint8_t chain_num, uint8_t asic_num, uint8_t fan_pwm_data, uint8_t timeout_data,
  296. uint16_t frequency, uint8_t * voltage, uint8_t chain_check_time,
  297. uint8_t chip_address, uint8_t reg_address, uint8_t * reg_data)
  298. {
  299. uint16_t crc = 0;
  300. int datalen = 0;
  301. uint8_t version = 0;
  302. uint8_t * sendbuf = (uint8_t *)bm;
  303. if (unlikely(!bm)) {
  304. applog(LOG_WARNING, "bitmain_set_txconfig bitmain_txconfig_token is null");
  305. return -1;
  306. }
  307. if (unlikely(timeout_data <= 0 || asic_num <= 0 || chain_num <= 0)) {
  308. applog(LOG_WARNING, "bitmain_set_txconfig parameter invalid timeout_data(%d) asic_num(%d) chain_num(%d)",
  309. timeout_data, asic_num, chain_num);
  310. return -1;
  311. }
  312. datalen = sizeof(struct bitmain_txconfig_token);
  313. memset(bm, 0, datalen);
  314. bm->token_type = BITMAIN_TOKEN_TYPE_TXCONFIG;
  315. bm->version = version;
  316. bm->length = datalen-4;
  317. bm->length = htole16(bm->length);
  318. bm->reset = reset;
  319. bm->fan_eft = fan_eft;
  320. bm->timeout_eft = timeout_eft;
  321. bm->frequency_eft = frequency_eft;
  322. bm->voltage_eft = voltage_eft;
  323. bm->chain_check_time_eft = chain_check_time_eft;
  324. bm->chip_config_eft = chip_config_eft;
  325. bm->hw_error_eft = hw_error_eft;
  326. bm->beeper_ctrl = beeper_ctrl;
  327. bm->temp_over_ctrl = temp_over_ctrl;
  328. bm->fan_home_mode = fan_home_mode;
  329. sendbuf[4] = htole8(sendbuf[4]);
  330. sendbuf[5] = htole8(sendbuf[5]);
  331. bm->chain_num = chain_num;
  332. bm->asic_num = asic_num;
  333. bm->fan_pwm_data = fan_pwm_data;
  334. bm->timeout_data = timeout_data;
  335. bm->frequency = htole16(frequency);
  336. memcpy(bm->voltage, voltage, 2);
  337. bm->chain_check_time = chain_check_time;
  338. memcpy(bm->reg_data, reg_data, 4);
  339. bm->chip_address = chip_address;
  340. bm->reg_address = reg_address;
  341. crc = CRC16((uint8_t *)bm, datalen-2);
  342. bm->crc = htole16(crc);
  343. applog(LOG_ERR, "BTM TxConfigToken:v(%d) reset(%d) fan_e(%d) tout_e(%d) fq_e(%d) vt_e(%d) chainc_e(%d) chipc_e(%d) hw_e(%d) b_c(%d) t_c(%d) f_m(%d) mnum(%d) anum(%d) fanpwmdata(%d) toutdata(%d) freq(%d) volt(%02x%02x) chainctime(%d) regdata(%02x%02x%02x%02x) chipaddr(%02x) regaddr(%02x) crc(%04x)",
  344. version, reset, fan_eft, timeout_eft, frequency_eft, voltage_eft,
  345. chain_check_time_eft, chip_config_eft, hw_error_eft, beeper_ctrl, temp_over_ctrl,fan_home_mode,chain_num, asic_num,
  346. fan_pwm_data, timeout_data, frequency, voltage[0], voltage[1],
  347. chain_check_time, reg_data[0], reg_data[1], reg_data[2], reg_data[3], chip_address, reg_address, crc);
  348. return datalen;
  349. }
  350. static int bitmain_set_txtask(uint8_t * sendbuf,
  351. unsigned int * last_work_block, struct work **works, int work_array_size, int work_array, int sendworkcount, int * sendcount)
  352. {
  353. uint16_t crc = 0;
  354. uint32_t work_id = 0;
  355. uint8_t version = 0;
  356. int datalen = 0;
  357. int i = 0;
  358. int index = work_array;
  359. uint8_t new_block= 0;
  360. struct bitmain_txtask_token *bm = (struct bitmain_txtask_token *)sendbuf;
  361. *sendcount = 0;
  362. int cursendcount = 0;
  363. int diff = 0;
  364. unsigned int difftmp = 0;
  365. unsigned int pooldiff = 0;
  366. int netdiff = 0;
  367. if (unlikely(!bm)) {
  368. applog(LOG_WARNING, "bitmain_set_txtask bitmain_txtask_token is null");
  369. return -1;
  370. }
  371. if (unlikely(!works)) {
  372. applog(LOG_WARNING, "bitmain_set_txtask work is null");
  373. return -1;
  374. }
  375. memset(bm, 0, sizeof(struct bitmain_txtask_token));
  376. bm->token_type = BITMAIN_TOKEN_TYPE_TXTASK;
  377. bm->version = version;
  378. datalen = 10;
  379. applog(LOG_DEBUG, "BTM send work count %d -----", sendworkcount);
  380. pooldiff = 0x100;
  381. unsigned lowest_goal_diff = UINT_MAX;
  382. for (i = 0; i < sendworkcount; ++i) {
  383. if (index > work_array_size) {
  384. index = 0;
  385. }
  386. if (!works[index]) {
  387. continue;
  388. }
  389. struct work * const work = works[index];
  390. if (work->work_difficulty < pooldiff)
  391. pooldiff = work->work_difficulty;
  392. const struct pool * const pool = work->pool;
  393. const struct mining_goal_info * const goal = pool->goal;
  394. if (goal->current_diff < lowest_goal_diff)
  395. lowest_goal_diff = goal->current_diff;
  396. }
  397. {
  398. difftmp = pooldiff;
  399. while(1) {
  400. difftmp = difftmp >> 1;
  401. if(difftmp > 0) {
  402. diff++;
  403. if(diff >= 255) {
  404. break;
  405. }
  406. } else {
  407. break;
  408. }
  409. }
  410. for (uint64_t netdifftmp = lowest_goal_diff; netdifftmp > 0; netdifftmp >>= 1) {
  411. ++netdiff;
  412. }
  413. pooldiff = pow(2, diff);
  414. }
  415. applog(LOG_DEBUG, "bitmain_set_txtask using nonce_diff=%u (log2=%d) and goal_diff=%u (log2=%d)", pooldiff, diff, lowest_goal_diff, netdiff);
  416. for(i = 0; i < sendworkcount; i++) {
  417. if(index > work_array_size) {
  418. index = 0;
  419. }
  420. if(works[index]) {
  421. const unsigned int work_block = bfg_work_block(works[index]);
  422. if(work_block != *last_work_block) {
  423. applog(LOG_ERR, "BTM send task new block %d old(%d)", work_block, *last_work_block);
  424. new_block = 1;
  425. *last_work_block = work_block;
  426. }
  427. #ifdef BITMAIN_TEST
  428. if(!hex2bin(works[index]->data, btm_work_test_data[g_test_index], 128)) {
  429. applog(LOG_DEBUG, "BTM send task set test data error");
  430. }
  431. if(!hex2bin(works[index]->midstate, btm_work_test_midstate[g_test_index], 32)) {
  432. applog(LOG_DEBUG, "BTM send task set test midstate error");
  433. }
  434. g_test_index++;
  435. if(g_test_index >= BITMAIN_TEST_USENUM) {
  436. g_test_index = 0;
  437. }
  438. applog(LOG_DEBUG, "BTM test index = %d", g_test_index);
  439. #endif
  440. work_id = works[index]->id;
  441. bm->works[cursendcount].work_id = htole32(work_id);
  442. applog(LOG_DEBUG, "BTM send task work id:%d %d", bm->works[cursendcount].work_id, work_id);
  443. memcpy(bm->works[cursendcount].midstate, works[index]->midstate, 32);
  444. memcpy(bm->works[cursendcount].data2, works[index]->data + 64, 12);
  445. works[index]->nonce_diff = pooldiff;
  446. if(BITMAIN_TEST_PRINT_WORK) {
  447. char ob_hex[(76 * 2) + 1];
  448. bin2hex(ob_hex, works[index]->data, 76);
  449. applog(LOG_ERR, "work %d data: %s", works[index]->id, ob_hex);
  450. }
  451. cursendcount++;
  452. }
  453. index++;
  454. }
  455. if(cursendcount <= 0) {
  456. applog(LOG_ERR, "BTM send work count %d", cursendcount);
  457. return 0;
  458. }
  459. datalen += 48*cursendcount;
  460. bm->length = datalen-4;
  461. bm->length = htole16(bm->length);
  462. //len = datalen-3;
  463. //len = htole16(len);
  464. //memcpy(sendbuf+1, &len, 2);
  465. bm->new_block = new_block;
  466. bm->diff = diff;
  467. bm->net_diff = htole16(netdiff);
  468. sendbuf[4] = htole8(sendbuf[4]);
  469. applog(LOG_DEBUG, "BitMain TxTask Token: %d %d %02x%02x%02x%02x%02x%02x",
  470. datalen, bm->length, sendbuf[0],sendbuf[1],sendbuf[2],sendbuf[3],sendbuf[4],sendbuf[5]);
  471. *sendcount = cursendcount;
  472. crc = CRC16(sendbuf, datalen-2);
  473. crc = htole16(crc);
  474. memcpy(sendbuf+datalen-2, &crc, 2);
  475. applog(LOG_DEBUG, "BitMain TxTask Token: v(%d) new_block(%d) diff(%d pool:%d net:%d) work_num(%d) crc(%04x)",
  476. version, new_block, diff, pooldiff,netdiff, cursendcount, crc);
  477. applog(LOG_DEBUG, "BitMain TxTask Token: %d %d %02x%02x%02x%02x%02x%02x",
  478. datalen, bm->length, sendbuf[0],sendbuf[1],sendbuf[2],sendbuf[3],sendbuf[4],sendbuf[5]);
  479. return datalen;
  480. }
  481. static int bitmain_set_rxstatus(struct bitmain_rxstatus_token *bm,
  482. uint8_t chip_status_eft, uint8_t detect_get, uint8_t chip_address, uint8_t reg_address)
  483. {
  484. uint16_t crc = 0;
  485. uint8_t version = 0;
  486. int datalen = 0;
  487. uint8_t * sendbuf = (uint8_t *)bm;
  488. if (unlikely(!bm)) {
  489. applog(LOG_WARNING, "bitmain_set_rxstatus bitmain_rxstatus_token is null");
  490. return -1;
  491. }
  492. datalen = sizeof(struct bitmain_rxstatus_token);
  493. memset(bm, 0, datalen);
  494. bm->token_type = BITMAIN_TOKEN_TYPE_RXSTATUS;
  495. bm->version = version;
  496. bm->length = datalen-4;
  497. bm->length = htole16(bm->length);
  498. bm->chip_status_eft = chip_status_eft;
  499. bm->detect_get = detect_get;
  500. sendbuf[4] = htole8(sendbuf[4]);
  501. bm->chip_address = chip_address;
  502. bm->reg_address = reg_address;
  503. crc = CRC16((uint8_t *)bm, datalen-2);
  504. bm->crc = htole16(crc);
  505. applog(LOG_ERR, "BitMain RxStatus Token: v(%d) chip_status_eft(%d) detect_get(%d) chip_address(%02x) reg_address(%02x) crc(%04x)",
  506. version, chip_status_eft, detect_get, chip_address, reg_address, crc);
  507. return datalen;
  508. }
  509. static int bitmain_parse_rxstatus(const uint8_t * data, int datalen, struct bitmain_rxstatus_data *bm)
  510. {
  511. uint16_t crc = 0;
  512. uint8_t version = 0;
  513. int i = 0, j = 0;
  514. int asic_num = 0;
  515. int dataindex = 0;
  516. uint8_t tmp = 0x01;
  517. if (unlikely(!bm)) {
  518. applog(LOG_WARNING, "bitmain_parse_rxstatus bitmain_rxstatus_data is null");
  519. return -1;
  520. }
  521. if (unlikely(!data || datalen <= 0)) {
  522. applog(LOG_WARNING, "bitmain_parse_rxstatus parameter invalid data is null or datalen(%d) error", datalen);
  523. return -1;
  524. }
  525. memset(bm, 0, sizeof(struct bitmain_rxstatus_data));
  526. memcpy(bm, data, 28);
  527. if (bm->data_type != BITMAIN_DATA_TYPE_RXSTATUS) {
  528. applog(LOG_ERR, "bitmain_parse_rxstatus datatype(%02x) error", bm->data_type);
  529. return -1;
  530. }
  531. if (bm->version != version) {
  532. applog(LOG_ERR, "bitmain_parse_rxstatus version(%02x) error", bm->version);
  533. return -1;
  534. }
  535. bm->length = htole16(bm->length);
  536. if (bm->length+4 != datalen) {
  537. applog(LOG_ERR, "bitmain_parse_rxstatus length(%d) datalen(%d) error", bm->length, datalen);
  538. return -1;
  539. }
  540. crc = CRC16(data, datalen-2);
  541. memcpy(&(bm->crc), data+datalen-2, 2);
  542. bm->crc = htole16(bm->crc);
  543. if(crc != bm->crc) {
  544. applog(LOG_ERR, "bitmain_parse_rxstatus check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  545. return -1;
  546. }
  547. bm->fifo_space = htole16(bm->fifo_space);
  548. bm->fan_exist = htole16(bm->fan_exist);
  549. bm->temp_exist = htole32(bm->temp_exist);
  550. bm->nonce_error = htole32(bm->nonce_error);
  551. if(bm->chain_num > BITMAIN_MAX_CHAIN_NUM) {
  552. applog(LOG_ERR, "bitmain_parse_rxstatus chain_num=%d error", bm->chain_num);
  553. return -1;
  554. }
  555. dataindex = 28;
  556. if(bm->chain_num > 0) {
  557. memcpy(bm->chain_asic_num, data+datalen-2-bm->chain_num-bm->temp_num-bm->fan_num, bm->chain_num);
  558. }
  559. for(i = 0; i < bm->chain_num; i++) {
  560. asic_num = bm->chain_asic_num[i];
  561. if(asic_num <= 0) {
  562. asic_num = 1;
  563. } else {
  564. if(asic_num % 32 == 0) {
  565. asic_num = asic_num / 32;
  566. } else {
  567. asic_num = asic_num / 32 + 1;
  568. }
  569. }
  570. memcpy((uint8_t *)bm->chain_asic_exist+i*32, data+dataindex, asic_num*4);
  571. dataindex += asic_num*4;
  572. }
  573. for(i = 0; i < bm->chain_num; i++) {
  574. asic_num = bm->chain_asic_num[i];
  575. if(asic_num <= 0) {
  576. asic_num = 1;
  577. } else {
  578. if(asic_num % 32 == 0) {
  579. asic_num = asic_num / 32;
  580. } else {
  581. asic_num = asic_num / 32 + 1;
  582. }
  583. }
  584. memcpy((uint8_t *)bm->chain_asic_status+i*32, data+dataindex, asic_num*4);
  585. dataindex += asic_num*4;
  586. }
  587. dataindex += bm->chain_num;
  588. if(dataindex + bm->temp_num + bm->fan_num + 2 != datalen) {
  589. applog(LOG_ERR, "bitmain_parse_rxstatus dataindex(%d) chain_num(%d) temp_num(%d) fan_num(%d) not match datalen(%d)",
  590. dataindex, bm->chain_num, bm->temp_num, bm->fan_num, datalen);
  591. return -1;
  592. }
  593. for(i = 0; i < bm->chain_num; i++) {
  594. //bm->chain_asic_status[i] = swab32(bm->chain_asic_status[i]);
  595. for(j = 0; j < 8; j++) {
  596. bm->chain_asic_exist[i*8+j] = htole32(bm->chain_asic_exist[i*8+j]);
  597. bm->chain_asic_status[i*8+j] = htole32(bm->chain_asic_status[i*8+j]);
  598. }
  599. }
  600. if(bm->temp_num > 0) {
  601. memcpy(bm->temp, data+dataindex, bm->temp_num);
  602. dataindex += bm->temp_num;
  603. }
  604. if(bm->fan_num > 0) {
  605. memcpy(bm->fan, data+dataindex, bm->fan_num);
  606. dataindex += bm->fan_num;
  607. }
  608. if(!opt_bitmain_checkall){
  609. if(tmp != htole8(tmp)){
  610. applog(LOG_ERR, "BitMain RxStatus byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  611. memcpy(&tmp,data+4,1);
  612. bm->chip_value_eft = tmp >>7;
  613. bm->get_blk_num = tmp >> 4;
  614. bm->reserved1 = ((tmp << 4) & 0xff) >> 5;
  615. }
  616. found_blocks = bm->get_blk_num;
  617. applog(LOG_ERR, "BitMain RxStatus tmp :0x%02x byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",tmp,*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  618. }
  619. applog(LOG_DEBUG, "BitMain RxStatusData: chipv_e(%d) chainnum(%d) fifos(%d) v1(%d) v2(%d) v3(%d) v4(%d) fann(%d) tempn(%d) fanet(%04x) tempet(%08x) ne(%d) regvalue(%d) crc(%04x)",
  620. bm->chip_value_eft, bm->chain_num, bm->fifo_space, bm->hw_version[0], bm->hw_version[1], bm->hw_version[2], bm->hw_version[3], bm->fan_num, bm->temp_num, bm->fan_exist, bm->temp_exist, bm->nonce_error, bm->reg_value, bm->crc);
  621. applog(LOG_DEBUG, "BitMain RxStatus Data chain info:");
  622. for(i = 0; i < bm->chain_num; i++) {
  623. applog(LOG_DEBUG, "BitMain RxStatus Data chain(%d) asic num=%d asic_exist=%08x asic_status=%08x", i+1, bm->chain_asic_num[i], bm->chain_asic_exist[i*8], bm->chain_asic_status[i*8]);
  624. }
  625. applog(LOG_DEBUG, "BitMain RxStatus Data temp info:");
  626. for(i = 0; i < bm->temp_num; i++) {
  627. applog(LOG_DEBUG, "BitMain RxStatus Data temp(%d) temp=%d", i+1, bm->temp[i]);
  628. }
  629. applog(LOG_DEBUG, "BitMain RxStatus Data fan info:");
  630. for(i = 0; i < bm->fan_num; i++) {
  631. applog(LOG_DEBUG, "BitMain RxStatus Data fan(%d) fan=%d", i+1, bm->fan[i]);
  632. }
  633. return 0;
  634. }
  635. static int bitmain_parse_rxnonce(const uint8_t * data, int datalen, struct bitmain_rxnonce_data *bm, int * nonce_num)
  636. {
  637. int i = 0;
  638. uint16_t crc = 0;
  639. uint8_t version = 0;
  640. int curnoncenum = 0;
  641. if (unlikely(!bm)) {
  642. applog(LOG_ERR, "bitmain_parse_rxnonce bitmain_rxstatus_data null");
  643. return -1;
  644. }
  645. if (unlikely(!data || datalen <= 0)) {
  646. applog(LOG_ERR, "bitmain_parse_rxnonce data null or datalen(%d) error", datalen);
  647. return -1;
  648. }
  649. memcpy(bm, data, sizeof(struct bitmain_rxnonce_data));
  650. if (bm->data_type != BITMAIN_DATA_TYPE_RXNONCE) {
  651. applog(LOG_ERR, "bitmain_parse_rxnonce datatype(%02x) error", bm->data_type);
  652. return -1;
  653. }
  654. if (bm->version != version) {
  655. applog(LOG_ERR, "bitmain_parse_rxnonce version(%02x) error", bm->version);
  656. return -1;
  657. }
  658. bm->length = htole16(bm->length);
  659. if (bm->length+4 != datalen) {
  660. applog(LOG_ERR, "bitmain_parse_rxnonce length(%d) error", bm->length);
  661. return -1;
  662. }
  663. crc = CRC16(data, datalen-2);
  664. memcpy(&(bm->crc), data+datalen-2, 2);
  665. bm->crc = htole16(bm->crc);
  666. if(crc != bm->crc) {
  667. applog(LOG_ERR, "bitmain_parse_rxnonce check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  668. return -1;
  669. }
  670. bm->fifo_space = htole16(bm->fifo_space);
  671. bm->diff = htole16(bm->diff);
  672. bm->total_nonce_num = htole64(bm->total_nonce_num);
  673. curnoncenum = (datalen-14)/8;
  674. applog(LOG_DEBUG, "BitMain RxNonce Data: nonce_num(%d) fifo_space(%d) diff(%d) tnn(%"PRIu64")", curnoncenum, bm->fifo_space, bm->diff, bm->total_nonce_num);
  675. for(i = 0; i < curnoncenum; i++) {
  676. bm->nonces[i].work_id = htole32(bm->nonces[i].work_id);
  677. bm->nonces[i].nonce = htole32(bm->nonces[i].nonce);
  678. applog(LOG_DEBUG, "BitMain RxNonce Data %d: work_id(%d) nonce(%08x)(%d)",
  679. i, bm->nonces[i].work_id, bm->nonces[i].nonce, bm->nonces[i].nonce);
  680. }
  681. *nonce_num = curnoncenum;
  682. return 0;
  683. }
  684. static int bitmain_read(struct cgpu_info *bitmain, unsigned char *buf,
  685. size_t bufsize, int timeout)
  686. {
  687. int err = 0;
  688. size_t total = 0;
  689. if(bitmain == NULL || buf == NULL || bufsize <= 0) {
  690. applog(LOG_WARNING, "bitmain_read parameter error bufsize(%llu)", (unsigned long long)bufsize);
  691. return -1;
  692. }
  693. {
  694. err = btm_read(bitmain, buf, bufsize);
  695. total = err;
  696. }
  697. return total;
  698. }
  699. static int bitmain_write(struct cgpu_info *bitmain, char *buf, ssize_t len)
  700. {
  701. int err;
  702. {
  703. int havelen = 0;
  704. while(havelen < len) {
  705. err = btm_write(bitmain, buf+havelen, len-havelen);
  706. if(err < 0) {
  707. applog(LOG_DEBUG, "%s%i: btm_write got err %d", bitmain->drv->name,
  708. bitmain->device_id, err);
  709. applog(LOG_WARNING, "usb_write error on bitmain_write");
  710. return BTM_SEND_ERROR;
  711. } else {
  712. havelen += err;
  713. }
  714. }
  715. }
  716. return BTM_SEND_OK;
  717. }
  718. static int bitmain_send_data(const uint8_t * data, int datalen, struct cgpu_info *bitmain)
  719. {
  720. int ret;
  721. if(datalen <= 0) {
  722. return 0;
  723. }
  724. //struct bitmain_info *info = bitmain->device_data;
  725. //int delay;
  726. //delay = datalen * 10 * 1000000;
  727. //delay = delay / info->baud;
  728. //delay += 4000;
  729. if(opt_debug) {
  730. char hex[(datalen * 2) + 1];
  731. bin2hex(hex, data, datalen);
  732. applog(LOG_DEBUG, "BitMain: Sent(%d): %s", datalen, hex);
  733. }
  734. //cgtimer_t ts_start;
  735. //cgsleep_prepare_r(&ts_start);
  736. //applog(LOG_DEBUG, "----bitmain_send_data start");
  737. ret = bitmain_write(bitmain, (char *)data, datalen);
  738. applog(LOG_DEBUG, "----bitmain_send_data stop ret=%d datalen=%d", ret, datalen);
  739. //cgsleep_us_r(&ts_start, delay);
  740. //applog(LOG_DEBUG, "BitMain: Sent: Buffer delay: %dus", delay);
  741. return ret;
  742. }
  743. static bool bitmain_decode_nonce(struct thr_info *thr, struct cgpu_info *bitmain,
  744. struct bitmain_info *info, uint32_t nonce, struct work *work)
  745. {
  746. info = bitmain->device_data;
  747. //info->matching_work[work->subid]++;
  748. applog(LOG_DEBUG, "BitMain: submit nonce = %08x", nonce);
  749. return submit_nonce(thr, work, nonce);
  750. }
  751. static void bitmain_inc_nvw(struct bitmain_info *info, struct thr_info *thr)
  752. {
  753. applog(LOG_INFO, "%s%d: No matching work - HW error",
  754. thr->cgpu->drv->name, thr->cgpu->device_id);
  755. inc_hw_errors_only(thr);
  756. info->no_matching_work++;
  757. }
  758. static inline void record_temp_fan(struct bitmain_info *info, struct bitmain_rxstatus_data *bm, float *temp_avg)
  759. {
  760. int i = 0;
  761. int maxfan = 0, maxtemp = 0;
  762. *temp_avg = 0;
  763. info->fan_num = bm->fan_num;
  764. for(i = 0; i < bm->fan_num; i++) {
  765. info->fan[i] = bm->fan[i] * BITMAIN_FAN_FACTOR;
  766. if(info->fan[i] > maxfan)
  767. maxfan = info->fan[i];
  768. }
  769. info->temp_num = bm->temp_num;
  770. for(i = 0; i < bm->temp_num; i++) {
  771. info->temp[i] = bm->temp[i];
  772. /*
  773. if(bm->temp[i] & 0x80) {
  774. bm->temp[i] &= 0x7f;
  775. info->temp[i] = 0 - ((~bm->temp[i] & 0x7f) + 1);
  776. }*/
  777. *temp_avg += info->temp[i];
  778. if(info->temp[i] > info->temp_max) {
  779. info->temp_max = info->temp[i];
  780. }
  781. if(info->temp[i] > maxtemp)
  782. maxtemp = info->temp[i];
  783. }
  784. if(bm->temp_num > 0) {
  785. *temp_avg = *temp_avg / bm->temp_num;
  786. info->temp_avg = *temp_avg;
  787. }
  788. // inc_dev_status
  789. mutex_lock(&stats_lock);
  790. info->g_max_fan = maxfan;
  791. info->g_max_temp = maxtemp;
  792. mutex_unlock(&stats_lock);
  793. }
  794. static void bitmain_update_temps(struct cgpu_info *bitmain, struct bitmain_info *info,
  795. struct bitmain_rxstatus_data *bm)
  796. {
  797. char tmp[64] = {0};
  798. char msg[10240] = {0};
  799. int i = 0;
  800. record_temp_fan(info, bm, &(bitmain->temp));
  801. strcpy(msg, "BitMain: ");
  802. for(i = 0; i < bm->fan_num; i++) {
  803. if(i != 0) {
  804. strcat(msg, ", ");
  805. }
  806. sprintf(tmp, "Fan%d: %d/m", i+1, info->fan[i]);
  807. strcat(msg, tmp);
  808. }
  809. strcat(msg, "\t");
  810. for(i = 0; i < bm->temp_num; i++) {
  811. if(i != 0) {
  812. strcat(msg, ", ");
  813. }
  814. sprintf(tmp, "Temp%d: %dC", i+1, info->temp[i]);
  815. strcat(msg, tmp);
  816. }
  817. sprintf(tmp, ", TempMAX: %dC", info->temp_max);
  818. strcat(msg, tmp);
  819. applog(LOG_INFO, "%s", msg);
  820. info->temp_history_index++;
  821. info->temp_sum += bitmain->temp;
  822. applog(LOG_DEBUG, "BitMain: temp_index: %d, temp_count: %d, temp_old: %d",
  823. info->temp_history_index, info->temp_history_count, info->temp_old);
  824. if (info->temp_history_index == info->temp_history_count) {
  825. info->temp_history_index = 0;
  826. info->temp_sum = 0;
  827. }
  828. if (unlikely(info->temp_old >= opt_bitmain_overheat)) {
  829. applog(LOG_WARNING, "BTM%d overheat! Idling", bitmain->device_id);
  830. info->overheat = true;
  831. } else if (info->overheat && info->temp_old <= opt_bitmain_temp) {
  832. applog(LOG_WARNING, "BTM%d cooled, restarting", bitmain->device_id);
  833. info->overheat = false;
  834. }
  835. }
  836. extern void cg_logwork_uint32(struct work *work, uint32_t nonce, bool ok);
  837. static void bitmain_parse_results(struct cgpu_info *bitmain, struct bitmain_info *info,
  838. struct thr_info *thr, uint8_t *buf, int *offset)
  839. {
  840. int i, j, n, m, r, errordiff, spare = BITMAIN_READ_SIZE;
  841. uint32_t checkbit = 0x00000000;
  842. bool found = false;
  843. struct work *work = NULL;
  844. struct bitmain_packet_head packethead;
  845. int asicnum = 0;
  846. int idiff = 0;
  847. int mod = 0,tmp = 0;
  848. for (i = 0; i <= spare; i++) {
  849. if(buf[i] == 0xa1) {
  850. struct bitmain_rxstatus_data rxstatusdata;
  851. applog(LOG_DEBUG, "bitmain_parse_results RxStatus Data");
  852. if(*offset < 4) {
  853. return;
  854. }
  855. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  856. packethead.length = htole16(packethead.length);
  857. if(packethead.length > 1130) {
  858. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus datalen=%d error", packethead.length+4);
  859. continue;
  860. }
  861. if(*offset < packethead.length + 4) {
  862. return;
  863. }
  864. if(bitmain_parse_rxstatus(buf+i, packethead.length+4, &rxstatusdata) != 0) {
  865. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus error len=%d", packethead.length+4);
  866. } else {
  867. mutex_lock(&info->qlock);
  868. info->chain_num = rxstatusdata.chain_num;
  869. info->fifo_space = rxstatusdata.fifo_space;
  870. info->hw_version[0] = rxstatusdata.hw_version[0];
  871. info->hw_version[1] = rxstatusdata.hw_version[1];
  872. info->hw_version[2] = rxstatusdata.hw_version[2];
  873. info->hw_version[3] = rxstatusdata.hw_version[3];
  874. info->nonce_error = rxstatusdata.nonce_error;
  875. errordiff = info->nonce_error-info->last_nonce_error;
  876. //sprintf(g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  877. applog(LOG_ERR, "bitmain_parse_results v=%d chain=%d fifo=%d hwv1=%d hwv2=%d hwv3=%d hwv4=%d nerr=%d-%d freq=%d chain info:",
  878. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  879. info->last_nonce_error, info->nonce_error, info->frequency);
  880. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  881. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  882. for(n = 0; n < rxstatusdata.chain_num; n++) {
  883. info->chain_asic_num[n] = rxstatusdata.chain_asic_num[n];
  884. memset(info->chain_asic_status_t[n], 0, 320);
  885. j = 0;
  886. mod = 0;
  887. if(info->chain_asic_num[n] <= 0) {
  888. asicnum = 0;
  889. } else {
  890. mod = info->chain_asic_num[n] % 32;
  891. if(mod == 0) {
  892. asicnum = info->chain_asic_num[n] / 32;
  893. } else {
  894. asicnum = info->chain_asic_num[n] / 32 + 1;
  895. }
  896. }
  897. if(asicnum > 0) {
  898. for(m = asicnum-1; m >= 0; m--) {
  899. tmp = mod ? (32-mod): 0;
  900. for(r = tmp;r < 32;r++){
  901. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  902. info->chain_asic_status_t[n][j] = ' ';
  903. j++;
  904. }
  905. checkbit = num2bit(r);
  906. if(rxstatusdata.chain_asic_exist[n*8+m] & checkbit) {
  907. if(rxstatusdata.chain_asic_status[n*8+m] & checkbit) {
  908. info->chain_asic_status_t[n][j] = 'o';
  909. } else {
  910. info->chain_asic_status_t[n][j] = 'x';
  911. }
  912. } else {
  913. info->chain_asic_status_t[n][j] = '-';
  914. }
  915. j++;
  916. }
  917. info->chain_asic_status_t[n][j] = ' ';
  918. j++;
  919. mod = 0;
  920. }
  921. }
  922. applog(LOG_DEBUG, "bitmain_parse_results chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  923. n, info->chain_asic_num[n],
  924. info->chain_asic_exist[n*8+0], info->chain_asic_exist[n*8+1], info->chain_asic_exist[n*8+2], info->chain_asic_exist[n*8+3], info->chain_asic_exist[n*8+4], info->chain_asic_exist[n*8+5], info->chain_asic_exist[n*8+6], info->chain_asic_exist[n*8+7],
  925. info->chain_asic_status[n*8+0], info->chain_asic_status[n*8+1], info->chain_asic_status[n*8+2], info->chain_asic_status[n*8+3], info->chain_asic_status[n*8+4], info->chain_asic_status[n*8+5], info->chain_asic_status[n*8+6], info->chain_asic_status[n*8+7]);
  926. applog(LOG_ERR, "bitmain_parse_results chain(%d) asic_num=%d asic_status=%s", n, info->chain_asic_num[n], info->chain_asic_status_t[n]);
  927. }
  928. mutex_unlock(&info->qlock);
  929. if(errordiff > 0) {
  930. for(j = 0; j < errordiff; j++) {
  931. bitmain_inc_nvw(info, thr);
  932. }
  933. mutex_lock(&info->qlock);
  934. info->last_nonce_error += errordiff;
  935. mutex_unlock(&info->qlock);
  936. }
  937. bitmain_update_temps(bitmain, info, &rxstatusdata);
  938. }
  939. found = true;
  940. spare = packethead.length + 4 + i;
  941. if(spare > *offset) {
  942. applog(LOG_ERR, "bitmain_parse_rxresults space(%d) > offset(%d)", spare, *offset);
  943. spare = *offset;
  944. }
  945. break;
  946. } else if(buf[i] == 0xa2) {
  947. struct bitmain_rxnonce_data rxnoncedata;
  948. int nonce_num = 0;
  949. applog(LOG_DEBUG, "bitmain_parse_results RxNonce Data");
  950. if(*offset < 4) {
  951. return;
  952. }
  953. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  954. packethead.length = htole16(packethead.length);
  955. if(packethead.length > 1030) {
  956. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce datalen=%d error", packethead.length+4);
  957. continue;
  958. }
  959. if(*offset < packethead.length + 4) {
  960. return;
  961. }
  962. if(bitmain_parse_rxnonce(buf+i, packethead.length+4, &rxnoncedata, &nonce_num) != 0) {
  963. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce error len=%d", packethead.length+4);
  964. } else {
  965. for(j = 0; j < nonce_num; j++) {
  966. const int work_id = rxnoncedata.nonces[j].work_id;
  967. HASH_FIND_INT(bitmain->queued_work, &work_id, work);
  968. if(work) {
  969. if(BITMAIN_TEST_PRINT_WORK) {
  970. applog(LOG_ERR, "bitmain_parse_results nonce find work(%d-%d)(%08x)", work->id, rxnoncedata.nonces[j].work_id, rxnoncedata.nonces[j].nonce);
  971. char ob_hex[(32 * 2) + 1];
  972. bin2hex(ob_hex, work->midstate, 32);
  973. applog(LOG_ERR, "work %d midstate: %s", work->id, ob_hex);
  974. bin2hex(ob_hex, &work->data[64], 12);
  975. applog(LOG_ERR, "work %d data2: %s", work->id, ob_hex);
  976. }
  977. if(bfg_work_block(work) != info->last_work_block) {
  978. applog(LOG_ERR, "BitMain: bitmain_parse_rxnonce work(%d) nonce stale", rxnoncedata.nonces[j].work_id);
  979. } else {
  980. if (bitmain_decode_nonce(thr, bitmain, info, rxnoncedata.nonces[j].nonce, work)) {
  981. mutex_lock(&info->qlock);
  982. info->nonces++;
  983. info->auto_nonces++;
  984. mutex_unlock(&info->qlock);
  985. } else {
  986. //bitmain_inc_nvw(info, thr);
  987. applog(LOG_ERR, "BitMain: bitmain_decode_nonce error work(%d)", rxnoncedata.nonces[j].work_id);
  988. }
  989. }
  990. } else {
  991. //bitmain_inc_nvw(info, thr);
  992. applog(LOG_ERR, "BitMain: Nonce not find work(%d)", rxnoncedata.nonces[j].work_id);
  993. }
  994. }
  995. #ifdef BITMAIN_CALC_DIFF1
  996. if(opt_bitmain_hwerror) {
  997. int difftmp = 0;
  998. difftmp = rxnoncedata.diff;
  999. idiff = 1;
  1000. while(difftmp > 0) {
  1001. difftmp--;
  1002. idiff = idiff << 1;
  1003. }
  1004. mutex_lock(&info->qlock);
  1005. difftmp = idiff*(rxnoncedata.total_nonce_num-info->total_nonce_num);
  1006. if(difftmp < 0)
  1007. difftmp = 0;
  1008. info->nonces = info->nonces+difftmp;
  1009. info->auto_nonces = info->auto_nonces+difftmp;
  1010. info->total_nonce_num = rxnoncedata.total_nonce_num;
  1011. info->fifo_space = rxnoncedata.fifo_space;
  1012. mutex_unlock(&info->qlock);
  1013. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d diff=%d rxtnn=%"PRIu64" tnn=%"PRIu64, info->fifo_space, idiff, rxnoncedata.total_nonce_num, info->total_nonce_num);
  1014. } else {
  1015. mutex_lock(&info->qlock);
  1016. info->fifo_space = rxnoncedata.fifo_space;
  1017. mutex_unlock(&info->qlock);
  1018. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  1019. }
  1020. #else
  1021. mutex_lock(&info->qlock);
  1022. info->fifo_space = rxnoncedata.fifo_space;
  1023. mutex_unlock(&info->qlock);
  1024. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  1025. #endif
  1026. #ifndef WIN32
  1027. if(nonce_num < BITMAIN_MAX_NONCE_NUM)
  1028. cgsleep_ms(5);
  1029. #endif
  1030. }
  1031. found = true;
  1032. spare = packethead.length + 4 + i;
  1033. if(spare > *offset) {
  1034. applog(LOG_ERR, "bitmain_parse_rxnonce space(%d) > offset(%d)", spare, *offset);
  1035. spare = *offset;
  1036. }
  1037. break;
  1038. } else {
  1039. applog(LOG_ERR, "bitmain_parse_results data type error=%02x", buf[i]);
  1040. }
  1041. }
  1042. if (!found) {
  1043. spare = *offset - BITMAIN_READ_SIZE;
  1044. /* We are buffering and haven't accumulated one more corrupt
  1045. * work result. */
  1046. if (spare < (int)BITMAIN_READ_SIZE)
  1047. return;
  1048. bitmain_inc_nvw(info, thr);
  1049. }
  1050. *offset -= spare;
  1051. memmove(buf, buf + spare, *offset);
  1052. }
  1053. static void bitmain_running_reset(struct cgpu_info *bitmain, struct bitmain_info *info)
  1054. {
  1055. bitmain->results = 0;
  1056. info->reset = false;
  1057. }
  1058. static void *bitmain_get_results(void *userdata)
  1059. {
  1060. struct cgpu_info *bitmain = (struct cgpu_info *)userdata;
  1061. struct bitmain_info *info = bitmain->device_data;
  1062. int offset = 0, ret = 0;
  1063. const int rsize = BITMAIN_FTDI_READSIZE;
  1064. uint8_t readbuf[BITMAIN_READBUF_SIZE];
  1065. struct thr_info *thr = info->thr;
  1066. char threadname[24];
  1067. int errorcount = 0;
  1068. snprintf(threadname, 24, "btm_recv/%d", bitmain->device_id);
  1069. RenameThread(threadname);
  1070. while (likely(!bitmain->shutdown)) {
  1071. unsigned char buf[rsize];
  1072. //applog(LOG_DEBUG, "+++++++bitmain_get_results offset=%d", offset);
  1073. if (offset >= (int)BITMAIN_READ_SIZE) {
  1074. //applog(LOG_DEBUG, "======start bitmain_get_results ");
  1075. bitmain_parse_results(bitmain, info, thr, readbuf, &offset);
  1076. //applog(LOG_DEBUG, "======stop bitmain_get_results ");
  1077. }
  1078. if (unlikely(offset + rsize >= BITMAIN_READBUF_SIZE)) {
  1079. /* This should never happen */
  1080. applog(LOG_DEBUG, "BitMain readbuf overflow, resetting buffer");
  1081. offset = 0;
  1082. }
  1083. if (unlikely(info->reset)) {
  1084. bitmain_running_reset(bitmain, info);
  1085. /* Discard anything in the buffer */
  1086. offset = 0;
  1087. }
  1088. /* As the usb read returns after just 1ms, sleep long enough
  1089. * to leave the interface idle for writes to occur, but do not
  1090. * sleep if we have been receiving data as more may be coming. */
  1091. //if (offset == 0) {
  1092. // cgsleep_ms_r(&ts_start, BITMAIN_READ_TIMEOUT);
  1093. //}
  1094. //cgsleep_prepare_r(&ts_start);
  1095. //applog(LOG_DEBUG, "======start bitmain_get_results bitmain_read");
  1096. ret = bitmain_read(bitmain, buf, rsize, BITMAIN_READ_TIMEOUT);
  1097. //applog(LOG_DEBUG, "======stop bitmain_get_results bitmain_read=%d", ret);
  1098. if ((ret < 1) || (ret == 18)) {
  1099. errorcount++;
  1100. #ifdef WIN32
  1101. if(errorcount > 200) {
  1102. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  1103. cgsleep_ms(20);
  1104. errorcount = 0;
  1105. }
  1106. #else
  1107. if(errorcount > 3) {
  1108. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  1109. cgsleep_ms(20);
  1110. errorcount = 0;
  1111. }
  1112. #endif
  1113. if(ret < 1)
  1114. continue;
  1115. }
  1116. if (opt_debug) {
  1117. char hex[(ret * 2) + 1];
  1118. bin2hex(hex, buf, ret);
  1119. applog(LOG_DEBUG, "BitMain: get: %s", hex);
  1120. }
  1121. memcpy(readbuf+offset, buf, ret);
  1122. offset += ret;
  1123. }
  1124. return NULL;
  1125. }
  1126. static void bitmain_init(struct cgpu_info *bitmain)
  1127. {
  1128. applog(LOG_INFO, "BitMain: Opened on %s", bitmain->device_path);
  1129. }
  1130. static bool bitmain_prepare(struct thr_info *thr)
  1131. {
  1132. struct cgpu_info *bitmain = thr->cgpu;
  1133. struct bitmain_info *info = bitmain->device_data;
  1134. free(bitmain->works);
  1135. bitmain->works = calloc(BITMAIN_MAX_WORK_NUM * sizeof(struct work *),
  1136. BITMAIN_ARRAY_SIZE);
  1137. if (!bitmain->works)
  1138. quit(1, "Failed to calloc bitmain works in bitmain_prepare");
  1139. info->thr = thr;
  1140. mutex_init(&info->lock);
  1141. mutex_init(&info->qlock);
  1142. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1143. quit(1, "Failed to pthread_cond_init bitmain qcond");
  1144. if (pthread_create(&info->read_thr, NULL, bitmain_get_results, (void *)bitmain))
  1145. quit(1, "Failed to create bitmain read_thr");
  1146. bitmain_init(bitmain);
  1147. return true;
  1148. }
  1149. static int bitmain_initialize(struct cgpu_info *bitmain)
  1150. {
  1151. uint8_t data[BITMAIN_READBUF_SIZE];
  1152. struct bitmain_info *info = NULL;
  1153. int ret = 0;
  1154. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1155. int readlen = 0;
  1156. int sendlen = 0;
  1157. int trycount = 3;
  1158. struct timespec p;
  1159. struct bitmain_rxstatus_data rxstatusdata;
  1160. int i = 0, j = 0, m = 0, r = 0, statusok = 0;
  1161. uint32_t checkbit = 0x00000000;
  1162. int hwerror_eft = 0;
  1163. int beeper_ctrl = 1;
  1164. int tempover_ctrl = 1;
  1165. int home_mode = 0;
  1166. struct bitmain_packet_head packethead;
  1167. int asicnum = 0;
  1168. int mod = 0,tmp = 0;
  1169. /* Send reset, then check for result */
  1170. if(!bitmain) {
  1171. applog(LOG_WARNING, "bitmain_initialize cgpu_info is null");
  1172. return -1;
  1173. }
  1174. info = bitmain->device_data;
  1175. /* clear read buf */
  1176. ret = bitmain_read(bitmain, data, BITMAIN_READBUF_SIZE,
  1177. BITMAIN_RESET_TIMEOUT);
  1178. if(ret > 0) {
  1179. if (opt_debug) {
  1180. char hex[(ret * 2) + 1];
  1181. bin2hex(hex, data, ret);
  1182. applog(LOG_DEBUG, "BTM%d Clear Read(%d): %s", bitmain->device_id, ret, hex);
  1183. }
  1184. }
  1185. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *)sendbuf, 0, 1, 0, 0);
  1186. if(sendlen <= 0) {
  1187. applog(LOG_ERR, "bitmain_initialize bitmain_set_rxstatus error(%d)", sendlen);
  1188. return -1;
  1189. }
  1190. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1191. if (unlikely(ret == BTM_SEND_ERROR)) {
  1192. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1193. return -1;
  1194. }
  1195. while(trycount >= 0) {
  1196. ret = bitmain_read(bitmain, data+readlen, BITMAIN_READBUF_SIZE, BITMAIN_RESET_TIMEOUT);
  1197. if(ret > 0) {
  1198. readlen += ret;
  1199. if(readlen > BITMAIN_READ_SIZE) {
  1200. for(i = 0; i < readlen; i++) {
  1201. if(data[i] == 0xa1) {
  1202. if (opt_debug) {
  1203. char hex[(readlen * 2) + 1];
  1204. bin2hex(hex, data, readlen);
  1205. applog(LOG_DEBUG, "%s%d initset: get: %s", bitmain->drv->name, bitmain->device_id, hex);
  1206. }
  1207. memcpy(&packethead, data+i, sizeof(struct bitmain_packet_head));
  1208. packethead.length = htole16(packethead.length);
  1209. if(packethead.length > 1130) {
  1210. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d error", packethead.length+4);
  1211. continue;
  1212. }
  1213. if(readlen-i < packethead.length+4) {
  1214. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d<%d low", readlen-i, packethead.length+4);
  1215. continue;
  1216. }
  1217. if (bitmain_parse_rxstatus(data+i, packethead.length+4, &rxstatusdata) != 0) {
  1218. applog(LOG_ERR, "bitmain_initialize bitmain_parse_rxstatus error");
  1219. continue;
  1220. }
  1221. info->chain_num = rxstatusdata.chain_num;
  1222. info->fifo_space = rxstatusdata.fifo_space;
  1223. info->hw_version[0] = rxstatusdata.hw_version[0];
  1224. info->hw_version[1] = rxstatusdata.hw_version[1];
  1225. info->hw_version[2] = rxstatusdata.hw_version[2];
  1226. info->hw_version[3] = rxstatusdata.hw_version[3];
  1227. info->nonce_error = 0;
  1228. info->last_nonce_error = 0;
  1229. sprintf(info->g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  1230. applog(LOG_ERR, "bitmain_initialize rxstatus v(%d) chain(%d) fifo(%d) hwv1(%d) hwv2(%d) hwv3(%d) hwv4(%d) nerr(%d) freq=%d",
  1231. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  1232. rxstatusdata.nonce_error, info->frequency);
  1233. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  1234. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  1235. for(i = 0; i < rxstatusdata.chain_num; i++) {
  1236. info->chain_asic_num[i] = rxstatusdata.chain_asic_num[i];
  1237. memset(info->chain_asic_status_t[i], 0, 320);
  1238. j = 0;
  1239. mod = 0;
  1240. if(info->chain_asic_num[i] <= 0) {
  1241. asicnum = 0;
  1242. } else {
  1243. mod = info->chain_asic_num[i] % 32;
  1244. if(mod == 0) {
  1245. asicnum = info->chain_asic_num[i] / 32;
  1246. } else {
  1247. asicnum = info->chain_asic_num[i] / 32 + 1;
  1248. }
  1249. }
  1250. if(asicnum > 0) {
  1251. for(m = asicnum-1; m >= 0; m--) {
  1252. tmp = mod ? (32-mod):0;
  1253. for(r = tmp;r < 32;r++){
  1254. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  1255. info->chain_asic_status_t[i][j] = ' ';
  1256. j++;
  1257. }
  1258. checkbit = num2bit(r);
  1259. if(rxstatusdata.chain_asic_exist[i*8+m] & checkbit) {
  1260. if(rxstatusdata.chain_asic_status[i*8+m] & checkbit) {
  1261. info->chain_asic_status_t[i][j] = 'o';
  1262. } else {
  1263. info->chain_asic_status_t[i][j] = 'x';
  1264. }
  1265. } else {
  1266. info->chain_asic_status_t[i][j] = '-';
  1267. }
  1268. j++;
  1269. }
  1270. info->chain_asic_status_t[i][j] = ' ';
  1271. j++;
  1272. mod = 0;
  1273. }
  1274. }
  1275. applog(LOG_DEBUG, "bitmain_initialize chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  1276. i, info->chain_asic_num[i],
  1277. info->chain_asic_exist[i*8+0], info->chain_asic_exist[i*8+1], info->chain_asic_exist[i*8+2], info->chain_asic_exist[i*8+3], info->chain_asic_exist[i*8+4], info->chain_asic_exist[i*8+5], info->chain_asic_exist[i*8+6], info->chain_asic_exist[i*8+7],
  1278. info->chain_asic_status[i*8+0], info->chain_asic_status[i*8+1], info->chain_asic_status[i*8+2], info->chain_asic_status[i*8+3], info->chain_asic_status[i*8+4], info->chain_asic_status[i*8+5], info->chain_asic_status[i*8+6], info->chain_asic_status[i*8+7]);
  1279. applog(LOG_ERR, "bitmain_initialize chain(%d) asic_num=%d asic_status=%s", i, info->chain_asic_num[i], info->chain_asic_status_t[i]);
  1280. }
  1281. bitmain_update_temps(bitmain, info, &rxstatusdata);
  1282. statusok = 1;
  1283. break;
  1284. }
  1285. }
  1286. if(statusok) {
  1287. break;
  1288. }
  1289. }
  1290. }
  1291. trycount--;
  1292. p.tv_sec = 0;
  1293. p.tv_nsec = BITMAIN_RESET_PITCH;
  1294. nanosleep(&p, NULL);
  1295. }
  1296. p.tv_sec = 0;
  1297. p.tv_nsec = BITMAIN_RESET_PITCH;
  1298. nanosleep(&p, NULL);
  1299. cgtime(&info->last_status_time);
  1300. if(statusok) {
  1301. applog(LOG_ERR, "bitmain_initialize start send txconfig");
  1302. if(opt_bitmain_hwerror)
  1303. hwerror_eft = 1;
  1304. else
  1305. hwerror_eft = 0;
  1306. if(opt_bitmain_nobeeper)
  1307. beeper_ctrl = 0;
  1308. else
  1309. beeper_ctrl = 1;
  1310. if(opt_bitmain_notempoverctrl)
  1311. tempover_ctrl = 0;
  1312. else
  1313. tempover_ctrl = 1;
  1314. if(opt_bitmain_homemode)
  1315. home_mode= 1;
  1316. else
  1317. home_mode= 0;
  1318. sendlen = bitmain_set_txconfig((struct bitmain_txconfig_token *)sendbuf, 1, 1, 1, 1, 1, 0, 1, hwerror_eft, beeper_ctrl, tempover_ctrl,home_mode,
  1319. info->chain_num, info->asic_num, BITMAIN_DEFAULT_FAN_MAX_PWM, info->timeout,
  1320. info->frequency, info->voltage, 0, 0, 0x04, info->reg_data);
  1321. if(sendlen <= 0) {
  1322. applog(LOG_ERR, "bitmain_initialize bitmain_set_txconfig error(%d)", sendlen);
  1323. return -1;
  1324. }
  1325. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1326. if (unlikely(ret == BTM_SEND_ERROR)) {
  1327. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1328. return -1;
  1329. }
  1330. applog(LOG_WARNING, "BMM%d: InitSet succeeded", bitmain->device_id);
  1331. } else {
  1332. applog(LOG_WARNING, "BMS%d: InitSet error", bitmain->device_id);
  1333. return -1;
  1334. }
  1335. return 0;
  1336. }
  1337. static bool bitmain_detect_one(const char * devpath)
  1338. {
  1339. struct bitmain_info *info;
  1340. struct cgpu_info *bitmain;
  1341. int ret;
  1342. bitmain = btm_alloc_cgpu(&bitmain_drv, BITMAIN_MINER_THREADS);
  1343. info = bitmain->device_data;
  1344. drv_set_defaults(&bitmain_drv, bitmain_set_device_funcs_init, info, devpath, NULL, 1);
  1345. if (!btm_init(bitmain, devpath))
  1346. goto shin;
  1347. applog(LOG_ERR, "bitmain_detect_one btm init ok");
  1348. info->fan_pwm = BITMAIN_DEFAULT_FAN_MIN_PWM;
  1349. info->temp_max = 0;
  1350. /* This is for check the temp/fan every 3~4s */
  1351. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  1352. if (info->temp_history_count <= 0)
  1353. info->temp_history_count = 1;
  1354. info->temp_history_index = 0;
  1355. info->temp_sum = 0;
  1356. info->temp_old = 0;
  1357. if (!add_cgpu(bitmain))
  1358. goto unshin;
  1359. ret = bitmain_initialize(bitmain);
  1360. applog(LOG_ERR, "bitmain_detect_one stop bitmain_initialize %d", ret);
  1361. if (ret)
  1362. goto unshin;
  1363. info->errorcount = 0;
  1364. applog(LOG_ERR, "BitMain Detected: %s "
  1365. "(chain_num=%d asic_num=%d timeout=%d freq=%d-%s volt=%02x%02x-%s)",
  1366. bitmain->device_path, info->chain_num, info->asic_num, info->timeout,
  1367. info->frequency, info->frequency_t, info->voltage[0], info->voltage[1], info->voltage_t);
  1368. return true;
  1369. unshin:
  1370. btm_uninit(bitmain);
  1371. shin:
  1372. free(bitmain->device_data);
  1373. bitmain->device_data = NULL;
  1374. free(bitmain);
  1375. return false;
  1376. }
  1377. static int bitmain_detect_auto(void)
  1378. {
  1379. const char * const auto_bitmain_dev = "/dev/bitmain-asic";
  1380. applog(LOG_DEBUG, "BTM detect dev: %s", auto_bitmain_dev);
  1381. return bitmain_detect_one(auto_bitmain_dev) ? 1 : 0;
  1382. }
  1383. static void bitmain_detect()
  1384. {
  1385. generic_detect(&bitmain_drv, bitmain_detect_one, bitmain_detect_auto, GDF_REQUIRE_DNAME | GDF_DEFAULT_NOAUTO);
  1386. }
  1387. static void do_bitmain_close(struct thr_info *thr)
  1388. {
  1389. struct cgpu_info *bitmain = thr->cgpu;
  1390. struct bitmain_info *info = bitmain->device_data;
  1391. pthread_join(info->read_thr, NULL);
  1392. bitmain_running_reset(bitmain, info);
  1393. info->no_matching_work = 0;
  1394. }
  1395. /* We use a replacement algorithm to only remove references to work done from
  1396. * the buffer when we need the extra space for new work. */
  1397. static bool bitmain_fill(struct cgpu_info *bitmain)
  1398. {
  1399. struct bitmain_info *info = bitmain->device_data;
  1400. int subid, slot;
  1401. struct work *work;
  1402. bool ret = true;
  1403. int sendret = 0, sendcount = 0, neednum = 0, queuednum = 0, sendnum = 0, sendlen = 0;
  1404. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1405. int senderror = 0;
  1406. struct timeval now;
  1407. int timediff = 0;
  1408. //applog(LOG_DEBUG, "BTM bitmain_fill start--------");
  1409. mutex_lock(&info->qlock);
  1410. if(info->fifo_space <= 0) {
  1411. //applog(LOG_DEBUG, "BTM bitmain_fill fifo space empty--------");
  1412. ret = true;
  1413. goto out_unlock;
  1414. }
  1415. if (bitmain->queued >= BITMAIN_MAX_WORK_QUEUE_NUM) {
  1416. ret = true;
  1417. } else {
  1418. ret = false;
  1419. }
  1420. while(info->fifo_space > 0) {
  1421. neednum = info->fifo_space<BITMAIN_MAX_WORK_NUM?info->fifo_space:BITMAIN_MAX_WORK_NUM;
  1422. queuednum = bitmain->queued;
  1423. applog(LOG_DEBUG, "BTM: Work task queued(%d) fifo space(%d) needsend(%d)", queuednum, info->fifo_space, neednum);
  1424. if(queuednum < neednum) {
  1425. while(true) {
  1426. work = get_queued(bitmain);
  1427. if (unlikely(!work)) {
  1428. break;
  1429. } else {
  1430. applog(LOG_DEBUG, "BTM get work queued number:%d neednum:%d", queuednum, neednum);
  1431. subid = bitmain->queued++;
  1432. work->subid = subid;
  1433. slot = bitmain->work_array + subid;
  1434. if (slot > BITMAIN_ARRAY_SIZE) {
  1435. applog(LOG_DEBUG, "bitmain_fill array cyc %d", BITMAIN_ARRAY_SIZE);
  1436. slot = 0;
  1437. }
  1438. if (likely(bitmain->works[slot])) {
  1439. applog(LOG_DEBUG, "bitmain_fill work_completed %d", slot);
  1440. work_completed(bitmain, bitmain->works[slot]);
  1441. }
  1442. bitmain->works[slot] = work;
  1443. queuednum++;
  1444. if(queuednum >= neednum) {
  1445. break;
  1446. }
  1447. }
  1448. }
  1449. }
  1450. if(queuednum < BITMAIN_MAX_DEAL_QUEUE_NUM) {
  1451. if(queuednum < neednum) {
  1452. applog(LOG_DEBUG, "BTM: No enough work to send, queue num=%d", queuednum);
  1453. break;
  1454. }
  1455. }
  1456. sendnum = queuednum < neednum ? queuednum : neednum;
  1457. sendlen = bitmain_set_txtask(sendbuf, &(info->last_work_block), bitmain->works, BITMAIN_ARRAY_SIZE, bitmain->work_array, sendnum, &sendcount);
  1458. bitmain->queued -= sendnum;
  1459. info->send_full_space += sendnum;
  1460. if (bitmain->queued < 0)
  1461. bitmain->queued = 0;
  1462. if (bitmain->work_array + sendnum > BITMAIN_ARRAY_SIZE) {
  1463. bitmain->work_array = bitmain->work_array + sendnum-BITMAIN_ARRAY_SIZE;
  1464. } else {
  1465. bitmain->work_array += sendnum;
  1466. }
  1467. applog(LOG_DEBUG, "BTM: Send work array %d", bitmain->work_array);
  1468. if (sendlen > 0) {
  1469. info->fifo_space -= sendcount;
  1470. if (info->fifo_space < 0)
  1471. info->fifo_space = 0;
  1472. sendret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1473. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1474. applog(LOG_ERR, "BTM%i: Comms error(buffer)", bitmain->device_id);
  1475. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1476. info->reset = true;
  1477. info->errorcount++;
  1478. senderror = 1;
  1479. if (info->errorcount > 1000) {
  1480. info->errorcount = 0;
  1481. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread", bitmain->drv->name, bitmain->device_id);
  1482. bitmain->shutdown = true;
  1483. }
  1484. break;
  1485. } else {
  1486. applog(LOG_DEBUG, "bitmain_send_data send ret=%d", sendret);
  1487. info->errorcount = 0;
  1488. }
  1489. } else {
  1490. applog(LOG_DEBUG, "BTM: Send work bitmain_set_txtask error: %d", sendlen);
  1491. break;
  1492. }
  1493. }
  1494. out_unlock:
  1495. cgtime(&now);
  1496. timediff = now.tv_sec - info->last_status_time.tv_sec;
  1497. if(timediff < 0) timediff = -timediff;
  1498. if (timediff > BITMAIN_SEND_STATUS_TIME) {
  1499. applog(LOG_DEBUG, "BTM: Send RX Status Token fifo_space(%d) timediff(%d)", info->fifo_space, timediff);
  1500. copy_time(&(info->last_status_time), &now);
  1501. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *) sendbuf, 0, 0, 0, 0);
  1502. if (sendlen > 0) {
  1503. sendret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1504. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1505. applog(LOG_ERR, "BTM%i: Comms error(buffer)", bitmain->device_id);
  1506. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1507. info->reset = true;
  1508. info->errorcount++;
  1509. senderror = 1;
  1510. if (info->errorcount > 1000) {
  1511. info->errorcount = 0;
  1512. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread", bitmain->drv->name, bitmain->device_id);
  1513. bitmain->shutdown = true;
  1514. }
  1515. } else {
  1516. info->errorcount = 0;
  1517. if (info->fifo_space <= 0) {
  1518. senderror = 1;
  1519. }
  1520. }
  1521. }
  1522. }
  1523. if(info->send_full_space > BITMAIN_SEND_FULL_SPACE) {
  1524. info->send_full_space = 0;
  1525. ret = true;
  1526. cgsleep_ms(1);
  1527. }
  1528. mutex_unlock(&info->qlock);
  1529. if(senderror) {
  1530. ret = true;
  1531. applog(LOG_DEBUG, "bitmain_fill send task sleep");
  1532. //cgsleep_ms(1);
  1533. }
  1534. return ret;
  1535. }
  1536. static int64_t bitmain_scanhash(struct thr_info *thr)
  1537. {
  1538. struct cgpu_info *bitmain = thr->cgpu;
  1539. struct bitmain_info *info = bitmain->device_data;
  1540. const int chain_num = info->chain_num;
  1541. int64_t hash_count;
  1542. //applog(LOG_DEBUG, "bitmain_scanhash info->qlock start");
  1543. mutex_lock(&info->qlock);
  1544. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1545. bitmain->results += info->nonces + info->idle;
  1546. if (bitmain->results > chain_num)
  1547. bitmain->results = chain_num;
  1548. if (!info->reset)
  1549. bitmain->results--;
  1550. info->nonces = info->idle = 0;
  1551. mutex_unlock(&info->qlock);
  1552. //applog(LOG_DEBUG, "bitmain_scanhash info->qlock stop");
  1553. /* Check for nothing but consecutive bad results or consistently less
  1554. * results than we should be getting and reset the FPGA if necessary */
  1555. //if (bitmain->results < -chain_num && !info->reset) {
  1556. // applog(LOG_ERR, "BTM%d: Result return rate low, resetting!",
  1557. // bitmain->device_id);
  1558. // info->reset = true;
  1559. //}
  1560. /* This hashmeter is just a utility counter based on returned shares */
  1561. return hash_count;
  1562. }
  1563. static void bitmain_flush_work(struct cgpu_info *bitmain)
  1564. {
  1565. struct bitmain_info *info = bitmain->device_data;
  1566. mutex_lock(&info->qlock);
  1567. /* Will overwrite any work queued */
  1568. applog(LOG_ERR, "bitmain_flush_work queued=%d array=%d", bitmain->queued, bitmain->work_array);
  1569. if(bitmain->queued > 0) {
  1570. if (bitmain->work_array + bitmain->queued > BITMAIN_ARRAY_SIZE) {
  1571. bitmain->work_array = bitmain->work_array + bitmain->queued-BITMAIN_ARRAY_SIZE;
  1572. } else {
  1573. bitmain->work_array += bitmain->queued;
  1574. }
  1575. }
  1576. bitmain->queued = 0;
  1577. //bitmain->work_array = 0;
  1578. //for (int i = 0; i < BITMAIN_ARRAY_SIZE; ++i) {
  1579. // bitmain->works[i] = NULL;
  1580. //}
  1581. //pthread_cond_signal(&info->qcond);
  1582. mutex_unlock(&info->qlock);
  1583. }
  1584. static struct api_data *bitmain_api_stats(struct cgpu_info *cgpu)
  1585. {
  1586. struct api_data *root = NULL;
  1587. struct bitmain_info *info = cgpu->device_data;
  1588. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1589. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1590. root = api_add_int(root, "baud", &(info->baud), false);
  1591. root = api_add_int(root, "miner_count", &(info->chain_num), false);
  1592. root = api_add_int(root, "asic_count", &(info->asic_num), false);
  1593. root = api_add_int(root, "timeout", &(info->timeout), false);
  1594. root = api_add_string(root, "frequency", info->frequency_t, false);
  1595. root = api_add_string(root, "voltage", info->voltage_t, false);
  1596. root = api_add_int(root, "hwv1", &(info->hw_version[0]), false);
  1597. root = api_add_int(root, "hwv2", &(info->hw_version[1]), false);
  1598. root = api_add_int(root, "hwv3", &(info->hw_version[2]), false);
  1599. root = api_add_int(root, "hwv4", &(info->hw_version[3]), false);
  1600. root = api_add_int(root, "fan_num", &(info->fan_num), false);
  1601. root = api_add_int(root, "fan1", &(info->fan[0]), false);
  1602. root = api_add_int(root, "fan2", &(info->fan[1]), false);
  1603. root = api_add_int(root, "fan3", &(info->fan[2]), false);
  1604. root = api_add_int(root, "fan4", &(info->fan[3]), false);
  1605. root = api_add_int(root, "fan5", &(info->fan[4]), false);
  1606. root = api_add_int(root, "fan6", &(info->fan[5]), false);
  1607. root = api_add_int(root, "fan7", &(info->fan[6]), false);
  1608. root = api_add_int(root, "fan8", &(info->fan[7]), false);
  1609. root = api_add_int(root, "fan9", &(info->fan[8]), false);
  1610. root = api_add_int(root, "fan10", &(info->fan[9]), false);
  1611. root = api_add_int(root, "fan11", &(info->fan[10]), false);
  1612. root = api_add_int(root, "fan12", &(info->fan[11]), false);
  1613. root = api_add_int(root, "fan13", &(info->fan[12]), false);
  1614. root = api_add_int(root, "fan14", &(info->fan[13]), false);
  1615. root = api_add_int(root, "fan15", &(info->fan[14]), false);
  1616. root = api_add_int(root, "fan16", &(info->fan[15]), false);
  1617. root = api_add_int(root, "temp_num", &(info->temp_num), false);
  1618. root = api_add_int(root, "temp1", &(info->temp[0]), false);
  1619. root = api_add_int(root, "temp2", &(info->temp[1]), false);
  1620. root = api_add_int(root, "temp3", &(info->temp[2]), false);
  1621. root = api_add_int(root, "temp4", &(info->temp[3]), false);
  1622. root = api_add_int(root, "temp5", &(info->temp[4]), false);
  1623. root = api_add_int(root, "temp6", &(info->temp[5]), false);
  1624. root = api_add_int(root, "temp7", &(info->temp[6]), false);
  1625. root = api_add_int(root, "temp8", &(info->temp[7]), false);
  1626. root = api_add_int(root, "temp9", &(info->temp[8]), false);
  1627. root = api_add_int(root, "temp10", &(info->temp[9]), false);
  1628. root = api_add_int(root, "temp11", &(info->temp[10]), false);
  1629. root = api_add_int(root, "temp12", &(info->temp[11]), false);
  1630. root = api_add_int(root, "temp13", &(info->temp[12]), false);
  1631. root = api_add_int(root, "temp14", &(info->temp[13]), false);
  1632. root = api_add_int(root, "temp15", &(info->temp[14]), false);
  1633. root = api_add_int(root, "temp16", &(info->temp[15]), false);
  1634. root = api_add_int(root, "temp_avg", &(info->temp_avg), false);
  1635. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1636. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1637. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1638. /*
  1639. for (int i = 0; i < info->chain_num; ++i) {
  1640. char mcw[24];
  1641. sprintf(mcw, "match_work_count%d", i + 1);
  1642. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1643. }*/
  1644. root = api_add_int(root, "chain_acn1", &(info->chain_asic_num[0]), false);
  1645. root = api_add_int(root, "chain_acn2", &(info->chain_asic_num[1]), false);
  1646. root = api_add_int(root, "chain_acn3", &(info->chain_asic_num[2]), false);
  1647. root = api_add_int(root, "chain_acn4", &(info->chain_asic_num[3]), false);
  1648. root = api_add_int(root, "chain_acn5", &(info->chain_asic_num[4]), false);
  1649. root = api_add_int(root, "chain_acn6", &(info->chain_asic_num[5]), false);
  1650. root = api_add_int(root, "chain_acn7", &(info->chain_asic_num[6]), false);
  1651. root = api_add_int(root, "chain_acn8", &(info->chain_asic_num[7]), false);
  1652. root = api_add_int(root, "chain_acn9", &(info->chain_asic_num[8]), false);
  1653. root = api_add_int(root, "chain_acn10", &(info->chain_asic_num[9]), false);
  1654. root = api_add_int(root, "chain_acn11", &(info->chain_asic_num[10]), false);
  1655. root = api_add_int(root, "chain_acn12", &(info->chain_asic_num[11]), false);
  1656. root = api_add_int(root, "chain_acn13", &(info->chain_asic_num[12]), false);
  1657. root = api_add_int(root, "chain_acn14", &(info->chain_asic_num[13]), false);
  1658. root = api_add_int(root, "chain_acn15", &(info->chain_asic_num[14]), false);
  1659. root = api_add_int(root, "chain_acn16", &(info->chain_asic_num[15]), false);
  1660. //applog(LOG_ERR, "chain asic status:%s", info->chain_asic_status_t[0]);
  1661. root = api_add_string(root, "chain_acs1", info->chain_asic_status_t[0], false);
  1662. root = api_add_string(root, "chain_acs2", info->chain_asic_status_t[1], false);
  1663. root = api_add_string(root, "chain_acs3", info->chain_asic_status_t[2], false);
  1664. root = api_add_string(root, "chain_acs4", info->chain_asic_status_t[3], false);
  1665. root = api_add_string(root, "chain_acs5", info->chain_asic_status_t[4], false);
  1666. root = api_add_string(root, "chain_acs6", info->chain_asic_status_t[5], false);
  1667. root = api_add_string(root, "chain_acs7", info->chain_asic_status_t[6], false);
  1668. root = api_add_string(root, "chain_acs8", info->chain_asic_status_t[7], false);
  1669. root = api_add_string(root, "chain_acs9", info->chain_asic_status_t[8], false);
  1670. root = api_add_string(root, "chain_acs10", info->chain_asic_status_t[9], false);
  1671. root = api_add_string(root, "chain_acs11", info->chain_asic_status_t[10], false);
  1672. root = api_add_string(root, "chain_acs12", info->chain_asic_status_t[11], false);
  1673. root = api_add_string(root, "chain_acs13", info->chain_asic_status_t[12], false);
  1674. root = api_add_string(root, "chain_acs14", info->chain_asic_status_t[13], false);
  1675. root = api_add_string(root, "chain_acs15", info->chain_asic_status_t[14], false);
  1676. root = api_add_string(root, "chain_acs16", info->chain_asic_status_t[15], false);
  1677. //root = api_add_int(root, "chain_acs1", &(info->chain_asic_status[0]), false);
  1678. //root = api_add_int(root, "chain_acs2", &(info->chain_asic_status[1]), false);
  1679. //root = api_add_int(root, "chain_acs3", &(info->chain_asic_status[2]), false);
  1680. //root = api_add_int(root, "chain_acs4", &(info->chain_asic_status[3]), false);
  1681. return root;
  1682. }
  1683. static void bitmain_shutdown(struct thr_info *thr)
  1684. {
  1685. do_bitmain_close(thr);
  1686. }
  1687. char *set_bitmain_fan(char *arg)
  1688. {
  1689. int val1, val2, ret;
  1690. ret = sscanf(arg, "%d-%d", &val1, &val2);
  1691. if (ret < 1)
  1692. return "No values passed to bitmain-fan";
  1693. if (ret == 1)
  1694. val2 = val1;
  1695. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  1696. return "Invalid value passed to bitmain-fan";
  1697. opt_bitmain_fan_min = val1 * BITMAIN_PWM_MAX / 100;
  1698. opt_bitmain_fan_max = val2 * BITMAIN_PWM_MAX / 100;
  1699. return NULL;
  1700. }
  1701. char *set_bitmain_freq(char *arg)
  1702. {
  1703. int val1, val2, ret;
  1704. ret = sscanf(arg, "%d-%d", &val1, &val2);
  1705. if (ret < 1)
  1706. return "No values passed to bitmain-freq";
  1707. if (ret == 1)
  1708. val2 = val1;
  1709. if (val1 < BITMAIN_MIN_FREQUENCY || val1 > BITMAIN_MAX_FREQUENCY ||
  1710. val2 < BITMAIN_MIN_FREQUENCY || val2 > BITMAIN_MAX_FREQUENCY ||
  1711. val2 < val1)
  1712. return "Invalid value passed to bitmain-freq";
  1713. opt_bitmain_freq_min = val1;
  1714. opt_bitmain_freq_max = val2;
  1715. return NULL;
  1716. }
  1717. const char *bitmain_set_baud(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1718. {
  1719. struct bitmain_info *info = proc->device_data;
  1720. const int baud = atoi(newvalue);
  1721. if (!valid_baud(baud))
  1722. return "Invalid baud setting";
  1723. info->baud = baud;
  1724. return NULL;
  1725. }
  1726. const char *bitmain_set_layout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1727. {
  1728. struct bitmain_info *info = proc->device_data;
  1729. char *endptr, *next_field;
  1730. const long int n_chains = strtol(newvalue, &endptr, 0);
  1731. if (endptr == newvalue || n_chains < 1)
  1732. return "Missing chain count";
  1733. long int n_asics = 0;
  1734. if (endptr[0] == ':' || endptr[1] == ',')
  1735. {
  1736. next_field = &endptr[1];
  1737. n_asics = strtol(next_field, &endptr, 0);
  1738. }
  1739. if (n_asics < 1)
  1740. return "Missing ASIC count";
  1741. if (n_asics > BITMAIN_DEFAULT_ASIC_NUM)
  1742. return "ASIC count too high";
  1743. info->chain_num = n_chains;
  1744. info->asic_num = n_asics;
  1745. return NULL;
  1746. }
  1747. const char *bitmain_set_timeout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1748. {
  1749. struct bitmain_info *info = proc->device_data;
  1750. const int timeout = atoi(newvalue);
  1751. if (timeout < 0 || timeout > 0xff)
  1752. return "Invalid timeout setting";
  1753. info->timeout = timeout;
  1754. return NULL;
  1755. }
  1756. const char *bitmain_set_clock(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1757. {
  1758. struct bitmain_info *info = proc->device_data;
  1759. const int freq = atoi(newvalue);
  1760. if (freq < BITMAIN_MIN_FREQUENCY || freq > BITMAIN_MAX_FREQUENCY)
  1761. return "Invalid clock frequency";
  1762. info->frequency = freq;
  1763. sprintf(info->frequency_t, "%d", freq);
  1764. return NULL;
  1765. }
  1766. const char *bitmain_set_reg_data(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1767. {
  1768. struct bitmain_info *info = proc->device_data;
  1769. uint8_t reg_data[4] = {0};
  1770. if (newvalue[0] == 'x')
  1771. ++newvalue;
  1772. size_t nvlen = strlen(newvalue);
  1773. if (nvlen > (sizeof(reg_data) * 2) || !nvlen || nvlen % 2)
  1774. return "reg_data must be a hex string of 2-8 digits (1-4 bytes)";
  1775. if (!hex2bin(reg_data, newvalue, nvlen / 2))
  1776. return "Invalid reg data hex";
  1777. memcpy(info->reg_data, reg_data, sizeof(reg_data));
  1778. return NULL;
  1779. }
  1780. const char *bitmain_set_voltage(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1781. {
  1782. struct bitmain_info *info = proc->device_data;
  1783. uint8_t voltage_data[2] = {0};
  1784. if (newvalue[0] == 'x')
  1785. ++newvalue;
  1786. else
  1787. voltage_usage:
  1788. return "voltage must be 'x' followed by a hex string of 1-4 digits (1-2 bytes)";
  1789. size_t nvlen = strlen(newvalue);
  1790. if (nvlen > (sizeof(voltage_data) * 2) || !nvlen || nvlen % 2)
  1791. goto voltage_usage;
  1792. if (!hex2bin(voltage_data, newvalue, nvlen / 2))
  1793. return "Invalid voltage data hex";
  1794. memcpy(info->voltage, voltage_data, sizeof(voltage_data));
  1795. bin2hex(info->voltage_t, voltage_data, 2);
  1796. info->voltage_t[5] = 0;
  1797. info->voltage_t[4] = info->voltage_t[3];
  1798. info->voltage_t[3] = info->voltage_t[2];
  1799. info->voltage_t[2] = info->voltage_t[1];
  1800. info->voltage_t[1] = '.';
  1801. return NULL;
  1802. }
  1803. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[] = {
  1804. {"baud", bitmain_set_baud, "serial baud rate"},
  1805. {"layout", bitmain_set_layout, "number of chains ':' number of ASICs per chain (eg: 32:8)"},
  1806. {"timeout", bitmain_set_timeout, "timeout"},
  1807. {"clock", bitmain_set_clock, "clock frequency"},
  1808. {"reg_data", bitmain_set_reg_data, "reg_data (eg: x0d82)"},
  1809. {"voltage", bitmain_set_voltage, "voltage (must be specified as 'x' and hex data; eg: x0725)"},
  1810. {NULL},
  1811. };
  1812. struct device_drv bitmain_drv = {
  1813. .dname = "bitmain",
  1814. .name = "BTM",
  1815. .drv_detect = bitmain_detect,
  1816. .thread_prepare = bitmain_prepare,
  1817. .minerloop = hash_queued_work,
  1818. .queue_full = bitmain_fill,
  1819. .scanwork = bitmain_scanhash,
  1820. .flush_work = bitmain_flush_work,
  1821. .get_api_stats = bitmain_api_stats,
  1822. .reinit_device = bitmain_init,
  1823. .thread_shutdown = bitmain_shutdown,
  1824. };