driver-avalon.c 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464
  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  41. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  42. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  43. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  44. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  45. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  46. bool opt_avalon_auto;
  47. static int option_offset = -1;
  48. struct device_drv avalon_drv;
  49. static int avalon_init_task(struct avalon_task *at,
  50. uint8_t reset, uint8_t ff, uint8_t fan,
  51. uint8_t timeout, uint8_t asic_num,
  52. uint8_t miner_num, uint8_t nonce_elf,
  53. uint8_t gate_miner, int frequency)
  54. {
  55. uint16_t *lefreq16;
  56. uint8_t *buf;
  57. static bool first = true;
  58. if (unlikely(!at))
  59. return -1;
  60. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  61. return -1;
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (unlikely(reset)) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (unlikely(first && !at->reset)) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = nonce_elf;
  81. at->gate_miner_elf = 1;
  82. at->asic_pll = 1;
  83. if (unlikely(gate_miner)) {
  84. at-> gate_miner = 1;
  85. at->asic_pll = 0;
  86. }
  87. buf = (uint8_t *)at;
  88. buf[5] = 0x00;
  89. buf[8] = 0x74;
  90. buf[9] = 0x01;
  91. buf[10] = 0x00;
  92. buf[11] = 0x00;
  93. lefreq16 = (uint16_t *)&buf[6];
  94. *lefreq16 = htole16(frequency * 8);
  95. return 0;
  96. }
  97. static inline void avalon_create_task(struct avalon_task *at,
  98. struct work *work)
  99. {
  100. memcpy(at->midstate, work->midstate, 32);
  101. memcpy(at->data, work->data + 64, 12);
  102. }
  103. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  104. {
  105. int err, amount;
  106. err = usb_write(avalon, buf, len, &amount, ep);
  107. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  108. avalon->device_id, err);
  109. if (unlikely(err != 0)) {
  110. applog(LOG_WARNING, "usb_write error on avalon_write");
  111. return AVA_SEND_ERROR;
  112. }
  113. if (amount != len) {
  114. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  115. return AVA_SEND_ERROR;
  116. }
  117. return AVA_SEND_OK;
  118. }
  119. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  120. {
  121. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  122. int delay, ret, i, ep = C_AVALON_TASK;
  123. struct avalon_info *info;
  124. uint32_t nonce_range;
  125. size_t nr_len;
  126. if (at->nonce_elf)
  127. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  128. else
  129. nr_len = AVALON_WRITE_SIZE;
  130. memcpy(buf, at, AVALON_WRITE_SIZE);
  131. if (at->nonce_elf) {
  132. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  133. for (i = 0; i < at->asic_num; i++) {
  134. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  135. (i * nonce_range & 0xff000000) >> 24;
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  137. (i * nonce_range & 0x00ff0000) >> 16;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  139. (i * nonce_range & 0x0000ff00) >> 8;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  141. (i * nonce_range & 0x000000ff) >> 0;
  142. }
  143. }
  144. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  145. uint8_t tt = 0;
  146. tt = (buf[0] & 0x0f) << 4;
  147. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  148. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  149. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  150. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  151. buf[0] = tt;
  152. tt = (buf[4] & 0x0f) << 4;
  153. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  154. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  155. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  156. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  157. buf[4] = tt;
  158. #endif
  159. info = avalon->device_data;
  160. delay = nr_len * 10 * 1000000;
  161. delay = delay / info->baud;
  162. if (at->reset) {
  163. ep = C_AVALON_RESET;
  164. nr_len = 1;
  165. }
  166. if (opt_debug) {
  167. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  168. hexdump(buf, nr_len);
  169. }
  170. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  171. delay += 4000;
  172. nusleep(delay);
  173. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  174. return ret;
  175. }
  176. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  177. struct avalon_info *info, struct avalon_result *ar,
  178. struct work *work)
  179. {
  180. uint32_t nonce;
  181. info = avalon->device_data;
  182. info->matching_work[work->subid]++;
  183. nonce = htole32(ar->nonce);
  184. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  185. return submit_nonce(thr, work, nonce);
  186. }
  187. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  188. static void wait_avalon_ready(struct cgpu_info *avalon)
  189. {
  190. while (avalon_buffer_full(avalon)) {
  191. nmsleep(40);
  192. }
  193. }
  194. #define AVALON_CTS (1 << 4)
  195. static inline bool avalon_cts(char c)
  196. {
  197. return (c & AVALON_CTS);
  198. }
  199. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  200. size_t bufsize, int timeout, int ep)
  201. {
  202. struct avalon_info *info = avalon->device_data;
  203. size_t total = 0, readsize = bufsize + 2;
  204. char readbuf[AVALON_READBUF_SIZE];
  205. int err, amount, ofs = 2, cp;
  206. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  207. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  208. avalon->drv->name, avalon->device_id, err);
  209. if (amount < 2)
  210. goto out;
  211. /* Use the fact that we're reading the status with the buffer to tell
  212. * the write thread it should send more work without needing to call
  213. * avalon_buffer_full directly. */
  214. if (avalon_cts(readbuf[0]))
  215. cgsem_post(&info->write_sem);
  216. /* The first 2 of every 64 bytes are status on FTDIRL */
  217. while (amount > 2) {
  218. cp = amount - 2;
  219. if (cp > 62)
  220. cp = 62;
  221. memcpy(&buf[total], &readbuf[ofs], cp);
  222. total += cp;
  223. amount -= cp + 2;
  224. ofs += 64;
  225. }
  226. out:
  227. return total;
  228. }
  229. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  230. {
  231. struct avalon_result ar;
  232. int ret, i, spare;
  233. struct avalon_task at;
  234. uint8_t *buf, *tmp;
  235. struct timespec p;
  236. /* Send reset, then check for result */
  237. avalon_init_task(&at, 1, 0,
  238. AVALON_DEFAULT_FAN_MAX_PWM,
  239. AVALON_DEFAULT_TIMEOUT,
  240. AVALON_DEFAULT_ASIC_NUM,
  241. AVALON_DEFAULT_MINER_NUM,
  242. 0, 0,
  243. AVALON_DEFAULT_FREQUENCY);
  244. wait_avalon_ready(avalon);
  245. ret = avalon_send_task(&at, avalon);
  246. if (unlikely(ret == AVA_SEND_ERROR))
  247. return -1;
  248. if (!initial) {
  249. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  250. return 0;
  251. }
  252. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  253. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  254. /* What do these sleeps do?? */
  255. p.tv_sec = 0;
  256. p.tv_nsec = AVALON_RESET_PITCH;
  257. nanosleep(&p, NULL);
  258. /* Look for the first occurrence of 0xAA, the reset response should be:
  259. * AA 55 AA 55 00 00 00 00 00 00 */
  260. spare = ret - 10;
  261. buf = tmp = (uint8_t *)&ar;
  262. if (opt_debug) {
  263. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  264. hexdump(tmp, AVALON_READ_SIZE);
  265. }
  266. for (i = 0; i <= spare; i++) {
  267. buf = &tmp[i];
  268. if (buf[0] == 0xAA)
  269. break;
  270. }
  271. i = 0;
  272. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  273. buf[2] == 0xAA && buf[3] == 0x55) {
  274. for (i = 4; i < 11; i++)
  275. if (buf[i] != 0)
  276. break;
  277. }
  278. if (i != 11) {
  279. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  280. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  281. i, buf[0], buf[1], buf[2], buf[3]);
  282. /* FIXME: return 1; */
  283. } else
  284. applog(LOG_WARNING, "%s%d: Reset succeeded",
  285. avalon->drv->name, avalon->device_id);
  286. return 0;
  287. }
  288. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  289. int *asic_count, int *timeout, int *frequency)
  290. {
  291. char buf[BUFSIZ+1];
  292. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  293. size_t max;
  294. int i, tmp;
  295. if (opt_avalon_options == NULL)
  296. buf[0] = '\0';
  297. else {
  298. ptr = opt_avalon_options;
  299. for (i = 0; i < this_option_offset; i++) {
  300. comma = strchr(ptr, ',');
  301. if (comma == NULL)
  302. break;
  303. ptr = comma + 1;
  304. }
  305. comma = strchr(ptr, ',');
  306. if (comma == NULL)
  307. max = strlen(ptr);
  308. else
  309. max = comma - ptr;
  310. if (max > BUFSIZ)
  311. max = BUFSIZ;
  312. strncpy(buf, ptr, max);
  313. buf[max] = '\0';
  314. }
  315. if (!(*buf))
  316. return false;
  317. colon = strchr(buf, ':');
  318. if (colon)
  319. *(colon++) = '\0';
  320. tmp = atoi(buf);
  321. switch (tmp) {
  322. case 115200:
  323. *baud = 115200;
  324. break;
  325. case 57600:
  326. *baud = 57600;
  327. break;
  328. case 38400:
  329. *baud = 38400;
  330. break;
  331. case 19200:
  332. *baud = 19200;
  333. break;
  334. default:
  335. quit(1, "Invalid avalon-options for baud (%s) "
  336. "must be 115200, 57600, 38400 or 19200", buf);
  337. }
  338. if (colon && *colon) {
  339. colon2 = strchr(colon, ':');
  340. if (colon2)
  341. *(colon2++) = '\0';
  342. if (*colon) {
  343. tmp = atoi(colon);
  344. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  345. *miner_count = tmp;
  346. } else {
  347. quit(1, "Invalid avalon-options for "
  348. "miner_count (%s) must be 1 ~ %d",
  349. colon, AVALON_DEFAULT_MINER_NUM);
  350. }
  351. }
  352. if (colon2 && *colon2) {
  353. colon3 = strchr(colon2, ':');
  354. if (colon3)
  355. *(colon3++) = '\0';
  356. tmp = atoi(colon2);
  357. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  358. *asic_count = tmp;
  359. else {
  360. quit(1, "Invalid avalon-options for "
  361. "asic_count (%s) must be 1 ~ %d",
  362. colon2, AVALON_DEFAULT_ASIC_NUM);
  363. }
  364. if (colon3 && *colon3) {
  365. colon4 = strchr(colon3, ':');
  366. if (colon4)
  367. *(colon4++) = '\0';
  368. tmp = atoi(colon3);
  369. if (tmp > 0 && tmp <= 0xff)
  370. *timeout = tmp;
  371. else {
  372. quit(1, "Invalid avalon-options for "
  373. "timeout (%s) must be 1 ~ %d",
  374. colon3, 0xff);
  375. }
  376. if (colon4 && *colon4) {
  377. tmp = atoi(colon4);
  378. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  379. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  380. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  381. }
  382. *frequency = tmp;
  383. }
  384. }
  385. }
  386. }
  387. return true;
  388. }
  389. char *set_avalon_fan(char *arg)
  390. {
  391. int val1, val2, ret;
  392. ret = sscanf(arg, "%d-%d", &val1, &val2);
  393. if (ret < 1)
  394. return "No values passed to avalon-fan";
  395. if (ret == 1)
  396. val2 = val1;
  397. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  398. return "Invalid value passed to avalon-fan";
  399. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  400. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  401. return NULL;
  402. }
  403. char *set_avalon_freq(char *arg)
  404. {
  405. int val1, val2, ret;
  406. ret = sscanf(arg, "%d-%d", &val1, &val2);
  407. if (ret < 1)
  408. return "No values passed to avalon-freq";
  409. if (ret == 1)
  410. val2 = val1;
  411. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  412. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  413. val2 < val1)
  414. return "Invalid value passed to avalon-freq";
  415. opt_avalon_freq_min = val1;
  416. opt_avalon_freq_max = val2;
  417. return NULL;
  418. }
  419. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  420. {
  421. int i;
  422. wait_avalon_ready(avalon);
  423. /* Send idle to all miners */
  424. for (i = 0; i < info->miner_count; i++) {
  425. struct avalon_task at;
  426. if (unlikely(avalon_buffer_full(avalon)))
  427. break;
  428. info->idle++;
  429. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  430. info->asic_count, info->miner_count, 1, 1,
  431. info->frequency);
  432. avalon_send_task(&at, avalon);
  433. }
  434. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  435. wait_avalon_ready(avalon);
  436. }
  437. static void avalon_initialise(struct cgpu_info *avalon)
  438. {
  439. int err, interface;
  440. if (avalon->usbinfo.nodev)
  441. return;
  442. interface = avalon->usbdev->found->interface;
  443. // Reset
  444. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  445. FTDI_VALUE_RESET, interface, C_RESET);
  446. applog(LOG_DEBUG, "%s%i: reset got err %d",
  447. avalon->drv->name, avalon->device_id, err);
  448. if (avalon->usbinfo.nodev)
  449. return;
  450. // Set latency
  451. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  452. AVALON_LATENCY, interface, C_LATENCY);
  453. applog(LOG_DEBUG, "%s%i: latency got err %d",
  454. avalon->drv->name, avalon->device_id, err);
  455. if (avalon->usbinfo.nodev)
  456. return;
  457. // Set data
  458. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  459. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  460. applog(LOG_DEBUG, "%s%i: data got err %d",
  461. avalon->drv->name, avalon->device_id, err);
  462. if (avalon->usbinfo.nodev)
  463. return;
  464. // Set the baud
  465. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  466. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  467. C_SETBAUD);
  468. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  469. avalon->drv->name, avalon->device_id, err);
  470. if (avalon->usbinfo.nodev)
  471. return;
  472. // Set Modem Control
  473. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  474. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  475. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  476. avalon->drv->name, avalon->device_id, err);
  477. if (avalon->usbinfo.nodev)
  478. return;
  479. // Set Flow Control
  480. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  481. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  482. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  483. avalon->drv->name, avalon->device_id, err);
  484. if (avalon->usbinfo.nodev)
  485. return;
  486. /* Avalon repeats the following */
  487. // Set Modem Control
  488. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  489. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  490. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  491. avalon->drv->name, avalon->device_id, err);
  492. if (avalon->usbinfo.nodev)
  493. return;
  494. // Set Flow Control
  495. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  496. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  497. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  498. avalon->drv->name, avalon->device_id, err);
  499. }
  500. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  501. {
  502. uint8_t buf[2];
  503. int err;
  504. if (usb_ident(avalon) == IDENT_BTB) {
  505. buf[0] = (uint8_t)core_voltage;
  506. buf[1] = (uint8_t)(core_voltage >> 8);
  507. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  508. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  509. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  510. if (unlikely(err < 0)) {
  511. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  512. avalon->drv->name, avalon->device_id, err);
  513. return false;
  514. } else {
  515. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  516. avalon->drv->name, avalon->device_id,
  517. core_voltage);
  518. }
  519. return true;
  520. }
  521. return false;
  522. }
  523. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  524. {
  525. uint8_t buf[2];
  526. int err;
  527. int amount;
  528. if (usb_ident(avalon) == IDENT_BTB) {
  529. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  530. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  531. (char *)buf, sizeof(buf), &amount,
  532. C_BB_GET_VOLTAGE);
  533. if (unlikely(err != 0 || amount != 2)) {
  534. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  535. avalon->drv->name, avalon->device_id, err, amount);
  536. return 0;
  537. } else {
  538. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  539. }
  540. } else {
  541. return 0;
  542. }
  543. }
  544. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  545. {
  546. int baud, uninitialised_var(miner_count), uninitialised_var(asic_count),
  547. uninitialised_var(timeout), frequency = 0;
  548. int this_option_offset = ++option_offset;
  549. struct avalon_info *info;
  550. struct cgpu_info *avalon;
  551. bool configured;
  552. int ret;
  553. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  554. configured = get_options(this_option_offset, &baud, &miner_count,
  555. &asic_count, &timeout, &frequency);
  556. if (!usb_init(avalon, dev, found))
  557. goto shin;
  558. /* Even though this is an FTDI type chip, we want to do the parsing
  559. * all ourselves so set it to std usb type */
  560. avalon->usbdev->usb_type = USB_TYPE_STD;
  561. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  562. /* We have a real Avalon! */
  563. avalon_initialise(avalon);
  564. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  565. if (unlikely(!(avalon->device_data)))
  566. quit(1, "Failed to calloc avalon_info data");
  567. info = avalon->device_data;
  568. if (configured) {
  569. info->baud = baud;
  570. info->miner_count = miner_count;
  571. info->asic_count = asic_count;
  572. info->timeout = timeout;
  573. info->frequency = frequency;
  574. } else {
  575. info->baud = AVALON_IO_SPEED;
  576. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  577. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  578. info->timeout = AVALON_DEFAULT_TIMEOUT;
  579. info->frequency = AVALON_DEFAULT_FREQUENCY;
  580. }
  581. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  582. info->temp_max = 0;
  583. /* This is for check the temp/fan every 3~4s */
  584. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  585. if (info->temp_history_count <= 0)
  586. info->temp_history_count = 1;
  587. info->temp_history_index = 0;
  588. info->temp_sum = 0;
  589. info->temp_old = 0;
  590. if (!add_cgpu(avalon))
  591. goto unshin;
  592. ret = avalon_reset(avalon, true);
  593. if (ret && !configured)
  594. goto unshin;
  595. update_usb_stats(avalon);
  596. avalon_idle(avalon, info);
  597. applog(LOG_DEBUG, "Avalon Detected: %s "
  598. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  599. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  600. info->frequency);
  601. if (usb_ident(avalon) == IDENT_BTB) {
  602. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  603. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  604. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  605. opt_bitburner_core_voltage,
  606. BITBURNER_MIN_COREMV,
  607. BITBURNER_MAX_COREMV);
  608. } else
  609. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  610. }
  611. return true;
  612. unshin:
  613. usb_uninit(avalon);
  614. shin:
  615. free(avalon->device_data);
  616. avalon->device_data = NULL;
  617. avalon = usb_free_cgpu(avalon);
  618. return false;
  619. }
  620. static void avalon_detect(void)
  621. {
  622. usb_detect(&avalon_drv, avalon_detect_one);
  623. }
  624. static void avalon_init(struct cgpu_info *avalon)
  625. {
  626. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  627. }
  628. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  629. {
  630. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  631. (char *)ar->data, 64, 12);
  632. }
  633. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  634. struct avalon_result *ar);
  635. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  636. {
  637. applog(LOG_INFO, "%s%d: No matching work - HW error",
  638. thr->cgpu->drv->name, thr->cgpu->device_id);
  639. inc_hw_errors(thr);
  640. info->no_matching_work++;
  641. }
  642. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  643. struct thr_info *thr, char *buf, int *offset)
  644. {
  645. int i, spare = *offset - AVALON_READ_SIZE;
  646. bool found = false;
  647. for (i = 0; i <= spare; i++) {
  648. struct avalon_result *ar;
  649. struct work *work;
  650. ar = (struct avalon_result *)&buf[i];
  651. work = avalon_valid_result(avalon, ar);
  652. if (work) {
  653. bool gettemp = false;
  654. found = true;
  655. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  656. mutex_lock(&info->lock);
  657. if (!info->nonces++)
  658. gettemp = true;
  659. info->auto_nonces++;
  660. mutex_unlock(&info->lock);
  661. } else if (opt_avalon_auto) {
  662. mutex_lock(&info->lock);
  663. info->auto_hw++;
  664. mutex_unlock(&info->lock);
  665. }
  666. if (gettemp)
  667. avalon_update_temps(avalon, info, ar);
  668. break;
  669. }
  670. }
  671. if (!found) {
  672. spare = *offset - AVALON_READ_SIZE;
  673. /* We are buffering and haven't accumulated one more corrupt
  674. * work result. */
  675. if (spare < (int)AVALON_READ_SIZE)
  676. return;
  677. avalon_inc_nvw(info, thr);
  678. } else {
  679. spare = AVALON_READ_SIZE + i;
  680. if (i) {
  681. if (i >= (int)AVALON_READ_SIZE)
  682. avalon_inc_nvw(info, thr);
  683. else
  684. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  685. }
  686. }
  687. *offset -= spare;
  688. memmove(buf, buf + spare, *offset);
  689. }
  690. static void avalon_running_reset(struct cgpu_info *avalon,
  691. struct avalon_info *info)
  692. {
  693. avalon_reset(avalon, false);
  694. avalon_idle(avalon, info);
  695. avalon->results = 0;
  696. info->reset = false;
  697. }
  698. static void *avalon_get_results(void *userdata)
  699. {
  700. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  701. struct avalon_info *info = avalon->device_data;
  702. int offset = 0, read_delay = 0, ret = 0;
  703. const int rsize = AVALON_FTDI_READSIZE;
  704. char readbuf[AVALON_READBUF_SIZE];
  705. struct thr_info *thr = info->thr;
  706. struct timeval tv_start, tv_end;
  707. char threadname[24];
  708. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  709. RenameThread(threadname);
  710. while (likely(!avalon->shutdown)) {
  711. unsigned char buf[rsize];
  712. struct timeval tv_diff;
  713. int us_diff;
  714. if (offset >= (int)AVALON_READ_SIZE)
  715. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  716. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  717. /* This should never happen */
  718. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  719. offset = 0;
  720. }
  721. if (unlikely(info->reset)) {
  722. avalon_running_reset(avalon, info);
  723. /* Discard anything in the buffer */
  724. offset = 0;
  725. }
  726. /* As the usb read returns after just 1ms, sleep long enough
  727. * to leave the interface idle for writes to occur, but do not
  728. * sleep if we have been receiving data as more may be coming. */
  729. if (ret < 1) {
  730. cgtime(&tv_end);
  731. timersub(&tv_end, &tv_start, &tv_diff);
  732. /* Assume it has not been > 1 second so ignore tv_sec */
  733. us_diff = tv_diff.tv_usec;
  734. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  735. if (likely(read_delay >= 1000))
  736. nusleep(read_delay);
  737. }
  738. cgtime(&tv_start);
  739. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  740. C_AVALON_READ);
  741. if (ret < 1)
  742. continue;
  743. if (opt_debug) {
  744. applog(LOG_DEBUG, "Avalon: get:");
  745. hexdump((uint8_t *)buf, ret);
  746. }
  747. memcpy(&readbuf[offset], &buf, ret);
  748. offset += ret;
  749. }
  750. return NULL;
  751. }
  752. static void avalon_rotate_array(struct cgpu_info *avalon)
  753. {
  754. avalon->queued = 0;
  755. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  756. avalon->work_array = 0;
  757. }
  758. static void avalon_set_timeout(struct avalon_info *info)
  759. {
  760. info->timeout = AVALON_TIMEOUT_FACTOR / info->frequency;
  761. }
  762. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  763. {
  764. struct avalon_info *info = avalon->device_data;
  765. info->frequency = frequency;
  766. if (info->frequency > opt_avalon_freq_max)
  767. info->frequency = opt_avalon_freq_max;
  768. if (info->frequency < opt_avalon_freq_min)
  769. info->frequency = opt_avalon_freq_min;
  770. avalon_set_timeout(info);
  771. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  772. avalon->drv->name, avalon->device_id,
  773. info->frequency, info->timeout);
  774. }
  775. static void avalon_inc_freq(struct avalon_info *info)
  776. {
  777. info->frequency += 2;
  778. if (info->frequency > opt_avalon_freq_max)
  779. info->frequency = opt_avalon_freq_max;
  780. avalon_set_timeout(info);
  781. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  782. info->frequency, info->timeout);
  783. }
  784. static void avalon_dec_freq(struct avalon_info *info)
  785. {
  786. info->frequency -= 1;
  787. if (info->frequency < opt_avalon_freq_min)
  788. info->frequency = opt_avalon_freq_min;
  789. avalon_set_timeout(info);
  790. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  791. info->frequency, info->timeout);
  792. }
  793. static void avalon_reset_auto(struct avalon_info *info)
  794. {
  795. info->auto_queued =
  796. info->auto_nonces =
  797. info->auto_hw = 0;
  798. }
  799. static void *avalon_send_tasks(void *userdata)
  800. {
  801. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  802. struct avalon_info *info = avalon->device_data;
  803. const int avalon_get_work_count = info->miner_count;
  804. char threadname[24];
  805. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  806. RenameThread(threadname);
  807. while (likely(!avalon->shutdown)) {
  808. int start_count, end_count, i, j, ret;
  809. struct avalon_task at;
  810. bool idled = false;
  811. while (avalon_buffer_full(avalon))
  812. cgsem_wait(&info->write_sem);
  813. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  814. mutex_lock(&info->lock);
  815. if (!info->optimal) {
  816. if (info->fan_pwm >= opt_avalon_fan_max) {
  817. applog(LOG_WARNING,
  818. "%s%i: Above optimal temperature, throttling",
  819. avalon->drv->name, avalon->device_id);
  820. avalon_dec_freq(info);
  821. }
  822. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  823. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  824. int total = info->auto_nonces + info->auto_hw;
  825. /* Try to keep hw errors < 2% */
  826. if (info->auto_hw * 100 < total)
  827. avalon_inc_freq(info);
  828. else if (info->auto_hw * 66 > total)
  829. avalon_dec_freq(info);
  830. }
  831. avalon_reset_auto(info);
  832. mutex_unlock(&info->lock);
  833. }
  834. mutex_lock(&info->qlock);
  835. start_count = avalon->work_array * avalon_get_work_count;
  836. end_count = start_count + avalon_get_work_count;
  837. for (i = start_count, j = 0; i < end_count; i++, j++) {
  838. if (avalon_buffer_full(avalon)) {
  839. applog(LOG_INFO,
  840. "%s%i: Buffer full after only %d of %d work queued",
  841. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  842. if (usb_ident(avalon) != IDENT_BTB)
  843. break;
  844. else {
  845. while (avalon_buffer_full(avalon))
  846. cgsem_wait(&info->write_sem);
  847. }
  848. }
  849. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  850. avalon_init_task(&at, 0, 0, info->fan_pwm,
  851. info->timeout, info->asic_count,
  852. info->miner_count, 1, 0, info->frequency);
  853. avalon_create_task(&at, avalon->works[i]);
  854. info->auto_queued++;
  855. } else {
  856. int idle_freq = info->frequency;
  857. if (!info->idle++)
  858. idled = true;
  859. if (unlikely(info->overheat && opt_avalon_auto))
  860. idle_freq = AVALON_MIN_FREQUENCY;
  861. avalon_init_task(&at, 0, 0, info->fan_pwm,
  862. info->timeout, info->asic_count,
  863. info->miner_count, 1, 1, idle_freq);
  864. /* Reset the auto_queued count if we end up
  865. * idling any miners. */
  866. avalon_reset_auto(info);
  867. }
  868. ret = avalon_send_task(&at, avalon);
  869. if (unlikely(ret == AVA_SEND_ERROR)) {
  870. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  871. avalon->drv->name, avalon->device_id);
  872. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  873. info->reset = true;
  874. break;
  875. }
  876. }
  877. avalon_rotate_array(avalon);
  878. pthread_cond_signal(&info->qcond);
  879. mutex_unlock(&info->qlock);
  880. if (unlikely(idled)) {
  881. applog(LOG_WARNING, "%s%i: Idled %d miners",
  882. avalon->drv->name, avalon->device_id, idled);
  883. }
  884. }
  885. return NULL;
  886. }
  887. static bool avalon_prepare(struct thr_info *thr)
  888. {
  889. struct cgpu_info *avalon = thr->cgpu;
  890. struct avalon_info *info = avalon->device_data;
  891. free(avalon->works);
  892. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  893. AVALON_ARRAY_SIZE);
  894. if (!avalon->works)
  895. quit(1, "Failed to calloc avalon works in avalon_prepare");
  896. info->thr = thr;
  897. mutex_init(&info->lock);
  898. mutex_init(&info->qlock);
  899. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  900. quit(1, "Failed to pthread_cond_init avalon qcond");
  901. cgsem_init(&info->write_sem);
  902. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  903. quit(1, "Failed to create avalon read_thr");
  904. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  905. quit(1, "Failed to create avalon write_thr");
  906. avalon_init(avalon);
  907. return true;
  908. }
  909. static void do_avalon_close(struct thr_info *thr)
  910. {
  911. struct cgpu_info *avalon = thr->cgpu;
  912. struct avalon_info *info = avalon->device_data;
  913. pthread_join(info->read_thr, NULL);
  914. pthread_join(info->write_thr, NULL);
  915. avalon_running_reset(avalon, info);
  916. info->no_matching_work = 0;
  917. cgsem_destroy(&info->write_sem);
  918. }
  919. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  920. {
  921. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  922. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  923. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  924. info->temp0 = ar->temp0;
  925. info->temp1 = ar->temp1;
  926. info->temp2 = ar->temp2;
  927. if (ar->temp0 & 0x80) {
  928. ar->temp0 &= 0x7f;
  929. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  930. }
  931. if (ar->temp1 & 0x80) {
  932. ar->temp1 &= 0x7f;
  933. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  934. }
  935. if (ar->temp2 & 0x80) {
  936. ar->temp2 &= 0x7f;
  937. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  938. }
  939. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  940. if (info->temp0 > info->temp_max)
  941. info->temp_max = info->temp0;
  942. if (info->temp1 > info->temp_max)
  943. info->temp_max = info->temp1;
  944. if (info->temp2 > info->temp_max)
  945. info->temp_max = info->temp2;
  946. }
  947. static void temp_rise(struct avalon_info *info, int temp)
  948. {
  949. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  950. info->fan_pwm = AVALON_PWM_MAX;
  951. return;
  952. }
  953. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  954. info->fan_pwm += 10;
  955. else if (temp > opt_avalon_temp)
  956. info->fan_pwm += 5;
  957. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  958. info->fan_pwm += 1;
  959. else
  960. return;
  961. if (info->fan_pwm > opt_avalon_fan_max)
  962. info->fan_pwm = opt_avalon_fan_max;
  963. }
  964. static void temp_drop(struct avalon_info *info, int temp)
  965. {
  966. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  967. info->fan_pwm = opt_avalon_fan_min;
  968. return;
  969. }
  970. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  971. info->fan_pwm -= 10;
  972. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  973. info->fan_pwm -= 5;
  974. else if (temp < opt_avalon_temp)
  975. info->fan_pwm -= 1;
  976. if (info->fan_pwm < opt_avalon_fan_min)
  977. info->fan_pwm = opt_avalon_fan_min;
  978. }
  979. static inline void adjust_fan(struct avalon_info *info)
  980. {
  981. int temp_new;
  982. temp_new = info->temp_sum / info->temp_history_count;
  983. if (temp_new > info->temp_old)
  984. temp_rise(info, temp_new);
  985. else if (temp_new < info->temp_old)
  986. temp_drop(info, temp_new);
  987. else {
  988. /* temp_new == info->temp_old */
  989. if (temp_new > opt_avalon_temp)
  990. temp_rise(info, temp_new);
  991. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  992. temp_drop(info, temp_new);
  993. }
  994. info->temp_old = temp_new;
  995. if (info->temp_old <= opt_avalon_temp)
  996. info->optimal = true;
  997. else
  998. info->optimal = false;
  999. }
  1000. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1001. struct avalon_result *ar)
  1002. {
  1003. record_temp_fan(info, ar, &(avalon->temp));
  1004. applog(LOG_INFO,
  1005. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1006. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1007. info->fan0, info->fan1, info->fan2,
  1008. info->temp0, info->temp1, info->temp2, info->temp_max);
  1009. info->temp_history_index++;
  1010. info->temp_sum += avalon->temp;
  1011. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1012. info->temp_history_index, info->temp_history_count, info->temp_old);
  1013. if (usb_ident(avalon) == IDENT_BTB) {
  1014. info->core_voltage = bitburner_get_core_voltage(avalon);
  1015. }
  1016. if (info->temp_history_index == info->temp_history_count) {
  1017. adjust_fan(info);
  1018. info->temp_history_index = 0;
  1019. info->temp_sum = 0;
  1020. }
  1021. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1022. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1023. info->overheat = true;
  1024. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1025. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1026. info->overheat = false;
  1027. }
  1028. }
  1029. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1030. {
  1031. struct avalon_info *info = avalon->device_data;
  1032. int lowfan = 10000;
  1033. if (usb_ident(avalon) == IDENT_BTB) {
  1034. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1035. } else {
  1036. /* Find the lowest fan speed of the ASIC cooling fans. */
  1037. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1038. lowfan = info->fan1;
  1039. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1040. lowfan = info->fan2;
  1041. tailsprintf(buf, bufsiz, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1042. }
  1043. }
  1044. /* We use a replacement algorithm to only remove references to work done from
  1045. * the buffer when we need the extra space for new work. */
  1046. static bool avalon_fill(struct cgpu_info *avalon)
  1047. {
  1048. struct avalon_info *info = avalon->device_data;
  1049. int subid, slot, mc;
  1050. struct work *work;
  1051. bool ret = true;
  1052. mc = info->miner_count;
  1053. mutex_lock(&info->qlock);
  1054. if (avalon->queued >= mc)
  1055. goto out_unlock;
  1056. work = get_queued(avalon);
  1057. if (unlikely(!work)) {
  1058. ret = false;
  1059. goto out_unlock;
  1060. }
  1061. subid = avalon->queued++;
  1062. work->subid = subid;
  1063. slot = avalon->work_array * mc + subid;
  1064. if (likely(avalon->works[slot]))
  1065. work_completed(avalon, avalon->works[slot]);
  1066. avalon->works[slot] = work;
  1067. if (avalon->queued < mc)
  1068. ret = false;
  1069. out_unlock:
  1070. mutex_unlock(&info->qlock);
  1071. return ret;
  1072. }
  1073. static int64_t avalon_scanhash(struct thr_info *thr)
  1074. {
  1075. struct cgpu_info *avalon = thr->cgpu;
  1076. struct avalon_info *info = avalon->device_data;
  1077. const int miner_count = info->miner_count;
  1078. struct timeval now, then, tdiff;
  1079. int64_t hash_count, us_timeout;
  1080. struct timespec abstime;
  1081. int ret;
  1082. /* Half nonce range */
  1083. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1084. tdiff.tv_sec = us_timeout / 1000000;
  1085. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  1086. cgtime(&now);
  1087. timeradd(&now, &tdiff, &then);
  1088. abstime.tv_sec = then.tv_sec;
  1089. abstime.tv_nsec = then.tv_usec * 1000;
  1090. /* Wait until avalon_send_tasks signals us that it has completed
  1091. * sending its work or a full nonce range timeout has occurred */
  1092. mutex_lock(&info->qlock);
  1093. ret = pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1094. mutex_unlock(&info->qlock);
  1095. /* If we timed out, avalon_send_tasks may be stuck waiting on the
  1096. * write_sem, so force it to check for avalon_buffer_full itself. */
  1097. if (ret)
  1098. cgsem_post(&info->write_sem);
  1099. mutex_lock(&info->lock);
  1100. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1101. avalon->results += info->nonces + info->idle;
  1102. if (avalon->results > miner_count)
  1103. avalon->results = miner_count;
  1104. if (!info->reset)
  1105. avalon->results--;
  1106. info->nonces = info->idle = 0;
  1107. mutex_unlock(&info->lock);
  1108. /* Check for nothing but consecutive bad results or consistently less
  1109. * results than we should be getting and reset the FPGA if necessary */
  1110. if (usb_ident(avalon) != IDENT_BTB) {
  1111. if (avalon->results < -miner_count && !info->reset) {
  1112. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1113. avalon->drv->name, avalon->device_id);
  1114. info->reset = true;
  1115. }
  1116. }
  1117. if (unlikely(avalon->usbinfo.nodev)) {
  1118. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1119. avalon->drv->name, avalon->device_id);
  1120. avalon->shutdown = true;
  1121. }
  1122. /* This hashmeter is just a utility counter based on returned shares */
  1123. return hash_count;
  1124. }
  1125. static void avalon_flush_work(struct cgpu_info *avalon)
  1126. {
  1127. struct avalon_info *info = avalon->device_data;
  1128. mutex_lock(&info->qlock);
  1129. /* Will overwrite any work queued */
  1130. avalon->queued = 0;
  1131. pthread_cond_signal(&info->qcond);
  1132. mutex_unlock(&info->qlock);
  1133. }
  1134. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1135. {
  1136. struct api_data *root = NULL;
  1137. struct avalon_info *info = cgpu->device_data;
  1138. int i;
  1139. root = api_add_int(root, "baud", &(info->baud), false);
  1140. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1141. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1142. root = api_add_int(root, "timeout", &(info->timeout), false);
  1143. root = api_add_int(root, "frequency", &(info->frequency), false);
  1144. root = api_add_int(root, "fan1", &(info->fan0), false);
  1145. root = api_add_int(root, "fan2", &(info->fan1), false);
  1146. root = api_add_int(root, "fan3", &(info->fan2), false);
  1147. root = api_add_int(root, "temp1", &(info->temp0), false);
  1148. root = api_add_int(root, "temp2", &(info->temp1), false);
  1149. root = api_add_int(root, "temp3", &(info->temp2), false);
  1150. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1151. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1152. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1153. for (i = 0; i < info->miner_count; i++) {
  1154. char mcw[24];
  1155. sprintf(mcw, "match_work_count%d", i + 1);
  1156. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1157. }
  1158. return root;
  1159. }
  1160. static void avalon_shutdown(struct thr_info *thr)
  1161. {
  1162. do_avalon_close(thr);
  1163. }
  1164. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1165. {
  1166. int val;
  1167. if (strcasecmp(option, "help") == 0) {
  1168. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1169. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1170. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1171. return replybuf;
  1172. }
  1173. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1174. if (usb_ident(avalon) != IDENT_BTB) {
  1175. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1176. return replybuf;
  1177. }
  1178. if (!setting || !*setting) {
  1179. sprintf(replybuf, "missing millivolts setting");
  1180. return replybuf;
  1181. }
  1182. val = atoi(setting);
  1183. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1184. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1185. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1186. return replybuf;
  1187. }
  1188. if (bitburner_set_core_voltage(avalon, val))
  1189. return NULL;
  1190. else {
  1191. sprintf(replybuf, "Set millivolts failed");
  1192. return replybuf;
  1193. }
  1194. }
  1195. if (strcasecmp(option, "freq") == 0) {
  1196. if (!setting || !*setting) {
  1197. sprintf(replybuf, "missing freq setting");
  1198. return replybuf;
  1199. }
  1200. val = atoi(setting);
  1201. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1202. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1203. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1204. return replybuf;
  1205. }
  1206. avalon_set_freq(avalon, val);
  1207. return NULL;
  1208. }
  1209. sprintf(replybuf, "Unknown option: %s", option);
  1210. return replybuf;
  1211. }
  1212. struct device_drv avalon_drv = {
  1213. .drv_id = DRIVER_AVALON,
  1214. .dname = "avalon",
  1215. .name = "AVA",
  1216. .drv_detect = avalon_detect,
  1217. .thread_prepare = avalon_prepare,
  1218. .hash_work = hash_queued_work,
  1219. .queue_full = avalon_fill,
  1220. .scanwork = avalon_scanhash,
  1221. .flush_work = avalon_flush_work,
  1222. .get_api_stats = avalon_api_stats,
  1223. .get_statline_before = get_avalon_statline_before,
  1224. .set_device = avalon_set_device,
  1225. .reinit_device = avalon_init,
  1226. .thread_shutdown = avalon_shutdown,
  1227. };