driver-avalon.c 26 KB

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  1. /*
  2. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Luke Dashjr
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static int option_offset = -1;
  36. struct avalon_info **avalon_info;
  37. struct device_api avalon_api;
  38. static inline uint8_t rev8(uint8_t d)
  39. {
  40. int i;
  41. uint8_t out = 0;
  42. /* from left to right */
  43. for (i = 0; i < 8; i++)
  44. if (d & (1 << i))
  45. out |= (1 << (7 - i));
  46. return out;
  47. }
  48. static int avalon_init_task(struct avalon_task *at,
  49. uint8_t reset, uint8_t ff, uint8_t fan,
  50. uint8_t timeout, uint8_t asic_num,
  51. uint8_t miner_num, uint8_t nonce_elf,
  52. uint8_t gate_miner, int frequency)
  53. {
  54. uint8_t *buf;
  55. static bool first = true;
  56. if (unlikely(!at))
  57. return -1;
  58. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  59. return -1;
  60. memset(at, 0, sizeof(struct avalon_task));
  61. if (unlikely(reset)) {
  62. at->reset = 1;
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = true;
  66. }
  67. at->flush_fifo = (ff ? 1 : 0);
  68. at->fan_eft = (fan ? 1 : 0);
  69. if (unlikely(first && !at->reset)) {
  70. at->fan_eft = 1;
  71. at->timer_eft = 1;
  72. first = false;
  73. }
  74. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  75. at->timeout_data = timeout;
  76. at->asic_num = asic_num;
  77. at->miner_num = miner_num;
  78. at->nonce_elf = nonce_elf;
  79. at->gate_miner_elf = 1;
  80. at->asic_pll = 1;
  81. if (unlikely(gate_miner)) {
  82. at-> gate_miner = 1;
  83. at->asic_pll = 0;
  84. }
  85. buf = (uint8_t *)at;
  86. buf[5] = 0x00;
  87. buf[8] = 0x74;
  88. buf[9] = 0x01;
  89. buf[10] = 0x00;
  90. buf[11] = 0x00;
  91. if (frequency == 256) {
  92. buf[6] = 0x03;
  93. buf[7] = 0x08;
  94. } else if (frequency == 270) {
  95. buf[6] = 0x73;
  96. buf[7] = 0x08;
  97. } else if (frequency == 282) {
  98. buf[6] = 0xd3;
  99. buf[7] = 0x08;
  100. } else if (frequency == 300) {
  101. buf[6] = 0x63;
  102. buf[7] = 0x09;
  103. }
  104. return 0;
  105. }
  106. static inline void avalon_create_task(struct avalon_task *at,
  107. struct work *work)
  108. {
  109. memcpy(at->midstate, work->midstate, 32);
  110. memcpy(at->data, work->data + 64, 12);
  111. }
  112. static int avalon_send_task(int fd, const struct avalon_task *at,
  113. struct cgpu_info *avalon)
  114. {
  115. size_t ret;
  116. int full;
  117. struct timespec p;
  118. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  119. size_t nr_len;
  120. struct avalon_info *info;
  121. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  122. uint32_t nonce_range;
  123. int i;
  124. if (at->nonce_elf)
  125. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  126. else
  127. nr_len = AVALON_WRITE_SIZE;
  128. memcpy(buf, at, AVALON_WRITE_SIZE);
  129. if (at->nonce_elf) {
  130. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  131. for (i = 0; i < at->asic_num; i++) {
  132. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  133. (i * nonce_range & 0xff000000) >> 24;
  134. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  135. (i * nonce_range & 0x00ff0000) >> 16;
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  137. (i * nonce_range & 0x0000ff00) >> 8;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  139. (i * nonce_range & 0x000000ff) >> 0;
  140. }
  141. }
  142. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  143. uint8_t tt = 0;
  144. tt = (buf[0] & 0x0f) << 4;
  145. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  146. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  147. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  148. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  149. buf[0] = tt;
  150. tt = (buf[4] & 0x0f) << 4;
  151. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  152. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  153. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  154. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  155. buf[4] = tt;
  156. #endif
  157. if (likely(avalon)) {
  158. info = avalon_info[avalon->device_id];
  159. delay = nr_len * 10 * 1000000000ULL;
  160. delay = delay / info->baud;
  161. }
  162. if (at->reset)
  163. nr_len = 1;
  164. if (opt_debug) {
  165. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  166. hexdump((uint8_t *)buf, nr_len);
  167. }
  168. ret = write(fd, buf, nr_len);
  169. if (unlikely(ret != nr_len))
  170. return AVA_SEND_ERROR;
  171. p.tv_sec = 0;
  172. p.tv_nsec = (long)delay + 4000000;
  173. nanosleep(&p, NULL);
  174. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  175. full = avalon_buffer_full(fd);
  176. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  177. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  178. if (unlikely(full == AVA_BUFFER_FULL))
  179. return AVA_SEND_BUFFER_FULL;
  180. return AVA_SEND_BUFFER_EMPTY;
  181. }
  182. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  183. struct thr_info *thr, struct timeval *tv_finish)
  184. {
  185. ssize_t ret = 0;
  186. int rc = 0;
  187. int read_amount = AVALON_READ_SIZE;
  188. bool first = true;
  189. /* Read reply 1 byte at a time to get earliest tv_finish */
  190. while (true) {
  191. ret = read(fd, buf, 1);
  192. if (ret < 0)
  193. return AVA_GETS_ERROR;
  194. if (first && tv_finish != NULL)
  195. gettimeofday(tv_finish, NULL);
  196. if (ret >= read_amount)
  197. return AVA_GETS_OK;
  198. if (ret > 0) {
  199. buf += ret;
  200. read_amount -= ret;
  201. first = false;
  202. continue;
  203. }
  204. rc++;
  205. if (rc >= read_count) {
  206. if (opt_debug) {
  207. applog(LOG_WARNING,
  208. "Avalon: No data in %.2f seconds",
  209. (float)rc/(float)AVALON_TIME_FACTOR);
  210. }
  211. return AVA_GETS_TIMEOUT;
  212. }
  213. if (thr && thr->work_restart) {
  214. if (opt_debug) {
  215. applog(LOG_WARNING,
  216. "Avalon: Work restart at %.2f seconds",
  217. (float)(rc)/(float)AVALON_TIME_FACTOR);
  218. }
  219. return AVA_GETS_RESTART;
  220. }
  221. }
  222. }
  223. static int avalon_get_result(int fd, struct avalon_result *ar,
  224. struct thr_info *thr, struct timeval *tv_finish)
  225. {
  226. struct cgpu_info *avalon;
  227. struct avalon_info *info;
  228. uint8_t result[AVALON_READ_SIZE];
  229. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  230. if (likely(thr)) {
  231. avalon = thr->cgpu;
  232. info = avalon_info[avalon->device_id];
  233. read_count = info->read_count;
  234. }
  235. memset(result, 0, AVALON_READ_SIZE);
  236. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  237. if (ret == AVA_GETS_OK) {
  238. if (opt_debug) {
  239. applog(LOG_DEBUG, "Avalon: get:");
  240. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  241. }
  242. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  243. }
  244. return ret;
  245. }
  246. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  247. struct avalon_result *ar, uint32_t *nonce)
  248. {
  249. struct cgpu_info *avalon;
  250. struct avalon_info *info;
  251. int avalon_get_work_count, i;
  252. if (unlikely(!work))
  253. return -1;
  254. avalon = thr->cgpu;
  255. info = avalon_info[avalon->device_id];
  256. avalon_get_work_count = info->miner_count;
  257. for (i = 0; i < avalon_get_work_count; i++) {
  258. if (work[i] &&
  259. !memcmp(ar->data, work[i]->data + 64, 12) &&
  260. !memcmp(ar->midstate, work[i]->midstate, 32))
  261. break;
  262. }
  263. if (i == avalon_get_work_count)
  264. return -1;
  265. info->matching_work[i]++;
  266. *nonce = ar->nonce;
  267. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  268. *nonce = swab32(*nonce);
  269. #endif
  270. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  271. info->matching_work[i]);
  272. return i;
  273. }
  274. static int avalon_reset(int fd, struct avalon_result *ar)
  275. {
  276. struct avalon_task at;
  277. uint8_t *buf;
  278. int ret, i = 0;
  279. struct timespec p;
  280. avalon_init_task(&at, 1, 0,
  281. AVALON_DEFAULT_FAN_MAX_PWM,
  282. AVALON_DEFAULT_TIMEOUT,
  283. AVALON_DEFAULT_ASIC_NUM,
  284. AVALON_DEFAULT_MINER_NUM,
  285. 0, 0,
  286. AVALON_DEFAULT_FREQUENCY);
  287. ret = avalon_send_task(fd, &at, NULL);
  288. if (ret == AVA_SEND_ERROR)
  289. return 1;
  290. avalon_get_result(fd, ar, NULL, NULL);
  291. buf = (uint8_t *)ar;
  292. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  293. buf[2] == 0xAA && buf[3] == 0x55) {
  294. for (i = 4; i < 11; i++)
  295. if (buf[i] != 0)
  296. break;
  297. }
  298. if (i != 11) {
  299. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  300. " (%d: %02x %02x %02x %02x)",
  301. i, buf[0], buf[1], buf[2], buf[3]);
  302. /* FIXME: return 1; */
  303. }
  304. p.tv_sec = 0;
  305. p.tv_nsec = AVALON_RESET_PITCH;
  306. nanosleep(&p, NULL);
  307. applog(LOG_WARNING, "Avalon: Reset succeeded");
  308. return 0;
  309. }
  310. static void avalon_idle(struct cgpu_info *avalon)
  311. {
  312. int i, ret;
  313. struct avalon_task at;
  314. int fd = avalon->device_fd;
  315. struct avalon_info *info = avalon_info[avalon->device_id];
  316. int avalon_get_work_count = info->miner_count;
  317. i = 0;
  318. while (true) {
  319. avalon_init_task(&at, 0, 0, info->fan_pwm,
  320. info->timeout, info->asic_count,
  321. info->miner_count, 1, 1, info->frequency);
  322. ret = avalon_send_task(fd, &at, avalon);
  323. if (unlikely(ret == AVA_SEND_ERROR ||
  324. (ret == AVA_SEND_BUFFER_EMPTY &&
  325. (i + 1 == avalon_get_work_count * 2)))) {
  326. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  327. return;
  328. }
  329. if (i + 1 == avalon_get_work_count * 2)
  330. break;
  331. if (ret == AVA_SEND_BUFFER_FULL)
  332. break;
  333. i++;
  334. }
  335. applog(LOG_ERR, "Avalon: Goto idle mode");
  336. }
  337. static void get_options(int this_option_offset, int *baud, int *miner_count,
  338. int *asic_count, int *timeout, int *frequency)
  339. {
  340. char err_buf[BUFSIZ+1];
  341. char buf[BUFSIZ+1];
  342. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  343. size_t max;
  344. int i, tmp;
  345. if (opt_avalon_options == NULL)
  346. buf[0] = '\0';
  347. else {
  348. ptr = opt_avalon_options;
  349. for (i = 0; i < this_option_offset; i++) {
  350. comma = strchr(ptr, ',');
  351. if (comma == NULL)
  352. break;
  353. ptr = comma + 1;
  354. }
  355. comma = strchr(ptr, ',');
  356. if (comma == NULL)
  357. max = strlen(ptr);
  358. else
  359. max = comma - ptr;
  360. if (max > BUFSIZ)
  361. max = BUFSIZ;
  362. strncpy(buf, ptr, max);
  363. buf[max] = '\0';
  364. }
  365. *baud = AVALON_IO_SPEED;
  366. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  367. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  368. *timeout = AVALON_DEFAULT_TIMEOUT;
  369. *frequency = AVALON_DEFAULT_FREQUENCY;
  370. if (!(*buf))
  371. return;
  372. colon = strchr(buf, ':');
  373. if (colon)
  374. *(colon++) = '\0';
  375. tmp = atoi(buf);
  376. switch (tmp) {
  377. case 115200:
  378. *baud = 115200;
  379. break;
  380. case 57600:
  381. *baud = 57600;
  382. break;
  383. case 38400:
  384. *baud = 38400;
  385. break;
  386. case 19200:
  387. *baud = 19200;
  388. break;
  389. default:
  390. sprintf(err_buf,
  391. "Invalid avalon-options for baud (%s) "
  392. "must be 115200, 57600, 38400 or 19200", buf);
  393. quit(1, err_buf);
  394. }
  395. if (colon && *colon) {
  396. colon2 = strchr(colon, ':');
  397. if (colon2)
  398. *(colon2++) = '\0';
  399. if (*colon) {
  400. tmp = atoi(colon);
  401. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  402. *miner_count = tmp;
  403. } else {
  404. sprintf(err_buf,
  405. "Invalid avalon-options for "
  406. "miner_count (%s) must be 1 ~ %d",
  407. colon, AVALON_DEFAULT_MINER_NUM);
  408. quit(1, err_buf);
  409. }
  410. }
  411. if (colon2 && *colon2) {
  412. colon3 = strchr(colon2, ':');
  413. if (colon3)
  414. *(colon3++) = '\0';
  415. tmp = atoi(colon2);
  416. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  417. *asic_count = tmp;
  418. else {
  419. sprintf(err_buf,
  420. "Invalid avalon-options for "
  421. "asic_count (%s) must be 1 ~ %d",
  422. colon2, AVALON_DEFAULT_ASIC_NUM);
  423. quit(1, err_buf);
  424. }
  425. if (colon3 && *colon3) {
  426. colon4 = strchr(colon3, ':');
  427. if (colon4)
  428. *(colon4++) = '\0';
  429. tmp = atoi(colon3);
  430. if (tmp > 0 && tmp <= 0xff)
  431. *timeout = tmp;
  432. else {
  433. sprintf(err_buf,
  434. "Invalid avalon-options for "
  435. "timeout (%s) must be 1 ~ %d",
  436. colon3, 0xff);
  437. quit(1, err_buf);
  438. }
  439. if (colon4 && *colon4) {
  440. tmp = atoi(colon4);
  441. switch (tmp) {
  442. case 256:
  443. case 270:
  444. case 282:
  445. case 300:
  446. *frequency = tmp;
  447. break;
  448. default:
  449. sprintf(err_buf,
  450. "Invalid avalon-options for "
  451. "frequency must be 256/270/282/300");
  452. quit(1, err_buf);
  453. }
  454. }
  455. }
  456. }
  457. }
  458. }
  459. static bool avalon_detect_one(const char *devpath)
  460. {
  461. struct avalon_info *info;
  462. struct avalon_result ar;
  463. int fd, ret;
  464. int baud, miner_count, asic_count, timeout, frequency = 0;
  465. int this_option_offset = ++option_offset;
  466. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  467. &timeout, &frequency);
  468. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  469. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  470. devpath, baud, miner_count, asic_count, timeout, frequency);
  471. fd = avalon_open2(devpath, baud, true);
  472. if (unlikely(fd == -1)) {
  473. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  474. return false;
  475. }
  476. ret = avalon_reset(fd, &ar);
  477. if (ret) {
  478. ; /* FIXME: I think IT IS avalon and wait on reset;
  479. * avalon_close(fd);
  480. * return false; */
  481. }
  482. /* We have a real Avalon! */
  483. struct cgpu_info *avalon;
  484. avalon = calloc(1, sizeof(struct cgpu_info));
  485. avalon->api = &avalon_api;
  486. avalon->device_path = strdup(devpath);
  487. avalon->device_fd = fd;
  488. avalon->threads = AVALON_MINER_THREADS;
  489. add_cgpu(avalon);
  490. avalon_info = realloc(avalon_info,
  491. sizeof(struct avalon_info *) *
  492. (total_devices + 1));
  493. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  494. devpath, avalon->device_id);
  495. avalon_info[avalon->device_id] = (struct avalon_info *)
  496. malloc(sizeof(struct avalon_info));
  497. if (unlikely(!(avalon_info[avalon->device_id])))
  498. quit(1, "Failed to malloc avalon_info");
  499. info = avalon_info[avalon->device_id];
  500. memset(info, 0, sizeof(struct avalon_info));
  501. info->baud = baud;
  502. info->miner_count = miner_count;
  503. info->asic_count = asic_count;
  504. info->timeout = timeout;
  505. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  506. AVALON_TIME_FACTOR) / (float)info->miner_count;
  507. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  508. info->temp_max = 0;
  509. /* This is for check the temp/fan every 3~4s */
  510. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  511. if (info->temp_history_count <= 0)
  512. info->temp_history_count = 1;
  513. info->temp_history_index = 0;
  514. info->temp_sum = 0;
  515. info->temp_old = 0;
  516. info->frequency = frequency;
  517. /* Set asic to idle mode after detect */
  518. avalon_idle(avalon);
  519. avalon->device_fd = -1;
  520. avalon_close(fd);
  521. return true;
  522. }
  523. static inline void avalon_detect()
  524. {
  525. serial_detect(&avalon_api, avalon_detect_one);
  526. }
  527. static void avalon_init(struct cgpu_info *avalon)
  528. {
  529. struct avalon_result ar;
  530. int fd, ret;
  531. avalon->device_fd = -1;
  532. fd = avalon_open(avalon->device_path,
  533. avalon_info[avalon->device_id]->baud);
  534. if (unlikely(fd == -1)) {
  535. applog(LOG_ERR, "Avalon: Failed to open on %s",
  536. avalon->device_path);
  537. return;
  538. }
  539. ret = avalon_reset(fd, &ar);
  540. if (ret) {
  541. avalon_close(fd);
  542. return;
  543. }
  544. avalon->device_fd = fd;
  545. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  546. return;
  547. }
  548. static bool avalon_prepare(struct thr_info *thr)
  549. {
  550. struct cgpu_info *avalon = thr->cgpu;
  551. struct timeval now;
  552. avalon_init(avalon);
  553. if (avalon->device_fd == -1)
  554. return false;
  555. gettimeofday(&now, NULL);
  556. get_datestamp(avalon->init, &now);
  557. return true;
  558. }
  559. static void avalon_free_work(struct thr_info *thr, struct work **work)
  560. {
  561. struct cgpu_info *avalon;
  562. struct avalon_info *info;
  563. int i;
  564. if (unlikely(!work))
  565. return;
  566. avalon = thr->cgpu;
  567. info = avalon_info[avalon->device_id];
  568. for (i = 0; i < info->miner_count; i++)
  569. if (likely(work[i])) {
  570. free_work(work[i]);
  571. work[i] = NULL;
  572. }
  573. }
  574. static void do_avalon_close(struct thr_info *thr)
  575. {
  576. struct cgpu_info *avalon = thr->cgpu;
  577. struct avalon_info *info = avalon_info[avalon->device_id];
  578. avalon_idle(avalon);
  579. avalon_close(avalon->device_fd);
  580. avalon->device_fd = -1;
  581. info->no_matching_work = 0;
  582. avalon_free_work(thr, info->bulk0);
  583. avalon_free_work(thr, info->bulk1);
  584. avalon_free_work(thr, info->bulk2);
  585. avalon_free_work(thr, info->bulk3);
  586. }
  587. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  588. {
  589. int max;
  590. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  591. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  592. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  593. info->temp0 = ar->temp0;
  594. info->temp1 = ar->temp1;
  595. info->temp2 = ar->temp2;
  596. if (ar->temp0 & 0x80) {
  597. ar->temp0 &= 0x7f;
  598. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  599. }
  600. if (ar->temp1 & 0x80) {
  601. ar->temp1 &= 0x7f;
  602. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  603. }
  604. if (ar->temp2 & 0x80) {
  605. ar->temp2 &= 0x7f;
  606. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  607. }
  608. *temp_avg = info->temp2;
  609. max = info->temp_max;
  610. if (info->temp0 > max)
  611. max = info->temp0;
  612. if (info->temp1 > max)
  613. max = info->temp1;
  614. if (info->temp2 > max)
  615. max = info->temp2;
  616. if (max >= 100) { /* FIXME: fix the root cause on fpga controller firmware */
  617. if (opt_debug) {
  618. applog(LOG_DEBUG, "Avalon: temp_max: %d", max);
  619. hexdump((uint8_t *)ar, AVALON_READ_SIZE);
  620. }
  621. return;
  622. }
  623. info->temp_max = max;
  624. }
  625. static inline void adjust_fan(struct avalon_info *info)
  626. {
  627. int temp_new;
  628. temp_new = info->temp_sum / info->temp_history_count;
  629. if (temp_new < 35) {
  630. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  631. info->temp_old = temp_new;
  632. } else if (temp_new > 55) {
  633. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  634. info->temp_old = temp_new;
  635. } else if (abs(temp_new - info->temp_old) >= 2) {
  636. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  637. info->temp_old = temp_new;
  638. }
  639. }
  640. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  641. __maybe_unused int64_t max_nonce)
  642. {
  643. struct cgpu_info *avalon;
  644. int fd, ret, full;
  645. struct avalon_info *info;
  646. struct avalon_task at;
  647. struct avalon_result ar;
  648. int i, work_i0, work_i1, work_i2, work_i3;
  649. int avalon_get_work_count;
  650. struct timeval tv_start, tv_finish, elapsed;
  651. uint32_t nonce;
  652. int64_t hash_count;
  653. static int first_try = 0;
  654. avalon = thr->cgpu;
  655. info = avalon_info[avalon->device_id];
  656. avalon_get_work_count = info->miner_count;
  657. if (unlikely(avalon->device_fd == -1))
  658. if (!avalon_prepare(thr)) {
  659. applog(LOG_ERR, "AVA%i: Comms error(open)",
  660. avalon->device_id);
  661. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  662. /* fail the device if the reopen attempt fails */
  663. return -1;
  664. }
  665. fd = avalon->device_fd;
  666. #ifndef WIN32
  667. tcflush(fd, TCOFLUSH);
  668. #endif
  669. for (i = 0; i < avalon_get_work_count; i++) {
  670. info->bulk0[i] = info->bulk1[i];
  671. info->bulk1[i] = info->bulk2[i];
  672. info->bulk2[i] = info->bulk3[i];
  673. info->bulk3[i] = work[i];
  674. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  675. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  676. }
  677. i = 0;
  678. while (true) {
  679. avalon_init_task(&at, 0, 0, info->fan_pwm,
  680. info->timeout, info->asic_count,
  681. info->miner_count, 1, 0, info->frequency);
  682. avalon_create_task(&at, work[i]);
  683. ret = avalon_send_task(fd, &at, avalon);
  684. if (unlikely(ret == AVA_SEND_ERROR ||
  685. (ret == AVA_SEND_BUFFER_EMPTY &&
  686. (i + 1 == avalon_get_work_count) &&
  687. first_try))) {
  688. avalon_free_work(thr, info->bulk0);
  689. avalon_free_work(thr, info->bulk1);
  690. avalon_free_work(thr, info->bulk2);
  691. avalon_free_work(thr, info->bulk3);
  692. do_avalon_close(thr);
  693. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  694. avalon->device_id);
  695. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  696. first_try = 0;
  697. sleep(1);
  698. return 0; /* This should never happen */
  699. }
  700. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  701. first_try = 1;
  702. return 0xffffffff;
  703. }
  704. work[i]->blk.nonce = 0xffffffff;
  705. if (ret == AVA_SEND_BUFFER_FULL)
  706. break;
  707. i++;
  708. }
  709. if (unlikely(first_try))
  710. first_try = 0;
  711. elapsed.tv_sec = elapsed.tv_usec = 0;
  712. gettimeofday(&tv_start, NULL);
  713. hash_count = 0;
  714. while (true) {
  715. work_i0 = work_i1 = work_i2 = work_i3 = -1;
  716. full = avalon_buffer_full(fd);
  717. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  718. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  719. if (unlikely(full == AVA_BUFFER_EMPTY))
  720. break;
  721. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  722. if (unlikely(ret == AVA_GETS_ERROR)) {
  723. avalon_free_work(thr, info->bulk0);
  724. avalon_free_work(thr, info->bulk1);
  725. avalon_free_work(thr, info->bulk2);
  726. avalon_free_work(thr, info->bulk3);
  727. do_avalon_close(thr);
  728. applog(LOG_ERR,
  729. "AVA%i: Comms error(read)", avalon->device_id);
  730. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  731. return 0;
  732. }
  733. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  734. timersub(&tv_finish, &tv_start, &elapsed);
  735. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  736. elapsed.tv_sec, elapsed.tv_usec);
  737. continue;
  738. }
  739. if (unlikely(ret == AVA_GETS_RESTART)) {
  740. avalon_free_work(thr, info->bulk0);
  741. avalon_free_work(thr, info->bulk1);
  742. avalon_free_work(thr, info->bulk2);
  743. avalon_free_work(thr, info->bulk3);
  744. continue;
  745. }
  746. record_temp_fan(info, &ar, &(avalon->temp));
  747. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  748. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  749. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  750. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  751. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  752. info->no_matching_work++;
  753. if (opt_debug) {
  754. timersub(&tv_finish, &tv_start, &elapsed);
  755. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  756. " (%ld.%06lds)", info->no_matching_work,
  757. elapsed.tv_sec, elapsed.tv_usec);
  758. }
  759. continue;
  760. }
  761. if (work_i0 >= 0)
  762. submit_nonce(thr, info->bulk0[work_i0], nonce);
  763. if (work_i1 >= 0)
  764. submit_nonce(thr, info->bulk1[work_i1], nonce);
  765. if (work_i2 >= 0)
  766. submit_nonce(thr, info->bulk2[work_i2], nonce);
  767. if (work_i3 >= 0)
  768. submit_nonce(thr, info->bulk3[work_i3], nonce);
  769. hash_count += nonce;
  770. if (opt_debug) {
  771. timersub(&tv_finish, &tv_start, &elapsed);
  772. applog(LOG_DEBUG,
  773. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  774. "(%ld.%06lds)", nonce, hash_count,
  775. elapsed.tv_sec, elapsed.tv_usec);
  776. }
  777. }
  778. avalon_free_work(thr, info->bulk0);
  779. applog(LOG_WARNING,
  780. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  781. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  782. info->fan0, info->fan1, info->fan2,
  783. info->temp0, info->temp1, info->temp2, info->temp_max);
  784. info->temp_history_index++;
  785. info->temp_sum += info->temp2;
  786. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  787. info->temp_history_index, info->temp_history_count, info->temp_old);
  788. if (info->temp_history_index == info->temp_history_count) {
  789. adjust_fan(info);
  790. info->temp_history_index = 0;
  791. info->temp_sum = 0;
  792. }
  793. /*
  794. * FIXME: Each work split to 10 pieces, each piece send to a
  795. * asic(256MHs). one work can be mulit-nonce back. it is not
  796. * easy calculate correct hash on such situation. so I simplely
  797. * add each nonce to hash_count. base on Utility/m hash_count*2
  798. * give a very good result.
  799. *
  800. * Any patch will be great.
  801. */
  802. return (hash_count * 2);
  803. }
  804. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  805. {
  806. struct api_data *root = NULL;
  807. struct avalon_info *info = avalon_info[cgpu->device_id];
  808. root = api_add_int(root, "baud", &(info->baud), false);
  809. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  810. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  811. root = api_add_int(root, "read_count", &(info->read_count), false);
  812. root = api_add_int(root, "timeout", &(info->timeout), false);
  813. root = api_add_int(root, "frequency", &(info->frequency), false);
  814. root = api_add_int(root, "fan1", &(info->fan0), false);
  815. root = api_add_int(root, "fan2", &(info->fan1), false);
  816. root = api_add_int(root, "fan3", &(info->fan2), false);
  817. root = api_add_int(root, "temp1", &(info->temp0), false);
  818. root = api_add_int(root, "temp2", &(info->temp1), false);
  819. root = api_add_int(root, "temp3", &(info->temp2), false);
  820. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  821. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  822. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  823. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  824. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  825. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  826. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  827. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  828. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  829. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  830. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  831. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  832. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  833. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  834. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  835. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  836. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  837. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  838. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  839. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  840. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  841. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  842. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  843. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  844. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  845. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  846. return root;
  847. }
  848. static void avalon_shutdown(struct thr_info *thr)
  849. {
  850. do_avalon_close(thr);
  851. }
  852. struct device_api avalon_api = {
  853. .dname = "avalon",
  854. .name = "AVA",
  855. .api_detect = avalon_detect,
  856. .thread_prepare = avalon_prepare,
  857. .scanhash_queue = avalon_scanhash,
  858. .get_api_stats = avalon_api_stats,
  859. .reinit_device = avalon_init,
  860. .thread_shutdown = avalon_shutdown,
  861. };