driver-avalon.c 20 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p,
  40. uint8_t miner_num_p)
  41. {
  42. static bool first = true;
  43. uint8_t timeout;
  44. uint8_t asic_num;
  45. uint8_t miner_num;
  46. struct cgpu_info *avalon;
  47. struct avalon_info *info;
  48. if (!at)
  49. return -1;
  50. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  51. return -1;
  52. timeout = timeout_p;
  53. miner_num = miner_num_p;
  54. asic_num = asic_num_p;
  55. if (thr) {
  56. avalon = thr->cgpu;
  57. info = avalon_info[avalon->device_id];
  58. timeout = info->timeout;
  59. miner_num = info->miner_count;
  60. asic_num = info->asic_count;
  61. }
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (reset) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (first && !at->reset) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = 1;
  81. return 0;
  82. }
  83. static inline void avalon_create_task(struct avalon_task *at,
  84. struct work *work)
  85. {
  86. memcpy(at->midstate, work->midstate, 32);
  87. memcpy(at->data, work->data + 64, 12);
  88. }
  89. static int avalon_send_task(int fd, const struct avalon_task *at,
  90. struct thr_info *thr)
  91. {
  92. size_t ret;
  93. int full;
  94. struct timespec p;
  95. uint8_t *buf;
  96. size_t nr_len;
  97. struct cgpu_info *avalon;
  98. struct avalon_info *info;
  99. uint64_t delay = 32000000; /* default 32ms for B19200 */
  100. uint32_t nonce_range;
  101. int i;
  102. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  103. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  104. if (!buf)
  105. return AVA_SEND_ERROR;
  106. memcpy(buf, at, AVALON_WRITE_SIZE);
  107. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  108. for (i = 0; i < at->asic_num; i++) {
  109. buf[AVALON_WRITE_SIZE + (i * 4) + 0] = (i * nonce_range & 0xff000000) >> 24;
  110. buf[AVALON_WRITE_SIZE + (i * 4) + 1] = (i * nonce_range & 0x00ff0000) >> 16;
  111. buf[AVALON_WRITE_SIZE + (i * 4) + 2] = (i * nonce_range & 0x0000ff00) >> 8;
  112. buf[AVALON_WRITE_SIZE + (i * 4) + 3] = (i * nonce_range & 0x000000ff) >> 0;
  113. }
  114. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  115. uint8_t tt = 0;
  116. tt = (buf[0] & 0x0f) << 4;
  117. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  118. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  119. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  120. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  121. buf[0] = tt;
  122. buf[4] = rev8(buf[4]);
  123. #endif
  124. if (opt_debug) {
  125. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  126. hexdump((uint8_t *)buf, nr_len);
  127. }
  128. ret = write(fd, buf, nr_len);
  129. free(buf);
  130. if (unlikely(ret != nr_len))
  131. return AVA_SEND_ERROR;
  132. if (thr) {
  133. avalon = thr->cgpu;
  134. info = avalon_info[avalon->device_id];
  135. delay = nr_len * 10 * 1000000000ULL;
  136. delay = delay / info->baud;
  137. }
  138. p.tv_sec = 0;
  139. p.tv_nsec = (long)delay + 4000000;
  140. nanosleep(&p, NULL);
  141. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  142. full = avalon_buffer_full(fd);
  143. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  144. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  145. if (full == AVA_BUFFER_EMPTY)
  146. return AVA_SEND_BUFFER_EMPTY;
  147. return AVA_SEND_BUFFER_FULL;
  148. }
  149. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  150. struct thr_info *thr, struct timeval *tv_finish)
  151. {
  152. ssize_t ret = 0;
  153. int rc = 0;
  154. int read_amount = AVALON_READ_SIZE;
  155. bool first = true;
  156. /* Read reply 1 byte at a time to get earliest tv_finish */
  157. while (true) {
  158. ret = read(fd, buf, 1);
  159. if (ret < 0)
  160. return AVA_GETS_ERROR;
  161. if (first && tv_finish != NULL)
  162. gettimeofday(tv_finish, NULL);
  163. if (ret >= read_amount)
  164. return AVA_GETS_OK;
  165. if (ret > 0) {
  166. buf += ret;
  167. read_amount -= ret;
  168. first = false;
  169. continue;
  170. }
  171. rc++;
  172. if (rc >= read_count) {
  173. if (opt_debug) {
  174. applog(LOG_ERR,
  175. "Avalon: No data in %.2f seconds",
  176. (float)rc/(float)TIME_FACTOR);
  177. }
  178. return AVA_GETS_TIMEOUT;
  179. }
  180. if (thr && thr->work_restart) {
  181. if (opt_debug) {
  182. applog(LOG_ERR,
  183. "Avalon: Work restart at %.2f seconds",
  184. (float)(rc)/(float)TIME_FACTOR);
  185. }
  186. return AVA_GETS_RESTART;
  187. }
  188. }
  189. }
  190. static int avalon_get_result(int fd, struct avalon_result *ar,
  191. struct thr_info *thr, struct timeval *tv_finish)
  192. {
  193. struct cgpu_info *avalon;
  194. struct avalon_info *info;
  195. uint8_t result[AVALON_READ_SIZE];
  196. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  197. if (thr) {
  198. avalon = thr->cgpu;
  199. info = avalon_info[avalon->device_id];
  200. read_count = info->read_count;
  201. }
  202. memset(result, 0, AVALON_READ_SIZE);
  203. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  204. if (ret == AVA_GETS_OK) {
  205. if (opt_debug) {
  206. applog(LOG_DEBUG, "Avalon: get:");
  207. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  208. }
  209. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  210. }
  211. return ret;
  212. }
  213. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  214. struct avalon_result *ar, uint32_t *nonce)
  215. {
  216. struct cgpu_info *avalon;
  217. struct avalon_info *info;
  218. int avalon_get_work_count, i;
  219. if (!work)
  220. return -1;
  221. avalon = thr->cgpu;
  222. info = avalon_info[avalon->device_id];
  223. avalon_get_work_count = info->miner_count;
  224. for (i = 0; i < avalon_get_work_count; i++) {
  225. if (work[i] &&
  226. !memcmp(ar->data, work[i]->data + 64, 12) &&
  227. !memcmp(ar->midstate, work[i]->midstate, 32))
  228. break;
  229. }
  230. if (i == avalon_get_work_count)
  231. return -1;
  232. *nonce = ar->nonce;
  233. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  234. *nonce = swab32(*nonce);
  235. #endif
  236. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  237. return i;
  238. }
  239. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  240. uint8_t miner_num_p, struct avalon_result *ar)
  241. {
  242. struct avalon_task at;
  243. uint8_t *buf;
  244. int ret, i;
  245. struct timespec p;
  246. avalon_init_task(NULL,
  247. &at, 1, 0,
  248. AVALON_DEFAULT_FAN_PWM,
  249. timeout_p, asic_num_p, miner_num_p);
  250. ret = avalon_send_task(fd, &at, NULL);
  251. if (ret == AVA_SEND_ERROR)
  252. return 1;
  253. avalon_get_result(fd, ar, NULL, NULL);
  254. buf = (uint8_t *)ar;
  255. for (i = 0; i < 11; i++)
  256. if (buf[i] != 0)
  257. break;
  258. /* FIXME: add more avalon info base on return */
  259. if (i != 11) {
  260. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  261. return 1;
  262. }
  263. p.tv_sec = 1;
  264. p.tv_nsec = AVALON_RESET_PITCH;
  265. nanosleep(&p, NULL);
  266. applog(LOG_ERR,
  267. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  268. ar->fan0, ar->fan1, ar->fan2, ar->temp0, ar->temp1, ar->temp2);
  269. applog(LOG_ERR, "Avalon: Reset succeeded");
  270. return 0;
  271. }
  272. static void do_avalon_close(struct thr_info *thr)
  273. {
  274. struct cgpu_info *avalon = thr->cgpu;
  275. avalon_close(avalon->device_fd);
  276. avalon->device_fd = -1;
  277. /* FIXME: we should free the bulk0/1/2 */
  278. }
  279. static void set_timing_mode(struct cgpu_info *avalon, struct avalon_result *ar)
  280. {
  281. struct avalon_info *info = avalon_info[avalon->device_id];
  282. info->Hs = ((info->timeout * AVALON_HASH_TIME_FACTOR) / (double)0xffffffff);
  283. info->read_count =
  284. ((int)(info->timeout * AVALON_HASH_TIME_FACTOR * TIME_FACTOR) - 1) / info->miner_count;
  285. info->fan0 = ar->fan0;
  286. info->fan1 = ar->fan1;
  287. info->fan2 = ar->fan2;
  288. info->temp0 = ar->temp0;
  289. info->temp1 = ar->temp1;
  290. info->temp2 = ar->temp2;
  291. if (info->temp0 > info->temp_max)
  292. info->temp_max = info->temp0;
  293. if (info->temp1 > info->temp_max)
  294. info->temp_max = info->temp1;
  295. if (info->temp2 > info->temp_max)
  296. info->temp_max = info->temp2;
  297. }
  298. static void get_options(int this_option_offset, int *baud, int *miner_count,
  299. int *asic_count, int *timeout)
  300. {
  301. char err_buf[BUFSIZ+1];
  302. char buf[BUFSIZ+1];
  303. char *ptr, *comma, *colon, *colon2, *colon3;
  304. size_t max;
  305. int i, tmp;
  306. if (opt_avalon_options == NULL)
  307. buf[0] = '\0';
  308. else {
  309. ptr = opt_avalon_options;
  310. for (i = 0; i < this_option_offset; i++) {
  311. comma = strchr(ptr, ',');
  312. if (comma == NULL)
  313. break;
  314. ptr = comma + 1;
  315. }
  316. comma = strchr(ptr, ',');
  317. if (comma == NULL)
  318. max = strlen(ptr);
  319. else
  320. max = comma - ptr;
  321. if (max > BUFSIZ)
  322. max = BUFSIZ;
  323. strncpy(buf, ptr, max);
  324. buf[max] = '\0';
  325. }
  326. *baud = AVALON_IO_SPEED;
  327. *miner_count = AVALON_DEFAULT_MINER_NUM;
  328. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  329. *timeout = AVALON_DEFAULT_TIMEOUT;
  330. if (!(*buf))
  331. return;
  332. colon = strchr(buf, ':');
  333. if (colon)
  334. *(colon++) = '\0';
  335. tmp = atoi(buf);
  336. switch (tmp) {
  337. case 115200:
  338. *baud = 115200;
  339. break;
  340. case 57600:
  341. *baud = 57600;
  342. break;
  343. case 19200:
  344. *baud = 19200;
  345. break;
  346. default:
  347. sprintf(err_buf,
  348. "Invalid avalon-options for baud (%s) "
  349. "must be 115200, 57600 or 19200", buf);
  350. quit(1, err_buf);
  351. }
  352. if (colon && *colon) {
  353. colon2 = strchr(colon, ':');
  354. if (colon2)
  355. *(colon2++) = '\0';
  356. if (*colon) {
  357. tmp = atoi(colon);
  358. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  359. *miner_count = tmp;
  360. } else {
  361. sprintf(err_buf,
  362. "Invalid avalon-options for "
  363. "miner_count (%s) must be 1 ~ %d",
  364. colon, AVALON_DEFAULT_MINER_NUM);
  365. quit(1, err_buf);
  366. }
  367. }
  368. if (colon2 && *colon2) {
  369. colon3 = strchr(colon2, ':');
  370. if (colon3)
  371. *(colon3++) = '\0';
  372. tmp = atoi(colon2);
  373. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  374. *asic_count = tmp;
  375. else {
  376. sprintf(err_buf,
  377. "Invalid avalon-options for "
  378. "asic_count (%s) must be 1 ~ %d",
  379. colon2, AVALON_DEFAULT_ASIC_NUM);
  380. quit(1, err_buf);
  381. }
  382. if (colon3 && *colon3) {
  383. tmp = atoi(colon3);
  384. if (tmp > 0 && tmp <= 0xff)
  385. *timeout = tmp;
  386. else {
  387. sprintf(err_buf,
  388. "Invalid avalon-options for "
  389. "timeout (%s) must be 1 ~ %d",
  390. colon3, 0xff);
  391. quit(1, err_buf);
  392. }
  393. }
  394. }
  395. }
  396. }
  397. static bool avalon_detect_one(const char *devpath)
  398. {
  399. struct avalon_info *info;
  400. struct avalon_result ar;
  401. int fd, ret;
  402. int baud, miner_count, asic_count, timeout;
  403. int this_option_offset = ++option_offset;
  404. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  405. &timeout);
  406. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  407. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  408. devpath, baud, miner_count, asic_count, timeout);
  409. fd = avalon_open2(devpath, baud, true);
  410. if (unlikely(fd == -1)) {
  411. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  412. return false;
  413. }
  414. ret = avalon_reset(fd, timeout, asic_count, miner_count, &ar);
  415. avalon_close(fd);
  416. if (ret)
  417. return false;
  418. /* We have a real Avalon! */
  419. struct cgpu_info *avalon;
  420. avalon = calloc(1, sizeof(struct cgpu_info));
  421. avalon->api = &avalon_api;
  422. avalon->device_path = strdup(devpath);
  423. avalon->device_fd = -1;
  424. avalon->threads = AVALON_MINER_THREADS;
  425. add_cgpu(avalon);
  426. avalon_info = realloc(avalon_info,
  427. sizeof(struct avalon_info *) *
  428. (total_devices + 1));
  429. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  430. devpath, avalon->device_id);
  431. avalon_info[avalon->device_id] = (struct avalon_info *)
  432. malloc(sizeof(struct avalon_info));
  433. if (unlikely(!(avalon_info[avalon->device_id])))
  434. quit(1, "Failed to malloc avalon_info");
  435. info = avalon_info[avalon->device_id];
  436. memset(info, 0, sizeof(struct avalon_info));
  437. info->baud = baud;
  438. info->miner_count = miner_count;
  439. info->asic_count = asic_count;
  440. info->timeout = timeout;
  441. set_timing_mode(avalon, &ar);
  442. return true;
  443. }
  444. static inline void avalon_detect()
  445. {
  446. serial_detect(&avalon_api, avalon_detect_one);
  447. }
  448. static bool avalon_prepare(struct thr_info *thr)
  449. {
  450. struct avalon_result ar;
  451. struct cgpu_info *avalon = thr->cgpu;
  452. struct timeval now;
  453. int fd, ret;
  454. struct avalon_info *info = avalon_info[avalon->device_id];
  455. avalon->device_fd = -1;
  456. fd = avalon_open(avalon->device_path,
  457. avalon_info[avalon->device_id]->baud);
  458. if (unlikely(fd == -1)) {
  459. applog(LOG_ERR, "Avalon: Failed to open on %s",
  460. avalon->device_path);
  461. return false;
  462. }
  463. ret = avalon_reset(fd, info->timeout, info->asic_count,
  464. info->miner_count, &ar);
  465. if (ret)
  466. return false;
  467. avalon->device_fd = fd;
  468. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  469. gettimeofday(&now, NULL);
  470. get_datestamp(avalon->init, &now);
  471. return true;
  472. }
  473. static void avalon_free_work(struct thr_info *thr, struct work **work)
  474. {
  475. struct cgpu_info *avalon;
  476. struct avalon_info *info;
  477. int avalon_get_work_count, i;
  478. if (!work)
  479. return;
  480. avalon = thr->cgpu;
  481. info = avalon_info[avalon->device_id];
  482. avalon_get_work_count = info->miner_count;
  483. for (i = 0; i < avalon_get_work_count; i++)
  484. if (work[i]) {
  485. free_work(work[i]);
  486. work[i] = NULL;
  487. }
  488. }
  489. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  490. __maybe_unused int64_t max_nonce)
  491. {
  492. struct cgpu_info *avalon;
  493. int fd;
  494. int ret;
  495. int full;
  496. struct avalon_info *info;
  497. struct avalon_task at;
  498. struct avalon_result ar;
  499. static struct work *bulk0[AVALON_DEFAULT_MINER_NUM] = {
  500. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  501. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  502. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  503. static struct work *bulk1[AVALON_DEFAULT_MINER_NUM] = {
  504. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  505. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  506. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  507. static struct work *bulk2[AVALON_DEFAULT_MINER_NUM] = {
  508. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  509. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  510. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  511. struct work **work = NULL;
  512. int i, work_i0, work_i1, work_i2;
  513. int avalon_get_work_count;
  514. uint32_t nonce;
  515. int64_t hash_count;
  516. struct timeval tv_start, tv_finish, elapsed;
  517. int curr_hw_errors;
  518. bool was_hw_error;
  519. int64_t estimate_hashes;
  520. avalon = thr->cgpu;
  521. info = avalon_info[avalon->device_id];
  522. avalon_get_work_count = info->miner_count;
  523. if (avalon->device_fd == -1)
  524. if (!avalon_prepare(thr)) {
  525. applog(LOG_ERR, "AVA%i: Comms error",
  526. avalon->device_id);
  527. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  528. /* fail the device if the reopen attempt fails */
  529. return -1;
  530. }
  531. fd = avalon->device_fd;
  532. #ifndef WIN32
  533. tcflush(fd, TCOFLUSH);
  534. #endif
  535. work = bulk_work;
  536. for (i = 0; i < avalon_get_work_count; i++) {
  537. bulk0[i] = bulk1[i];
  538. bulk1[i] = bulk2[i];
  539. bulk2[i] = work[i];
  540. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  541. i, bulk0[i], bulk1[i], bulk2[i]);
  542. }
  543. i = 0;
  544. while (true) {
  545. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  546. avalon_create_task(&at, work[i]);
  547. ret = avalon_send_task(fd, &at, thr);
  548. if (ret == AVA_SEND_ERROR ||
  549. (ret == AVA_SEND_BUFFER_EMPTY &&
  550. (i + 1 == avalon_get_work_count))) {
  551. avalon_free_work(thr, bulk0);
  552. avalon_free_work(thr, bulk1);
  553. avalon_free_work(thr, bulk2);
  554. do_avalon_close(thr);
  555. applog(LOG_ERR, "AVA%i: Comms error",
  556. avalon->device_id);
  557. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  558. sleep(1);
  559. return 0; /* This should never happen */
  560. }
  561. work[i]->blk.nonce = 0xffffffff;
  562. if (ret == AVA_SEND_BUFFER_FULL)
  563. break;
  564. i++;
  565. }
  566. elapsed.tv_sec = elapsed.tv_usec = 0;
  567. gettimeofday(&tv_start, NULL);
  568. while(true) {
  569. full = avalon_buffer_full(fd);
  570. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  571. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  572. if (full == AVA_BUFFER_EMPTY)
  573. break;
  574. work_i0 = work_i1 = work_i2 = -1;
  575. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  576. if (ret == AVA_GETS_ERROR) {
  577. avalon_free_work(thr, bulk0);
  578. avalon_free_work(thr, bulk1);
  579. avalon_free_work(thr, bulk2);
  580. do_avalon_close(thr);
  581. applog(LOG_ERR,
  582. "AVA%i: Comms error", avalon->device_id);
  583. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  584. return 0;
  585. }
  586. /* aborted before becoming idle, get new work */
  587. if (ret == AVA_GETS_TIMEOUT) {
  588. timersub(&tv_finish, &tv_start, &elapsed);
  589. estimate_hashes = ((double)(elapsed.tv_sec) +
  590. ((double)(elapsed.tv_usec)) /
  591. ((double)1000000)) / info->Hs;
  592. /* If Serial-USB delay allowed the full nonce range to
  593. * complete it can't have done more than a full nonce
  594. */
  595. if (unlikely(estimate_hashes > 0xffffffff))
  596. estimate_hashes = 0xffffffff;
  597. applog(LOG_DEBUG,
  598. "Avalon: no nonce = 0x%08llx hashes "
  599. "(%ld.%06lds)",
  600. estimate_hashes, elapsed.tv_sec,
  601. elapsed.tv_usec);
  602. continue;
  603. }
  604. if (ret == AVA_GETS_RESTART) {
  605. avalon_free_work(thr, bulk0);
  606. avalon_free_work(thr, bulk1);
  607. avalon_free_work(thr, bulk2);
  608. continue;
  609. }
  610. avalon->temp = (ar.temp0 + ar.temp1 + ar.temp2) / 3;
  611. info->fan0 = ar.fan0;
  612. info->fan1 = ar.fan1;
  613. info->fan2 = ar.fan2;
  614. info->temp0 = ar.temp0;
  615. info->temp1 = ar.temp1;
  616. info->temp2 = ar.temp2;
  617. if (info->temp0 > info->temp_max)
  618. info->temp_max = info->temp0;
  619. if (info->temp1 > info->temp_max)
  620. info->temp_max = info->temp1;
  621. if (info->temp2 > info->temp_max)
  622. info->temp_max = info->temp2;
  623. work_i0 = avalon_decode_nonce(thr, bulk0, &ar, &nonce);
  624. work_i1 = avalon_decode_nonce(thr, bulk1, &ar, &nonce);
  625. work_i2 = avalon_decode_nonce(thr, bulk2, &ar, &nonce);
  626. curr_hw_errors = avalon->hw_errors;
  627. if (work_i0 >= 0)
  628. submit_nonce(thr, bulk0[work_i0], nonce);
  629. if (work_i1 >= 0)
  630. submit_nonce(thr, bulk1[work_i1], nonce);
  631. if (work_i2 >= 0)
  632. submit_nonce(thr, bulk2[work_i2], nonce);
  633. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  634. /* Force a USB close/reopen on any hw error */
  635. if (was_hw_error)
  636. do_avalon_close(thr);
  637. hash_count = nonce;
  638. hash_count++;
  639. hash_count *= info->asic_count;
  640. }
  641. avalon_free_work(thr, bulk0);
  642. if (opt_debug) {
  643. timersub(&tv_finish, &tv_start, &elapsed);
  644. applog(LOG_DEBUG,
  645. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  646. "(%ld.%06lds)",
  647. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  648. }
  649. applog(LOG_ERR,
  650. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  651. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  652. return hash_count;
  653. }
  654. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  655. {
  656. struct api_data *root = NULL;
  657. struct avalon_info *info = avalon_info[cgpu->device_id];
  658. root = api_add_int(root, "read_count", &(info->read_count), false);
  659. root = api_add_int(root, "baud", &(info->baud), false);
  660. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  661. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  662. root = api_add_int(root, "fan1", &(info->fan0), false);
  663. root = api_add_int(root, "fan2", &(info->fan1), false);
  664. root = api_add_int(root, "fan3", &(info->fan2), false);
  665. root = api_add_int(root, "temp1", &(info->temp0), false);
  666. root = api_add_int(root, "temp2", &(info->temp1), false);
  667. root = api_add_int(root, "temp3", &(info->temp2), false);
  668. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  669. return root;
  670. }
  671. static void avalon_shutdown(struct thr_info *thr)
  672. {
  673. do_avalon_close(thr);
  674. }
  675. struct device_api avalon_api = {
  676. .dname = "avalon",
  677. .name = "AVA",
  678. .api_detect = avalon_detect,
  679. .thread_prepare = avalon_prepare,
  680. .scanhash_queue = avalon_scanhash,
  681. .get_api_stats = avalon_api_stats,
  682. .thread_shutdown = avalon_shutdown,
  683. };