driver-bitmain.c 65 KB

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  1. /*
  2. * Copyright 2012-2014 Lingchao Xu
  3. * Copyright 2015 Luke Dashjr
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <math.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <sys/select.h>
  21. #include <termios.h>
  22. #include <sys/stat.h>
  23. #include <fcntl.h>
  24. #ifndef O_CLOEXEC
  25. #define O_CLOEXEC 0
  26. #endif
  27. #else
  28. #include "compat.h"
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include <curl/curl.h>
  33. #include <uthash.h>
  34. #include "deviceapi.h"
  35. #include "miner.h"
  36. #include "driver-bitmain.h"
  37. #include "lowl-vcom.h"
  38. #include "util.h"
  39. const bool opt_bitmain_hwerror = true;
  40. const unsigned bitmain_poll_interval_us = 10000;
  41. BFG_REGISTER_DRIVER(bitmain_drv)
  42. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[];
  43. #define htole8(x) (x)
  44. #define BITMAIN_USING_CURL -2
  45. static
  46. struct cgpu_info *btm_alloc_cgpu(struct device_drv *drv, int threads)
  47. {
  48. struct cgpu_info *cgpu = calloc(1, sizeof(*cgpu));
  49. if (unlikely(!cgpu))
  50. quit(1, "Failed to calloc cgpu for %s in usb_alloc_cgpu", drv->dname);
  51. cgpu->drv = drv;
  52. cgpu->deven = DEV_ENABLED;
  53. cgpu->threads = threads;
  54. cgpu->device_fd = -1;
  55. struct bitmain_info *info = malloc(sizeof(*info));
  56. if (unlikely(!info))
  57. quit(1, "Failed to calloc bitmain_info data");
  58. cgpu->device_data = info;
  59. *info = (struct bitmain_info){
  60. .baud = BITMAIN_IO_SPEED,
  61. .chain_num = BITMAIN_DEFAULT_CHAIN_NUM,
  62. .asic_num = BITMAIN_DEFAULT_ASIC_NUM,
  63. .timeout = BITMAIN_DEFAULT_TIMEOUT,
  64. .frequency = BITMAIN_DEFAULT_FREQUENCY,
  65. .voltage[0] = BITMAIN_DEFAULT_VOLTAGE0,
  66. .voltage[1] = BITMAIN_DEFAULT_VOLTAGE1,
  67. .diff = 255,
  68. .lowest_goal_diff = 255,
  69. .work_restart = true,
  70. };
  71. sprintf(info->frequency_t, "%d", BITMAIN_DEFAULT_FREQUENCY),
  72. strcpy(info->voltage_t, BITMAIN_DEFAULT_VOLTAGE_T);
  73. return cgpu;
  74. }
  75. static curl_socket_t bitmain_grab_socket_opensocket_cb(void *clientp, __maybe_unused curlsocktype purpose, struct curl_sockaddr *addr)
  76. {
  77. struct bitmain_info * const info = clientp;
  78. curl_socket_t sck = bfg_socket(addr->family, addr->socktype, addr->protocol);
  79. info->curl_sock = sck;
  80. return sck;
  81. }
  82. static
  83. bool btm_init(struct cgpu_info *cgpu, const char * devpath)
  84. {
  85. applog(LOG_DEBUG, "btm_init cgpu->device_fd=%d", cgpu->device_fd);
  86. int fd = -1;
  87. if(cgpu->device_fd >= 0) {
  88. return false;
  89. }
  90. struct bitmain_info *info = cgpu->device_data;
  91. if (!strncmp(devpath, "ip:", 3)) {
  92. CURL *curl = curl_easy_init();
  93. if (!curl)
  94. applogr(false, LOG_ERR, "%s: curl_easy_init failed", cgpu->drv->dname);
  95. // CURLINFO_LASTSOCKET is broken on Win64 (which has a wider SOCKET type than curl_easy_getinfo returns), so we use this hack for now
  96. info->curl_sock = -1;
  97. curl_easy_setopt(curl, CURLOPT_OPENSOCKETFUNCTION, bitmain_grab_socket_opensocket_cb);
  98. curl_easy_setopt(curl, CURLOPT_OPENSOCKETDATA, info);
  99. curl_easy_setopt(curl, CURLOPT_FRESH_CONNECT, 1);
  100. curl_easy_setopt(curl, CURLOPT_CONNECTTIMEOUT, 5);
  101. curl_easy_setopt(curl, CURLOPT_NOSIGNAL, 1);
  102. curl_easy_setopt(curl, CURLOPT_TCP_NODELAY, 1);
  103. curl_easy_setopt(curl, CURLOPT_CONNECT_ONLY, 1);
  104. curl_easy_setopt(curl, CURLOPT_URL, &devpath[3]);
  105. if (curl_easy_perform(curl)) {
  106. curl_easy_cleanup(curl);
  107. applogr(false, LOG_ERR, "%s: curl_easy_perform failed for %s", cgpu->drv->dname, &devpath[3]);
  108. }
  109. cgpu->device_path = strdup(devpath);
  110. cgpu->device_fd = BITMAIN_USING_CURL;
  111. info->device_curl = curl;
  112. return true;
  113. }
  114. fd = serial_open(devpath, info->baud, 1, true);
  115. if(fd == -1) {
  116. applog(LOG_DEBUG, "%s open %s error %d",
  117. cgpu->drv->dname, devpath, errno);
  118. return false;
  119. }
  120. cgpu->device_path = strdup(devpath);
  121. cgpu->device_fd = fd;
  122. applog(LOG_DEBUG, "btm_init open device fd = %d", cgpu->device_fd);
  123. return true;
  124. }
  125. static
  126. void btm_uninit(struct cgpu_info *cgpu)
  127. {
  128. struct bitmain_info * const info = cgpu->device_data;
  129. applog(LOG_DEBUG, "BTM uninit %s%i", cgpu->drv->name, cgpu->device_fd);
  130. // May have happened already during a failed initialisation
  131. // if release_cgpu() was called due to a USB NODEV(err)
  132. if (cgpu->device_fd >= 0) {
  133. serial_close(cgpu->device_fd);
  134. cgpu->device_fd = -1;
  135. }
  136. if (info->device_curl) {
  137. curl_easy_cleanup(info->device_curl);
  138. info->device_curl = NULL;
  139. }
  140. if(cgpu->device_path) {
  141. free((char*)cgpu->device_path);
  142. cgpu->device_path = NULL;
  143. }
  144. }
  145. bool bitmain_curl_all(const bool is_recv, const int fd, CURL * const curl, void *p, size_t remsz)
  146. {
  147. CURLcode (* const func)(CURL *, void *, size_t, size_t *) = is_recv ? (void*)curl_easy_recv : (void*)curl_easy_send;
  148. CURLcode r;
  149. size_t sz;
  150. while (remsz) {
  151. fd_set otherfds, thisfds;
  152. FD_ZERO(&otherfds);
  153. FD_ZERO(&thisfds);
  154. FD_SET(fd, &thisfds);
  155. select(fd + 1, is_recv ? &thisfds : &otherfds, is_recv ? &otherfds : &thisfds, &thisfds, NULL);
  156. r = func(curl, p, remsz, &sz);
  157. switch (r) {
  158. case CURLE_OK:
  159. remsz -= sz;
  160. p += sz;
  161. break;
  162. case CURLE_AGAIN:
  163. break;
  164. default:
  165. return false;
  166. }
  167. }
  168. return true;
  169. }
  170. static
  171. int btm_read(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  172. {
  173. int err = 0;
  174. //applog(LOG_DEBUG, "btm_read ----- %d -----", bufsize);
  175. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  176. struct bitmain_info * const info = cgpu->device_data;
  177. uint8_t headbuf[5];
  178. headbuf[0] = 0;
  179. pk_u32be(headbuf, 1, bufsize);
  180. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, headbuf, sizeof(headbuf)))
  181. return -1;
  182. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, headbuf, 4))
  183. return -1;
  184. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  185. return -1;
  186. size_t sz = upk_u32be(headbuf, 0);
  187. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, buf, sz))
  188. return -1;
  189. return sz;
  190. }
  191. err = read(cgpu->device_fd, buf, bufsize);
  192. return err;
  193. }
  194. static
  195. int btm_write(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  196. {
  197. int err = 0;
  198. //applog(LOG_DEBUG, "btm_write ----- %d -----", bufsize);
  199. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  200. struct bitmain_info * const info = cgpu->device_data;
  201. uint8_t headbuf[5];
  202. headbuf[0] = 1;
  203. pk_u32be(headbuf, 1, bufsize);
  204. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, headbuf, sizeof(headbuf)))
  205. return -1;
  206. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, buf, bufsize))
  207. return -1;
  208. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, headbuf, 4))
  209. return -1;
  210. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  211. return -1;
  212. return upk_u32be(headbuf, 0);
  213. }
  214. err = write(cgpu->device_fd, buf, bufsize);
  215. return err;
  216. }
  217. #ifdef WIN32
  218. #define BITMAIN_TEST
  219. #endif
  220. #define BITMAIN_TEST_PRINT_WORK 0
  221. #ifdef BITMAIN_TEST
  222. #define BITMAIN_TEST_NUM 19
  223. #define BITMAIN_TEST_USENUM 1
  224. int g_test_index = 0;
  225. const char btm_work_test_data[BITMAIN_TEST_NUM][256] = {
  226. "00000002ddc1ce5579dbec17f17fbb8f31ae218a814b2a0c1900f0d90000000100000000b58aa6ca86546b07a5a46698f736c7ca9c0eedc756d8f28ac33c20cc24d792675276f879190afc85b6888022000000800000000000000000000000000000000000000000000000000000000000000000",
  227. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000eb2d45233c5b02de50ddcb9049ba16040e0ba00e9750a474eec75891571d925b52dfda4a190266667145b02f000000800000000000000000000000000000000000000000000000000000000000000000",
  228. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000090c7d3743e0b0562e4f56d3dd35cece3c5e8275d0abb21bf7e503cb72bd7ed3b52dfda4a190266667bbb58d7000000800000000000000000000000000000000000000000000000000000000000000000",
  229. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000006e0561da06022bfbb42c5ecd74a46bfd91934f201b777e9155cc6c3674724ec652dfda4a19026666a0cd827b000000800000000000000000000000000000000000000000000000000000000000000000",
  230. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000000312f42ce4964cc23f2d8c039f106f25ddd58e10a1faed21b3bba4b0e621807b52dfda4a1902666629c9497d000000800000000000000000000000000000000000000000000000000000000000000000",
  231. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000033093a6540dbe8f7f3d19e3d2af05585ac58dafad890fa9a942e977334a23d6e52dfda4a190266665ae95079000000800000000000000000000000000000000000000000000000000000000000000000",
  232. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000bd7893057d06e69705bddf9a89c7bac6b40c5b32f15e2295fc8c5edf491ea24952dfda4a190266664b89b4d3000000800000000000000000000000000000000000000000000000000000000000000000",
  233. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000075e66f533e53837d14236a793ee4e493985642bc39e016b9e63adf14a584a2aa52dfda4a19026666ab5d638d000000800000000000000000000000000000000000000000000000000000000000000000",
  234. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d936f90c5db5f0fe1d017344443854fbf9e40a07a9b7e74fedc8661c23162bff52dfda4a19026666338e79cb000000800000000000000000000000000000000000000000000000000000000000000000",
  235. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d2c1a7d279a4355b017bc0a4b0a9425707786729f21ee18add3fda4252a31a4152dfda4a190266669bc90806000000800000000000000000000000000000000000000000000000000000000000000000",
  236. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000ad36d19f33d04ca779942843890bc3b083cec83a4b60b6c45cf7d21fc187746552dfda4a1902666675d81ab7000000800000000000000000000000000000000000000000000000000000000000000000",
  237. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000093b809cf82b76082eacb55bc35b79f31882ed0976fd102ef54783cd24341319b52dfda4a1902666642ab4e42000000800000000000000000000000000000000000000000000000000000000000000000",
  238. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000007411ff315430a7bbf41de8a685d457e82d5177c05640d6a4436a40f39e99667852dfda4a190266662affa4b5000000800000000000000000000000000000000000000000000000000000000000000000",
  239. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000001ad0db5b9e1e2b57c8d3654c160f5a51067521eab7e340a270639d97f00a3fa252dfda4a1902666601a47bb6000000800000000000000000000000000000000000000000000000000000000000000000",
  240. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000022e055c442c46bbe16df68603a26891f6e4cf85b90102b39fd7cadb602b4e34552dfda4a1902666695d33cea000000800000000000000000000000000000000000000000000000000000000000000000",
  241. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000009c8baf5a8a1e16de2d6ae949d5fec3ed751f10dcd4c99810f2ce08040fb9e31d52dfda4a19026666fe78849d000000800000000000000000000000000000000000000000000000000000000000000000",
  242. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000e5655532b414887f35eb4652bc7b11ebac12891f65bc08cbe0ce5b277b9e795152dfda4a19026666fcc0d1d1000000800000000000000000000000000000000000000000000000000000000000000000",
  243. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000f272c5508704e2b62dd1c30ea970372c40bf00f9203f9bf69d456b4a7fbfffe352dfda4a19026666c03d4399000000800000000000000000000000000000000000000000000000000000000000000000",
  244. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000fca3b4531ba627ad9b0e23cdd84c888952c23810df196e9c6db0bcecba6a830952dfda4a19026666c14009cb000000800000000000000000000000000000000000000000000000000000000000000000"
  245. };
  246. const char btm_work_test_midstate[BITMAIN_TEST_NUM][256] = {
  247. "2d8738e7f5bcf76dcb8316fec772e20e240cd58c88d47f2d3f5a6a9547ed0a35",
  248. "d31b6ce09c0bfc2af6f3fe3a03475ebefa5aa191fa70a327a354b2c22f9692f1",
  249. "84a8c8224b80d36caeb42eff2a100f634e1ff873e83fd02ef1306a34abef9dbe",
  250. "059882159439b9b32968c79a93c5521e769dbea9d840f56c2a17b9ad87e530b8",
  251. "17fa435d05012574f8f1da26994cc87b6cb9660b5e82072dc6a0881cec150a0d",
  252. "92a28cc5ec4ba6a2688471dfe2032b5fe97c805ca286c503e447d6749796c6af",
  253. "1677a03516d6e9509ac37e273d2482da9af6e077abe8392cdca6a30e916a7ae9",
  254. "50bbe09f1b8ac18c97aeb745d5d2c3b5d669b6ac7803e646f65ac7b763a392d1",
  255. "e46a0022ebdc303a7fb1a0ebfa82b523946c312e745e5b8a116b17ae6b4ce981",
  256. "8f2f61e7f5b4d76d854e6d266acfff4d40347548216838ccc4ef3b9e43d3c9ea",
  257. "0a450588ae99f75d676a08d0326e1ea874a3497f696722c78a80c7b6ee961ea6",
  258. "3c4c0fc2cf040b806c51b46de9ec0dcc678a7cc5cf3eff11c6c03de3bc7818cc",
  259. "f6c7c785ab5daddb8f98e5f854f2cb41879fcaf47289eb2b4196fefc1b28316f",
  260. "005312351ccb0d0794779f5023e4335b5cad221accf0dfa3da7b881266fa9f5a",
  261. "7b26d189c6bba7add54143179aadbba7ccaeff6887bd8d5bec9597d5716126e6",
  262. "a4718f4c801e7ddf913a9474eb71774993525684ffea1915f767ab16e05e6889",
  263. "6b6226a8c18919d0e55684638d33a6892a00d22492cc2f5906ca7a4ac21c74a7",
  264. "383114dccd1cb824b869158aa2984d157fcb02f46234ceca65943e919329e697",
  265. "d4d478df3016852b27cb1ae9e1e98d98617f8d0943bf9dc1217f47f817236222"
  266. };
  267. #endif
  268. bool opt_bitmain_checkall = false;
  269. bool opt_bitmain_nobeeper = false;
  270. bool opt_bitmain_notempoverctrl = false;
  271. bool opt_bitmain_homemode = false;
  272. bool opt_bitmain_auto;
  273. // --------------------------------------------------------------
  274. // CRC16 check table
  275. // --------------------------------------------------------------
  276. static
  277. const uint8_t chCRCHTalbe[] = // CRC high byte table
  278. {
  279. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  280. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  281. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  282. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  283. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  284. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  285. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  286. 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  287. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  288. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  289. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  290. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  291. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  292. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  293. 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  294. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  295. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  296. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  297. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  298. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  299. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  300. 0x00, 0xC1, 0x81, 0x40
  301. };
  302. static
  303. const uint8_t chCRCLTalbe[] = // CRC low byte table
  304. {
  305. 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
  306. 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
  307. 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
  308. 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
  309. 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
  310. 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
  311. 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
  312. 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
  313. 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
  314. 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
  315. 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
  316. 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
  317. 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
  318. 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
  319. 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
  320. 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
  321. 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
  322. 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
  323. 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
  324. 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
  325. 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
  326. 0x41, 0x81, 0x80, 0x40
  327. };
  328. static uint16_t CRC16(const uint8_t* p_data, uint16_t w_len)
  329. {
  330. uint8_t chCRCHi = 0xFF; // CRC high byte initialize
  331. uint8_t chCRCLo = 0xFF; // CRC low byte initialize
  332. uint16_t wIndex = 0; // CRC cycling index
  333. while (w_len--) {
  334. wIndex = chCRCLo ^ *p_data++;
  335. chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
  336. chCRCHi = chCRCLTalbe[wIndex];
  337. }
  338. return ((chCRCHi << 8) | chCRCLo);
  339. }
  340. static uint32_t num2bit(int num) {
  341. return 1L << (31 - num);
  342. }
  343. static int bitmain_set_txconfig(struct bitmain_txconfig_token *bm,
  344. uint8_t reset, uint8_t fan_eft, uint8_t timeout_eft, uint8_t frequency_eft,
  345. uint8_t voltage_eft, uint8_t chain_check_time_eft, uint8_t chip_config_eft, uint8_t hw_error_eft,
  346. uint8_t beeper_ctrl, uint8_t temp_over_ctrl,uint8_t fan_home_mode,
  347. uint8_t chain_num, uint8_t asic_num, uint8_t fan_pwm_data, uint8_t timeout_data,
  348. uint16_t frequency, uint8_t * voltage, uint8_t chain_check_time,
  349. uint8_t chip_address, uint8_t reg_address, uint8_t * reg_data)
  350. {
  351. uint16_t crc = 0;
  352. int datalen = 0;
  353. uint8_t version = 0;
  354. uint8_t * sendbuf = (uint8_t *)bm;
  355. if (unlikely(!bm)) {
  356. applog(LOG_WARNING, "bitmain_set_txconfig bitmain_txconfig_token is null");
  357. return -1;
  358. }
  359. if (unlikely(timeout_data <= 0 || asic_num <= 0 || chain_num <= 0)) {
  360. applog(LOG_WARNING, "bitmain_set_txconfig parameter invalid timeout_data(%d) asic_num(%d) chain_num(%d)",
  361. timeout_data, asic_num, chain_num);
  362. return -1;
  363. }
  364. datalen = sizeof(struct bitmain_txconfig_token);
  365. memset(bm, 0, datalen);
  366. bm->token_type = BITMAIN_TOKEN_TYPE_TXCONFIG;
  367. bm->version = version;
  368. bm->length = datalen-4;
  369. bm->length = htole16(bm->length);
  370. bm->reset = reset;
  371. bm->fan_eft = fan_eft;
  372. bm->timeout_eft = timeout_eft;
  373. bm->frequency_eft = frequency_eft;
  374. bm->voltage_eft = voltage_eft;
  375. bm->chain_check_time_eft = chain_check_time_eft;
  376. bm->chip_config_eft = chip_config_eft;
  377. bm->hw_error_eft = hw_error_eft;
  378. bm->beeper_ctrl = beeper_ctrl;
  379. bm->temp_over_ctrl = temp_over_ctrl;
  380. bm->fan_home_mode = fan_home_mode;
  381. sendbuf[4] = htole8(sendbuf[4]);
  382. sendbuf[5] = htole8(sendbuf[5]);
  383. bm->chain_num = chain_num;
  384. bm->asic_num = asic_num;
  385. bm->fan_pwm_data = fan_pwm_data;
  386. bm->timeout_data = timeout_data;
  387. bm->frequency = htole16(frequency);
  388. memcpy(bm->voltage, voltage, 2);
  389. bm->chain_check_time = chain_check_time;
  390. memcpy(bm->reg_data, reg_data, 4);
  391. bm->chip_address = chip_address;
  392. bm->reg_address = reg_address;
  393. crc = CRC16((uint8_t *)bm, datalen-2);
  394. bm->crc = htole16(crc);
  395. applog(LOG_ERR, "BTM TxConfigToken:v(%d) reset(%d) fan_e(%d) tout_e(%d) fq_e(%d) vt_e(%d) chainc_e(%d) chipc_e(%d) hw_e(%d) b_c(%d) t_c(%d) f_m(%d) mnum(%d) anum(%d) fanpwmdata(%d) toutdata(%d) freq(%d) volt(%02x%02x) chainctime(%d) regdata(%02x%02x%02x%02x) chipaddr(%02x) regaddr(%02x) crc(%04x)",
  396. version, reset, fan_eft, timeout_eft, frequency_eft, voltage_eft,
  397. chain_check_time_eft, chip_config_eft, hw_error_eft, beeper_ctrl, temp_over_ctrl,fan_home_mode,chain_num, asic_num,
  398. fan_pwm_data, timeout_data, frequency, voltage[0], voltage[1],
  399. chain_check_time, reg_data[0], reg_data[1], reg_data[2], reg_data[3], chip_address, reg_address, crc);
  400. return datalen;
  401. }
  402. static int bitmain_set_rxstatus(struct bitmain_rxstatus_token *bm,
  403. uint8_t chip_status_eft, uint8_t detect_get, uint8_t chip_address, uint8_t reg_address)
  404. {
  405. uint16_t crc = 0;
  406. uint8_t version = 0;
  407. int datalen = 0;
  408. uint8_t * sendbuf = (uint8_t *)bm;
  409. if (unlikely(!bm)) {
  410. applog(LOG_WARNING, "bitmain_set_rxstatus bitmain_rxstatus_token is null");
  411. return -1;
  412. }
  413. datalen = sizeof(struct bitmain_rxstatus_token);
  414. memset(bm, 0, datalen);
  415. bm->token_type = BITMAIN_TOKEN_TYPE_RXSTATUS;
  416. bm->version = version;
  417. bm->length = datalen-4;
  418. bm->length = htole16(bm->length);
  419. bm->chip_status_eft = chip_status_eft;
  420. bm->detect_get = detect_get;
  421. sendbuf[4] = htole8(sendbuf[4]);
  422. bm->chip_address = chip_address;
  423. bm->reg_address = reg_address;
  424. crc = CRC16((uint8_t *)bm, datalen-2);
  425. bm->crc = htole16(crc);
  426. applog(LOG_ERR, "BitMain RxStatus Token: v(%d) chip_status_eft(%d) detect_get(%d) chip_address(%02x) reg_address(%02x) crc(%04x)",
  427. version, chip_status_eft, detect_get, chip_address, reg_address, crc);
  428. return datalen;
  429. }
  430. static int bitmain_parse_rxstatus(const uint8_t * data, int datalen, struct bitmain_rxstatus_data *bm)
  431. {
  432. uint16_t crc = 0;
  433. uint8_t version = 0;
  434. int i = 0, j = 0;
  435. int asic_num = 0;
  436. int dataindex = 0;
  437. uint8_t tmp = 0x01;
  438. if (unlikely(!bm)) {
  439. applog(LOG_WARNING, "bitmain_parse_rxstatus bitmain_rxstatus_data is null");
  440. return -1;
  441. }
  442. if (unlikely(!data || datalen <= 0)) {
  443. applog(LOG_WARNING, "bitmain_parse_rxstatus parameter invalid data is null or datalen(%d) error", datalen);
  444. return -1;
  445. }
  446. memset(bm, 0, sizeof(struct bitmain_rxstatus_data));
  447. memcpy(bm, data, 28);
  448. if (bm->data_type != BITMAIN_DATA_TYPE_RXSTATUS) {
  449. applog(LOG_ERR, "bitmain_parse_rxstatus datatype(%02x) error", bm->data_type);
  450. return -1;
  451. }
  452. if (bm->version != version) {
  453. applog(LOG_ERR, "bitmain_parse_rxstatus version(%02x) error", bm->version);
  454. return -1;
  455. }
  456. bm->length = htole16(bm->length);
  457. if (bm->length+4 != datalen) {
  458. applog(LOG_ERR, "bitmain_parse_rxstatus length(%d) datalen(%d) error", bm->length, datalen);
  459. return -1;
  460. }
  461. crc = CRC16(data, datalen-2);
  462. memcpy(&(bm->crc), data+datalen-2, 2);
  463. bm->crc = htole16(bm->crc);
  464. if(crc != bm->crc) {
  465. applog(LOG_ERR, "bitmain_parse_rxstatus check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  466. return -1;
  467. }
  468. bm->fifo_space = htole16(bm->fifo_space);
  469. bm->fan_exist = htole16(bm->fan_exist);
  470. bm->temp_exist = htole32(bm->temp_exist);
  471. bm->nonce_error = htole32(bm->nonce_error);
  472. if(bm->chain_num > BITMAIN_MAX_CHAIN_NUM) {
  473. applog(LOG_ERR, "bitmain_parse_rxstatus chain_num=%d error", bm->chain_num);
  474. return -1;
  475. }
  476. dataindex = 28;
  477. if(bm->chain_num > 0) {
  478. memcpy(bm->chain_asic_num, data+datalen-2-bm->chain_num-bm->temp_num-bm->fan_num, bm->chain_num);
  479. }
  480. for(i = 0; i < bm->chain_num; i++) {
  481. asic_num = bm->chain_asic_num[i];
  482. if(asic_num <= 0) {
  483. asic_num = 1;
  484. } else {
  485. if(asic_num % 32 == 0) {
  486. asic_num = asic_num / 32;
  487. } else {
  488. asic_num = asic_num / 32 + 1;
  489. }
  490. }
  491. memcpy((uint8_t *)bm->chain_asic_exist+i*32, data+dataindex, asic_num*4);
  492. dataindex += asic_num*4;
  493. }
  494. for(i = 0; i < bm->chain_num; i++) {
  495. asic_num = bm->chain_asic_num[i];
  496. if(asic_num <= 0) {
  497. asic_num = 1;
  498. } else {
  499. if(asic_num % 32 == 0) {
  500. asic_num = asic_num / 32;
  501. } else {
  502. asic_num = asic_num / 32 + 1;
  503. }
  504. }
  505. memcpy((uint8_t *)bm->chain_asic_status+i*32, data+dataindex, asic_num*4);
  506. dataindex += asic_num*4;
  507. }
  508. dataindex += bm->chain_num;
  509. if(dataindex + bm->temp_num + bm->fan_num + 2 != datalen) {
  510. applog(LOG_ERR, "bitmain_parse_rxstatus dataindex(%d) chain_num(%d) temp_num(%d) fan_num(%d) not match datalen(%d)",
  511. dataindex, bm->chain_num, bm->temp_num, bm->fan_num, datalen);
  512. return -1;
  513. }
  514. for(i = 0; i < bm->chain_num; i++) {
  515. //bm->chain_asic_status[i] = swab32(bm->chain_asic_status[i]);
  516. for(j = 0; j < 8; j++) {
  517. bm->chain_asic_exist[i*8+j] = htole32(bm->chain_asic_exist[i*8+j]);
  518. bm->chain_asic_status[i*8+j] = htole32(bm->chain_asic_status[i*8+j]);
  519. }
  520. }
  521. if(bm->temp_num > 0) {
  522. memcpy(bm->temp, data+dataindex, bm->temp_num);
  523. dataindex += bm->temp_num;
  524. }
  525. if(bm->fan_num > 0) {
  526. memcpy(bm->fan, data+dataindex, bm->fan_num);
  527. dataindex += bm->fan_num;
  528. }
  529. if(!opt_bitmain_checkall){
  530. if(tmp != htole8(tmp)){
  531. applog(LOG_ERR, "BitMain RxStatus byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  532. memcpy(&tmp,data+4,1);
  533. bm->chip_value_eft = tmp >>7;
  534. bm->get_blk_num = tmp >> 4;
  535. bm->reserved1 = ((tmp << 4) & 0xff) >> 5;
  536. }
  537. found_blocks = bm->get_blk_num;
  538. applog(LOG_ERR, "BitMain RxStatus tmp :0x%02x byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",tmp,*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  539. }
  540. applog(LOG_DEBUG, "BitMain RxStatusData: chipv_e(%d) chainnum(%d) fifos(%d) v1(%d) v2(%d) v3(%d) v4(%d) fann(%d) tempn(%d) fanet(%04x) tempet(%08x) ne(%d) regvalue(%d) crc(%04x)",
  541. bm->chip_value_eft, bm->chain_num, bm->fifo_space, bm->hw_version[0], bm->hw_version[1], bm->hw_version[2], bm->hw_version[3], bm->fan_num, bm->temp_num, bm->fan_exist, bm->temp_exist, bm->nonce_error, bm->reg_value, bm->crc);
  542. applog(LOG_DEBUG, "BitMain RxStatus Data chain info:");
  543. for(i = 0; i < bm->chain_num; i++) {
  544. applog(LOG_DEBUG, "BitMain RxStatus Data chain(%d) asic num=%d asic_exist=%08x asic_status=%08x", i+1, bm->chain_asic_num[i], bm->chain_asic_exist[i*8], bm->chain_asic_status[i*8]);
  545. }
  546. applog(LOG_DEBUG, "BitMain RxStatus Data temp info:");
  547. for(i = 0; i < bm->temp_num; i++) {
  548. applog(LOG_DEBUG, "BitMain RxStatus Data temp(%d) temp=%d", i+1, bm->temp[i]);
  549. }
  550. applog(LOG_DEBUG, "BitMain RxStatus Data fan info:");
  551. for(i = 0; i < bm->fan_num; i++) {
  552. applog(LOG_DEBUG, "BitMain RxStatus Data fan(%d) fan=%d", i+1, bm->fan[i]);
  553. }
  554. return 0;
  555. }
  556. static int bitmain_parse_rxnonce(const uint8_t * data, int datalen, struct bitmain_rxnonce_data *bm, int * nonce_num)
  557. {
  558. int i = 0;
  559. uint16_t crc = 0;
  560. uint8_t version = 0;
  561. int curnoncenum = 0;
  562. if (unlikely(!bm)) {
  563. applog(LOG_ERR, "bitmain_parse_rxnonce bitmain_rxstatus_data null");
  564. return -1;
  565. }
  566. if (unlikely(!data || datalen <= 0)) {
  567. applog(LOG_ERR, "bitmain_parse_rxnonce data null or datalen(%d) error", datalen);
  568. return -1;
  569. }
  570. memcpy(bm, data, sizeof(struct bitmain_rxnonce_data));
  571. if (bm->data_type != BITMAIN_DATA_TYPE_RXNONCE) {
  572. applog(LOG_ERR, "bitmain_parse_rxnonce datatype(%02x) error", bm->data_type);
  573. return -1;
  574. }
  575. if (bm->version != version) {
  576. applog(LOG_ERR, "bitmain_parse_rxnonce version(%02x) error", bm->version);
  577. return -1;
  578. }
  579. bm->length = htole16(bm->length);
  580. if (bm->length+4 != datalen) {
  581. applog(LOG_ERR, "bitmain_parse_rxnonce length(%d) error", bm->length);
  582. return -1;
  583. }
  584. crc = CRC16(data, datalen-2);
  585. memcpy(&(bm->crc), data+datalen-2, 2);
  586. bm->crc = htole16(bm->crc);
  587. if(crc != bm->crc) {
  588. applog(LOG_ERR, "bitmain_parse_rxnonce check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  589. return -1;
  590. }
  591. bm->fifo_space = htole16(bm->fifo_space);
  592. bm->diff = htole16(bm->diff);
  593. bm->total_nonce_num = htole64(bm->total_nonce_num);
  594. curnoncenum = (datalen-14)/8;
  595. applog(LOG_DEBUG, "BitMain RxNonce Data: nonce_num(%d) fifo_space(%d) diff(%d) tnn(%"PRIu64")", curnoncenum, bm->fifo_space, bm->diff, bm->total_nonce_num);
  596. for(i = 0; i < curnoncenum; i++) {
  597. bm->nonces[i].work_id = htole32(bm->nonces[i].work_id);
  598. bm->nonces[i].nonce = htole32(bm->nonces[i].nonce);
  599. applog(LOG_DEBUG, "BitMain RxNonce Data %d: work_id(%d) nonce(%08x)(%d)",
  600. i, bm->nonces[i].work_id, bm->nonces[i].nonce, bm->nonces[i].nonce);
  601. }
  602. *nonce_num = curnoncenum;
  603. return 0;
  604. }
  605. static int bitmain_read(struct cgpu_info *bitmain, unsigned char *buf,
  606. size_t bufsize, int timeout)
  607. {
  608. int err = 0;
  609. size_t total = 0;
  610. if(bitmain == NULL || buf == NULL || bufsize <= 0) {
  611. applog(LOG_WARNING, "bitmain_read parameter error bufsize(%llu)", (unsigned long long)bufsize);
  612. return -1;
  613. }
  614. {
  615. err = btm_read(bitmain, buf, bufsize);
  616. total = err;
  617. }
  618. return total;
  619. }
  620. static int bitmain_write(struct cgpu_info *bitmain, char *buf, ssize_t len)
  621. {
  622. int err;
  623. {
  624. int havelen = 0;
  625. while(havelen < len) {
  626. err = btm_write(bitmain, buf+havelen, len-havelen);
  627. if(err < 0) {
  628. applog(LOG_DEBUG, "%s%i: btm_write got err %d", bitmain->drv->name,
  629. bitmain->device_id, err);
  630. applog(LOG_WARNING, "usb_write error on bitmain_write");
  631. return BTM_SEND_ERROR;
  632. } else {
  633. havelen += err;
  634. }
  635. }
  636. }
  637. return BTM_SEND_OK;
  638. }
  639. static int bitmain_send_data(const uint8_t * data, int datalen, struct cgpu_info *bitmain)
  640. {
  641. int ret;
  642. if(datalen <= 0) {
  643. return 0;
  644. }
  645. //struct bitmain_info *info = bitmain->device_data;
  646. //int delay;
  647. //delay = datalen * 10 * 1000000;
  648. //delay = delay / info->baud;
  649. //delay += 4000;
  650. if(opt_debug) {
  651. char hex[(datalen * 2) + 1];
  652. bin2hex(hex, data, datalen);
  653. applog(LOG_DEBUG, "BitMain: Sent(%d): %s", datalen, hex);
  654. }
  655. //cgtimer_t ts_start;
  656. //cgsleep_prepare_r(&ts_start);
  657. //applog(LOG_DEBUG, "----bitmain_send_data start");
  658. ret = bitmain_write(bitmain, (char *)data, datalen);
  659. applog(LOG_DEBUG, "----bitmain_send_data stop ret=%d datalen=%d", ret, datalen);
  660. //cgsleep_us_r(&ts_start, delay);
  661. //applog(LOG_DEBUG, "BitMain: Sent: Buffer delay: %dus", delay);
  662. return ret;
  663. }
  664. static void bitmain_inc_nvw(struct bitmain_info *info, struct thr_info *thr)
  665. {
  666. applog(LOG_INFO, "%s%d: No matching work - HW error",
  667. thr->cgpu->drv->name, thr->cgpu->device_id);
  668. inc_hw_errors_only(thr);
  669. info->no_matching_work++;
  670. }
  671. static inline void record_temp_fan(struct bitmain_info *info, struct bitmain_rxstatus_data *bm, float *temp)
  672. {
  673. int i = 0;
  674. int maxfan = 0, maxtemp = 0;
  675. int temp_avg = 0;
  676. info->fan_num = bm->fan_num;
  677. for(i = 0; i < bm->fan_num; i++) {
  678. info->fan[i] = bm->fan[i] * BITMAIN_FAN_FACTOR;
  679. if(info->fan[i] > maxfan)
  680. maxfan = info->fan[i];
  681. }
  682. info->temp_num = bm->temp_num;
  683. for(i = 0; i < bm->temp_num; i++) {
  684. info->temp[i] = bm->temp[i];
  685. /*
  686. if(bm->temp[i] & 0x80) {
  687. bm->temp[i] &= 0x7f;
  688. info->temp[i] = 0 - ((~bm->temp[i] & 0x7f) + 1);
  689. }*/
  690. temp_avg += info->temp[i];
  691. if(info->temp[i] > info->temp_max) {
  692. info->temp_max = info->temp[i];
  693. }
  694. if(info->temp[i] > maxtemp)
  695. maxtemp = info->temp[i];
  696. }
  697. if(bm->temp_num > 0) {
  698. temp_avg /= bm->temp_num;
  699. info->temp_avg = temp_avg;
  700. }
  701. *temp = maxtemp;
  702. }
  703. static void bitmain_update_temps(struct cgpu_info *bitmain, struct bitmain_info *info,
  704. struct bitmain_rxstatus_data *bm)
  705. {
  706. char tmp[64] = {0};
  707. char msg[10240] = {0};
  708. int i = 0;
  709. record_temp_fan(info, bm, &(bitmain->temp));
  710. strcpy(msg, "BitMain: ");
  711. for(i = 0; i < bm->fan_num; i++) {
  712. if(i != 0) {
  713. strcat(msg, ", ");
  714. }
  715. sprintf(tmp, "Fan%d: %d/m", i+1, info->fan[i]);
  716. strcat(msg, tmp);
  717. }
  718. strcat(msg, "\t");
  719. for(i = 0; i < bm->temp_num; i++) {
  720. if(i != 0) {
  721. strcat(msg, ", ");
  722. }
  723. sprintf(tmp, "Temp%d: %dC", i+1, info->temp[i]);
  724. strcat(msg, tmp);
  725. }
  726. sprintf(tmp, ", TempMAX: %dC", info->temp_max);
  727. strcat(msg, tmp);
  728. applog(LOG_INFO, "%s", msg);
  729. info->temp_history_index++;
  730. info->temp_sum += bitmain->temp;
  731. applog(LOG_DEBUG, "BitMain: temp_index: %d, temp_count: %d, temp_old: %d",
  732. info->temp_history_index, info->temp_history_count, info->temp_old);
  733. if (info->temp_history_index == info->temp_history_count) {
  734. info->temp_history_index = 0;
  735. info->temp_sum = 0;
  736. }
  737. }
  738. static void bitmain_set_fifo_space(struct cgpu_info * const dev, const int fifo_space)
  739. {
  740. struct thr_info * const master_thr = dev->thr[0];
  741. struct bitmain_info * const info = dev->device_data;
  742. if (unlikely(fifo_space > info->max_fifo_space))
  743. info->max_fifo_space = fifo_space;
  744. info->fifo_space = fifo_space;
  745. master_thr->queue_full = !fifo_space;
  746. }
  747. static void bitmain_parse_results(struct cgpu_info *bitmain, struct bitmain_info *info,
  748. struct thr_info *thr, uint8_t *buf, int *offset)
  749. {
  750. int i, j, n, m, r, errordiff, spare = BITMAIN_READ_SIZE;
  751. uint32_t checkbit = 0x00000000;
  752. bool found = false;
  753. struct work *work = NULL;
  754. struct bitmain_packet_head packethead;
  755. int asicnum = 0;
  756. int mod = 0,tmp = 0;
  757. for (i = 0; i <= spare; i++) {
  758. if(buf[i] == 0xa1) {
  759. struct bitmain_rxstatus_data rxstatusdata;
  760. applog(LOG_DEBUG, "bitmain_parse_results RxStatus Data");
  761. if(*offset < 4) {
  762. return;
  763. }
  764. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  765. packethead.length = htole16(packethead.length);
  766. if(packethead.length > 1130) {
  767. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus datalen=%d error", packethead.length+4);
  768. continue;
  769. }
  770. if(*offset < packethead.length + 4) {
  771. return;
  772. }
  773. if(bitmain_parse_rxstatus(buf+i, packethead.length+4, &rxstatusdata) != 0) {
  774. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus error len=%d", packethead.length+4);
  775. } else {
  776. mutex_lock(&info->qlock);
  777. info->chain_num = rxstatusdata.chain_num;
  778. bitmain_set_fifo_space(bitmain, rxstatusdata.fifo_space);
  779. info->hw_version[0] = rxstatusdata.hw_version[0];
  780. info->hw_version[1] = rxstatusdata.hw_version[1];
  781. info->hw_version[2] = rxstatusdata.hw_version[2];
  782. info->hw_version[3] = rxstatusdata.hw_version[3];
  783. info->nonce_error = rxstatusdata.nonce_error;
  784. errordiff = info->nonce_error-info->last_nonce_error;
  785. //sprintf(g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  786. applog(LOG_ERR, "bitmain_parse_results v=%d chain=%d fifo=%d hwv1=%d hwv2=%d hwv3=%d hwv4=%d nerr=%d-%d freq=%d chain info:",
  787. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  788. info->last_nonce_error, info->nonce_error, info->frequency);
  789. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  790. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  791. for(n = 0; n < rxstatusdata.chain_num; n++) {
  792. info->chain_asic_num[n] = rxstatusdata.chain_asic_num[n];
  793. memset(info->chain_asic_status_t[n], 0, 320);
  794. j = 0;
  795. mod = 0;
  796. if(info->chain_asic_num[n] <= 0) {
  797. asicnum = 0;
  798. } else {
  799. mod = info->chain_asic_num[n] % 32;
  800. if(mod == 0) {
  801. asicnum = info->chain_asic_num[n] / 32;
  802. } else {
  803. asicnum = info->chain_asic_num[n] / 32 + 1;
  804. }
  805. }
  806. if(asicnum > 0) {
  807. for(m = asicnum-1; m >= 0; m--) {
  808. tmp = mod ? (32-mod): 0;
  809. for(r = tmp;r < 32;r++){
  810. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  811. info->chain_asic_status_t[n][j] = ' ';
  812. j++;
  813. }
  814. checkbit = num2bit(r);
  815. if(rxstatusdata.chain_asic_exist[n*8+m] & checkbit) {
  816. if(rxstatusdata.chain_asic_status[n*8+m] & checkbit) {
  817. info->chain_asic_status_t[n][j] = 'o';
  818. } else {
  819. info->chain_asic_status_t[n][j] = 'x';
  820. }
  821. } else {
  822. info->chain_asic_status_t[n][j] = '-';
  823. }
  824. j++;
  825. }
  826. info->chain_asic_status_t[n][j] = ' ';
  827. j++;
  828. mod = 0;
  829. }
  830. }
  831. applog(LOG_DEBUG, "bitmain_parse_results chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  832. n, info->chain_asic_num[n],
  833. info->chain_asic_exist[n*8+0], info->chain_asic_exist[n*8+1], info->chain_asic_exist[n*8+2], info->chain_asic_exist[n*8+3], info->chain_asic_exist[n*8+4], info->chain_asic_exist[n*8+5], info->chain_asic_exist[n*8+6], info->chain_asic_exist[n*8+7],
  834. info->chain_asic_status[n*8+0], info->chain_asic_status[n*8+1], info->chain_asic_status[n*8+2], info->chain_asic_status[n*8+3], info->chain_asic_status[n*8+4], info->chain_asic_status[n*8+5], info->chain_asic_status[n*8+6], info->chain_asic_status[n*8+7]);
  835. applog(LOG_ERR, "bitmain_parse_results chain(%d) asic_num=%d asic_status=%s", n, info->chain_asic_num[n], info->chain_asic_status_t[n]);
  836. }
  837. mutex_unlock(&info->qlock);
  838. if(errordiff > 0) {
  839. for(j = 0; j < errordiff; j++) {
  840. bitmain_inc_nvw(info, thr);
  841. }
  842. mutex_lock(&info->qlock);
  843. info->last_nonce_error += errordiff;
  844. mutex_unlock(&info->qlock);
  845. }
  846. bitmain_update_temps(bitmain, info, &rxstatusdata);
  847. }
  848. found = true;
  849. spare = packethead.length + 4 + i;
  850. if(spare > *offset) {
  851. applog(LOG_ERR, "bitmain_parse_rxresults space(%d) > offset(%d)", spare, *offset);
  852. spare = *offset;
  853. }
  854. break;
  855. } else if(buf[i] == 0xa2) {
  856. struct bitmain_rxnonce_data rxnoncedata;
  857. int nonce_num = 0;
  858. applog(LOG_DEBUG, "bitmain_parse_results RxNonce Data");
  859. if(*offset < 4) {
  860. return;
  861. }
  862. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  863. packethead.length = htole16(packethead.length);
  864. if(packethead.length > 1038) {
  865. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce datalen=%d error", packethead.length+4);
  866. continue;
  867. }
  868. if(*offset < packethead.length + 4) {
  869. return;
  870. }
  871. if(bitmain_parse_rxnonce(buf+i, packethead.length+4, &rxnoncedata, &nonce_num) != 0) {
  872. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce error len=%d", packethead.length+4);
  873. } else {
  874. const float nonce_diff = 1 << rxnoncedata.diff;
  875. for(j = 0; j < nonce_num; j++) {
  876. const work_device_id_t work_id = rxnoncedata.nonces[j].work_id;
  877. HASH_FIND(hh, thr->work_list, &work_id, sizeof(work_id), work);
  878. if(work) {
  879. if(BITMAIN_TEST_PRINT_WORK) {
  880. applog(LOG_ERR, "bitmain_parse_results nonce find work(%d-%d)(%08x)", work->id, rxnoncedata.nonces[j].work_id, rxnoncedata.nonces[j].nonce);
  881. char ob_hex[(32 * 2) + 1];
  882. bin2hex(ob_hex, work->midstate, 32);
  883. applog(LOG_ERR, "work %d midstate: %s", work->id, ob_hex);
  884. bin2hex(ob_hex, &work->data[64], 12);
  885. applog(LOG_ERR, "work %d data2: %s", work->id, ob_hex);
  886. }
  887. {
  888. const uint32_t nonce = rxnoncedata.nonces[j].nonce;
  889. applog(LOG_DEBUG, "BitMain: submit nonce = %08lx", (unsigned long)nonce);
  890. work->nonce_diff = nonce_diff;
  891. if (submit_nonce(thr, work, nonce)) {
  892. mutex_lock(&info->qlock);
  893. hashes_done2(thr, 0x100000000 * work->nonce_diff, NULL);
  894. mutex_unlock(&info->qlock);
  895. } else {
  896. applog(LOG_ERR, "BitMain: bitmain_decode_nonce error work(%d)", rxnoncedata.nonces[j].work_id);
  897. }
  898. }
  899. } else {
  900. bitmain_inc_nvw(info, thr);
  901. applog(LOG_ERR, "BitMain: Nonce not find work(%d)", rxnoncedata.nonces[j].work_id);
  902. }
  903. }
  904. mutex_lock(&info->qlock);
  905. bitmain_set_fifo_space(bitmain, rxnoncedata.fifo_space);
  906. mutex_unlock(&info->qlock);
  907. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  908. #ifndef WIN32
  909. if(nonce_num < BITMAIN_MAX_NONCE_NUM)
  910. cgsleep_ms(5);
  911. #endif
  912. }
  913. found = true;
  914. spare = packethead.length + 4 + i;
  915. if(spare > *offset) {
  916. applog(LOG_ERR, "bitmain_parse_rxnonce space(%d) > offset(%d)", spare, *offset);
  917. spare = *offset;
  918. }
  919. break;
  920. } else {
  921. applog(LOG_ERR, "bitmain_parse_results data type error=%02x", buf[i]);
  922. }
  923. }
  924. if (!found) {
  925. spare = *offset - BITMAIN_READ_SIZE;
  926. /* We are buffering and haven't accumulated one more corrupt
  927. * work result. */
  928. if (spare < (int)BITMAIN_READ_SIZE)
  929. return;
  930. bitmain_inc_nvw(info, thr);
  931. }
  932. *offset -= spare;
  933. memmove(buf, buf + spare, *offset);
  934. }
  935. static void bitmain_running_reset(struct cgpu_info *bitmain, struct bitmain_info *info)
  936. {
  937. info->reset = false;
  938. }
  939. static void bitmain_prune_old_work(struct cgpu_info * const dev)
  940. {
  941. struct thr_info * const master_thr = dev->thr[0];
  942. struct bitmain_info * const info = dev->device_data;
  943. const size_t retain_work_items = info->max_fifo_space * 2;
  944. const size_t queued_work_items = HASH_COUNT(master_thr->work_list);
  945. if (queued_work_items > retain_work_items) {
  946. size_t remove_work_items = queued_work_items - retain_work_items;
  947. while (remove_work_items--) {
  948. // Deletes the first item insertion-order
  949. struct work * const work = master_thr->work_list;
  950. HASH_DEL(master_thr->work_list, work);
  951. free_work(work);
  952. }
  953. }
  954. }
  955. static void bitmain_poll(struct thr_info * const thr)
  956. {
  957. struct cgpu_info *bitmain = thr->cgpu;
  958. struct bitmain_info *info = bitmain->device_data;
  959. int offset = info->readbuf_offset, ret = 0;
  960. const int rsize = BITMAIN_FTDI_READSIZE;
  961. uint8_t * const readbuf = info->readbuf;
  962. {
  963. unsigned char buf[rsize];
  964. if (unlikely(info->reset)) {
  965. bitmain_running_reset(bitmain, info);
  966. /* Discard anything in the buffer */
  967. offset = 0;
  968. }
  969. //cgsleep_prepare_r(&ts_start);
  970. //applog(LOG_DEBUG, "======start bitmain_get_results bitmain_read");
  971. ret = bitmain_read(bitmain, buf, rsize, BITMAIN_READ_TIMEOUT);
  972. //applog(LOG_DEBUG, "======stop bitmain_get_results bitmain_read=%d", ret);
  973. if ((ret < 1) || (ret == 18)) {
  974. ++info->errorcount2;
  975. #ifdef WIN32
  976. if(info->errorcount2 > 200) {
  977. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  978. cgsleep_ms(20);
  979. info->errorcount2 = 0;
  980. }
  981. #else
  982. if(info->errorcount2 > 3) {
  983. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  984. cgsleep_ms(20);
  985. info->errorcount2 = 0;
  986. }
  987. #endif
  988. if(ret < 1)
  989. return;
  990. }
  991. if (opt_debug) {
  992. char hex[(ret * 2) + 1];
  993. bin2hex(hex, buf, ret);
  994. applog(LOG_DEBUG, "BitMain: get: %s", hex);
  995. }
  996. memcpy(readbuf+offset, buf, ret);
  997. offset += ret;
  998. //applog(LOG_DEBUG, "+++++++bitmain_get_results offset=%d", offset);
  999. if (offset >= (int)BITMAIN_READ_SIZE) {
  1000. //applog(LOG_DEBUG, "======start bitmain_get_results ");
  1001. bitmain_parse_results(bitmain, info, thr, readbuf, &offset);
  1002. //applog(LOG_DEBUG, "======stop bitmain_get_results ");
  1003. }
  1004. if (unlikely(offset + rsize >= BITMAIN_READBUF_SIZE)) {
  1005. /* This should never happen */
  1006. applog(LOG_DEBUG, "BitMain readbuf overflow, resetting buffer");
  1007. offset = 0;
  1008. }
  1009. /* As the usb read returns after just 1ms, sleep long enough
  1010. * to leave the interface idle for writes to occur, but do not
  1011. * sleep if we have been receiving data as more may be coming. */
  1012. //if (offset == 0) {
  1013. // cgsleep_ms_r(&ts_start, BITMAIN_READ_TIMEOUT);
  1014. //}
  1015. }
  1016. info->readbuf_offset = offset;
  1017. bitmain_prune_old_work(bitmain);
  1018. timer_set_delay_from_now(&thr->tv_poll, bitmain_poll_interval_us);
  1019. }
  1020. static void bitmain_init(struct cgpu_info *bitmain)
  1021. {
  1022. applog(LOG_INFO, "BitMain: Opened on %s", bitmain->device_path);
  1023. }
  1024. static bool bitmain_prepare(struct thr_info *thr)
  1025. {
  1026. struct cgpu_info *bitmain = thr->cgpu;
  1027. struct bitmain_info *info = bitmain->device_data;
  1028. mutex_init(&info->qlock);
  1029. // To initialise queue_full
  1030. bitmain_set_fifo_space(bitmain, info->fifo_space);
  1031. bitmain_init(bitmain);
  1032. timer_set_now(&thr->tv_poll);
  1033. return true;
  1034. }
  1035. static int bitmain_initialize(struct cgpu_info *bitmain)
  1036. {
  1037. uint8_t data[BITMAIN_READBUF_SIZE];
  1038. struct bitmain_info *info = NULL;
  1039. int ret = 0;
  1040. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1041. int readlen = 0;
  1042. int sendlen = 0;
  1043. int trycount = 3;
  1044. struct timespec p;
  1045. struct bitmain_rxstatus_data rxstatusdata;
  1046. int i = 0, j = 0, m = 0, r = 0, statusok = 0;
  1047. uint32_t checkbit = 0x00000000;
  1048. int hwerror_eft = 0;
  1049. int beeper_ctrl = 1;
  1050. int tempover_ctrl = 1;
  1051. int home_mode = 0;
  1052. struct bitmain_packet_head packethead;
  1053. int asicnum = 0;
  1054. int mod = 0,tmp = 0;
  1055. /* Send reset, then check for result */
  1056. if(!bitmain) {
  1057. applog(LOG_WARNING, "bitmain_initialize cgpu_info is null");
  1058. return -1;
  1059. }
  1060. info = bitmain->device_data;
  1061. /* clear read buf */
  1062. ret = bitmain_read(bitmain, data, BITMAIN_READBUF_SIZE,
  1063. BITMAIN_RESET_TIMEOUT);
  1064. if(ret > 0) {
  1065. if (opt_debug) {
  1066. char hex[(ret * 2) + 1];
  1067. bin2hex(hex, data, ret);
  1068. applog(LOG_DEBUG, "BTM%d Clear Read(%d): %s", bitmain->device_id, ret, hex);
  1069. }
  1070. }
  1071. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *)sendbuf, 0, 1, 0, 0);
  1072. if(sendlen <= 0) {
  1073. applog(LOG_ERR, "bitmain_initialize bitmain_set_rxstatus error(%d)", sendlen);
  1074. return -1;
  1075. }
  1076. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1077. if (unlikely(ret == BTM_SEND_ERROR)) {
  1078. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1079. return -1;
  1080. }
  1081. while(trycount >= 0) {
  1082. ret = bitmain_read(bitmain, data+readlen, BITMAIN_READBUF_SIZE, BITMAIN_RESET_TIMEOUT);
  1083. if(ret > 0) {
  1084. readlen += ret;
  1085. if(readlen > BITMAIN_READ_SIZE) {
  1086. for(i = 0; i < readlen; i++) {
  1087. if(data[i] == 0xa1) {
  1088. if (opt_debug) {
  1089. char hex[(readlen * 2) + 1];
  1090. bin2hex(hex, data, readlen);
  1091. applog(LOG_DEBUG, "%s%d initset: get: %s", bitmain->drv->name, bitmain->device_id, hex);
  1092. }
  1093. memcpy(&packethead, data+i, sizeof(struct bitmain_packet_head));
  1094. packethead.length = htole16(packethead.length);
  1095. if(packethead.length > 1130) {
  1096. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d error", packethead.length+4);
  1097. continue;
  1098. }
  1099. if(readlen-i < packethead.length+4) {
  1100. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d<%d low", readlen-i, packethead.length+4);
  1101. continue;
  1102. }
  1103. if (bitmain_parse_rxstatus(data+i, packethead.length+4, &rxstatusdata) != 0) {
  1104. applog(LOG_ERR, "bitmain_initialize bitmain_parse_rxstatus error");
  1105. continue;
  1106. }
  1107. info->chain_num = rxstatusdata.chain_num;
  1108. // NOTE: This is before thr_info is allocated, so we cannot use bitmain_set_fifo_space (bitmain_prepare will re-set it for us)
  1109. info->fifo_space = rxstatusdata.fifo_space;
  1110. info->hw_version[0] = rxstatusdata.hw_version[0];
  1111. info->hw_version[1] = rxstatusdata.hw_version[1];
  1112. info->hw_version[2] = rxstatusdata.hw_version[2];
  1113. info->hw_version[3] = rxstatusdata.hw_version[3];
  1114. info->nonce_error = 0;
  1115. info->last_nonce_error = 0;
  1116. sprintf(info->g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  1117. applog(LOG_ERR, "bitmain_initialize rxstatus v(%d) chain(%d) fifo(%d) hwv1(%d) hwv2(%d) hwv3(%d) hwv4(%d) nerr(%d) freq=%d",
  1118. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  1119. rxstatusdata.nonce_error, info->frequency);
  1120. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  1121. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  1122. for(i = 0; i < rxstatusdata.chain_num; i++) {
  1123. info->chain_asic_num[i] = rxstatusdata.chain_asic_num[i];
  1124. memset(info->chain_asic_status_t[i], 0, 320);
  1125. j = 0;
  1126. mod = 0;
  1127. if(info->chain_asic_num[i] <= 0) {
  1128. asicnum = 0;
  1129. } else {
  1130. mod = info->chain_asic_num[i] % 32;
  1131. if(mod == 0) {
  1132. asicnum = info->chain_asic_num[i] / 32;
  1133. } else {
  1134. asicnum = info->chain_asic_num[i] / 32 + 1;
  1135. }
  1136. }
  1137. if(asicnum > 0) {
  1138. for(m = asicnum-1; m >= 0; m--) {
  1139. tmp = mod ? (32-mod):0;
  1140. for(r = tmp;r < 32;r++){
  1141. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  1142. info->chain_asic_status_t[i][j] = ' ';
  1143. j++;
  1144. }
  1145. checkbit = num2bit(r);
  1146. if(rxstatusdata.chain_asic_exist[i*8+m] & checkbit) {
  1147. if(rxstatusdata.chain_asic_status[i*8+m] & checkbit) {
  1148. info->chain_asic_status_t[i][j] = 'o';
  1149. } else {
  1150. info->chain_asic_status_t[i][j] = 'x';
  1151. }
  1152. } else {
  1153. info->chain_asic_status_t[i][j] = '-';
  1154. }
  1155. j++;
  1156. }
  1157. info->chain_asic_status_t[i][j] = ' ';
  1158. j++;
  1159. mod = 0;
  1160. }
  1161. }
  1162. applog(LOG_DEBUG, "bitmain_initialize chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  1163. i, info->chain_asic_num[i],
  1164. info->chain_asic_exist[i*8+0], info->chain_asic_exist[i*8+1], info->chain_asic_exist[i*8+2], info->chain_asic_exist[i*8+3], info->chain_asic_exist[i*8+4], info->chain_asic_exist[i*8+5], info->chain_asic_exist[i*8+6], info->chain_asic_exist[i*8+7],
  1165. info->chain_asic_status[i*8+0], info->chain_asic_status[i*8+1], info->chain_asic_status[i*8+2], info->chain_asic_status[i*8+3], info->chain_asic_status[i*8+4], info->chain_asic_status[i*8+5], info->chain_asic_status[i*8+6], info->chain_asic_status[i*8+7]);
  1166. applog(LOG_ERR, "bitmain_initialize chain(%d) asic_num=%d asic_status=%s", i, info->chain_asic_num[i], info->chain_asic_status_t[i]);
  1167. }
  1168. bitmain_update_temps(bitmain, info, &rxstatusdata);
  1169. statusok = 1;
  1170. break;
  1171. }
  1172. }
  1173. if(statusok) {
  1174. break;
  1175. }
  1176. }
  1177. }
  1178. trycount--;
  1179. p.tv_sec = 0;
  1180. p.tv_nsec = BITMAIN_RESET_PITCH;
  1181. nanosleep(&p, NULL);
  1182. }
  1183. p.tv_sec = 0;
  1184. p.tv_nsec = BITMAIN_RESET_PITCH;
  1185. nanosleep(&p, NULL);
  1186. if(statusok) {
  1187. applog(LOG_ERR, "bitmain_initialize start send txconfig");
  1188. if(opt_bitmain_hwerror)
  1189. hwerror_eft = 1;
  1190. else
  1191. hwerror_eft = 0;
  1192. if(opt_bitmain_nobeeper)
  1193. beeper_ctrl = 0;
  1194. else
  1195. beeper_ctrl = 1;
  1196. if(opt_bitmain_notempoverctrl)
  1197. tempover_ctrl = 0;
  1198. else
  1199. tempover_ctrl = 1;
  1200. if(opt_bitmain_homemode)
  1201. home_mode= 1;
  1202. else
  1203. home_mode= 0;
  1204. sendlen = bitmain_set_txconfig((struct bitmain_txconfig_token *)sendbuf, 1, 1, 1, 1, 1, 0, 1, hwerror_eft, beeper_ctrl, tempover_ctrl,home_mode,
  1205. info->chain_num, info->asic_num, BITMAIN_DEFAULT_FAN_MAX_PWM, info->timeout,
  1206. info->frequency, info->voltage, 0, 0, 0x04, info->reg_data);
  1207. if(sendlen <= 0) {
  1208. applog(LOG_ERR, "bitmain_initialize bitmain_set_txconfig error(%d)", sendlen);
  1209. return -1;
  1210. }
  1211. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1212. if (unlikely(ret == BTM_SEND_ERROR)) {
  1213. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1214. return -1;
  1215. }
  1216. applog(LOG_WARNING, "BMM%d: InitSet succeeded", bitmain->device_id);
  1217. } else {
  1218. applog(LOG_WARNING, "BMS%d: InitSet error", bitmain->device_id);
  1219. return -1;
  1220. }
  1221. return 0;
  1222. }
  1223. static bool bitmain_detect_one(const char * devpath)
  1224. {
  1225. struct bitmain_info *info;
  1226. struct cgpu_info *bitmain;
  1227. int ret;
  1228. bitmain = btm_alloc_cgpu(&bitmain_drv, BITMAIN_MINER_THREADS);
  1229. info = bitmain->device_data;
  1230. drv_set_defaults(&bitmain_drv, bitmain_set_device_funcs_init, info, devpath, NULL, 1);
  1231. if (!btm_init(bitmain, devpath))
  1232. goto shin;
  1233. applog(LOG_ERR, "bitmain_detect_one btm init ok");
  1234. info->fan_pwm = BITMAIN_DEFAULT_FAN_MIN_PWM;
  1235. info->temp_max = 0;
  1236. /* This is for check the temp/fan every 3~4s */
  1237. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  1238. if (info->temp_history_count <= 0)
  1239. info->temp_history_count = 1;
  1240. info->temp_history_index = 0;
  1241. info->temp_sum = 0;
  1242. info->temp_old = 0;
  1243. if (!add_cgpu(bitmain))
  1244. goto unshin;
  1245. ret = bitmain_initialize(bitmain);
  1246. applog(LOG_ERR, "bitmain_detect_one stop bitmain_initialize %d", ret);
  1247. if (ret)
  1248. goto unshin;
  1249. info->errorcount = 0;
  1250. applog(LOG_ERR, "BitMain Detected: %s "
  1251. "(chain_num=%d asic_num=%d timeout=%d freq=%d-%s volt=%02x%02x-%s)",
  1252. bitmain->device_path, info->chain_num, info->asic_num, info->timeout,
  1253. info->frequency, info->frequency_t, info->voltage[0], info->voltage[1], info->voltage_t);
  1254. return true;
  1255. unshin:
  1256. btm_uninit(bitmain);
  1257. shin:
  1258. free(bitmain->device_data);
  1259. bitmain->device_data = NULL;
  1260. free(bitmain);
  1261. return false;
  1262. }
  1263. static int bitmain_detect_auto(void)
  1264. {
  1265. const char * const auto_bitmain_dev = "/dev/bitmain-asic";
  1266. applog(LOG_DEBUG, "BTM detect dev: %s", auto_bitmain_dev);
  1267. return bitmain_detect_one(auto_bitmain_dev) ? 1 : 0;
  1268. }
  1269. static void bitmain_detect()
  1270. {
  1271. generic_detect(&bitmain_drv, bitmain_detect_one, bitmain_detect_auto, GDF_REQUIRE_DNAME | GDF_DEFAULT_NOAUTO);
  1272. }
  1273. static void do_bitmain_close(struct thr_info *thr)
  1274. {
  1275. struct cgpu_info *bitmain = thr->cgpu;
  1276. struct bitmain_info *info = bitmain->device_data;
  1277. bitmain_running_reset(bitmain, info);
  1278. info->no_matching_work = 0;
  1279. }
  1280. static uint8_t diff_to_bitmain(float diff)
  1281. {
  1282. uint8_t res = 0;
  1283. if (diff > UINT64_MAX)
  1284. diff = UINT64_MAX;
  1285. for (uint64_t tmp = diff; tmp >>= 1; ) {
  1286. if (++res == UINT8_MAX)
  1287. break;
  1288. }
  1289. return res;
  1290. }
  1291. static bool bitmain_queue_append(struct thr_info * const thr, struct work * const work)
  1292. {
  1293. struct cgpu_info * const proc = thr->cgpu;
  1294. struct cgpu_info * const dev = proc->device;
  1295. struct thr_info * const master_thr = dev->thr[0];
  1296. struct bitmain_info * const info = dev->device_data;
  1297. const struct pool * const pool = work->pool;
  1298. const struct mining_goal_info * const goal = pool->goal;
  1299. applog(LOG_DEBUG, "%s: %s with fifo_space=%d (max=%d) work_restart=%d", dev->dev_repr, __func__, info->fifo_space, info->max_fifo_space, (int)info->work_restart);
  1300. if (info->work_restart) {
  1301. info->work_restart = false;
  1302. info->ready_to_queue = 0;
  1303. bitmain_set_fifo_space(dev, info->max_fifo_space);
  1304. info->queuebuf[4] = 1; // clear work queues
  1305. }
  1306. if (!info->fifo_space) {
  1307. thr->queue_full = true;
  1308. return false;
  1309. }
  1310. uint8_t * const wbuf = &info->queuebuf[BITMAIN_TASK_HEADER_SIZE + (BITMAIN_WORK_SIZE * info->ready_to_queue)];
  1311. const int work_nonce_bmdiff = diff_to_bitmain(work->nonce_diff);
  1312. if (work_nonce_bmdiff < info->diff)
  1313. info->diff = work_nonce_bmdiff;
  1314. if (goal->current_diff < info->lowest_goal_diff)
  1315. info->lowest_goal_diff = goal->current_diff;
  1316. work->device_id = info->next_work_id++;
  1317. pk_u32le(wbuf, 0, work->device_id);
  1318. memcpy(&wbuf[4], work->midstate, 0x20);
  1319. memcpy(&wbuf[0x24], &work->data[0x40], 0xc);
  1320. HASH_ADD(hh, master_thr->work_list, device_id, sizeof(work->device_id), work);
  1321. ++info->ready_to_queue;
  1322. if (!(info->ready_to_queue == BITMAIN_MAX_WORK_NUM || info->fifo_space == info->ready_to_queue || info->fifo_space == info->max_fifo_space)) {
  1323. applog(LOG_DEBUG, "%s: %s now has ready_to_queue=%d; deferring send", dev->dev_repr, __func__, info->ready_to_queue);
  1324. return true;
  1325. }
  1326. applog(LOG_DEBUG, "%s: %s now has ready_to_queue=%d; sending to device", dev->dev_repr, __func__, info->ready_to_queue);
  1327. uint8_t * const buf = info->queuebuf;
  1328. const size_t buflen = BITMAIN_TASK_HEADER_SIZE + (info->ready_to_queue * BITMAIN_WORK_SIZE) + BITMAIN_TASK_FOOTER_SIZE;
  1329. buf[0] = BITMAIN_TOKEN_TYPE_TXTASK;
  1330. buf[1] = 0; // packet version
  1331. pk_u16le(buf, 2, buflen - 4); // length of data after this field (including CRC)
  1332. // buf[4] is set to 1 to clear work queues, when the first work item is added, and reset to 0 after we send
  1333. buf[5] = info->diff;
  1334. pk_u16le(buf, 6, diff_to_bitmain(info->lowest_goal_diff));
  1335. pk_u16le(buf, buflen - 2, CRC16(buf, buflen - 2));
  1336. int sendret = bitmain_send_data(buf, buflen, proc);
  1337. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1338. applog(LOG_ERR, "%s: Comms error(buffer)", dev->dev_repr);
  1339. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1340. info->reset = true;
  1341. info->errorcount++;
  1342. if (info->errorcount > 1000) {
  1343. info->errorcount = 0;
  1344. applog(LOG_ERR, "%s: Device disappeared, shutting down thread", dev->dev_repr);
  1345. dev->shutdown = true;
  1346. }
  1347. // The work is in the queuebuf already, so we're okay-ish for that...
  1348. return true;
  1349. } else {
  1350. applog(LOG_DEBUG, "bitmain_send_data send ret=%d", sendret);
  1351. info->errorcount = 0;
  1352. }
  1353. buf[4] = 0;
  1354. info->fifo_space -= info->ready_to_queue;
  1355. info->ready_to_queue = 0;
  1356. return true;
  1357. }
  1358. static void bitmain_queue_flush(struct thr_info * const thr)
  1359. {
  1360. struct cgpu_info * const proc = thr->cgpu;
  1361. struct cgpu_info * const dev = proc->device;
  1362. struct bitmain_info * const info = dev->device_data;
  1363. // Can't use thr->work_restart as that merely triggers this function in minerloop_queue
  1364. info->work_restart = true;
  1365. thr->queue_full = false;
  1366. }
  1367. static struct api_data *bitmain_api_stats(struct cgpu_info *cgpu)
  1368. {
  1369. struct api_data *root = NULL;
  1370. struct bitmain_info *info = cgpu->device_data;
  1371. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1372. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1373. root = api_add_int(root, "baud", &(info->baud), false);
  1374. root = api_add_int(root, "miner_count", &(info->chain_num), false);
  1375. root = api_add_int(root, "asic_count", &(info->asic_num), false);
  1376. root = api_add_int(root, "timeout", &(info->timeout), false);
  1377. root = api_add_string(root, "frequency", info->frequency_t, false);
  1378. root = api_add_string(root, "voltage", info->voltage_t, false);
  1379. root = api_add_int(root, "hwv1", &(info->hw_version[0]), false);
  1380. root = api_add_int(root, "hwv2", &(info->hw_version[1]), false);
  1381. root = api_add_int(root, "hwv3", &(info->hw_version[2]), false);
  1382. root = api_add_int(root, "hwv4", &(info->hw_version[3]), false);
  1383. root = api_add_int(root, "fan_num", &(info->fan_num), false);
  1384. root = api_add_int(root, "fan1", &(info->fan[0]), false);
  1385. root = api_add_int(root, "fan2", &(info->fan[1]), false);
  1386. root = api_add_int(root, "fan3", &(info->fan[2]), false);
  1387. root = api_add_int(root, "fan4", &(info->fan[3]), false);
  1388. root = api_add_int(root, "fan5", &(info->fan[4]), false);
  1389. root = api_add_int(root, "fan6", &(info->fan[5]), false);
  1390. root = api_add_int(root, "fan7", &(info->fan[6]), false);
  1391. root = api_add_int(root, "fan8", &(info->fan[7]), false);
  1392. root = api_add_int(root, "fan9", &(info->fan[8]), false);
  1393. root = api_add_int(root, "fan10", &(info->fan[9]), false);
  1394. root = api_add_int(root, "fan11", &(info->fan[10]), false);
  1395. root = api_add_int(root, "fan12", &(info->fan[11]), false);
  1396. root = api_add_int(root, "fan13", &(info->fan[12]), false);
  1397. root = api_add_int(root, "fan14", &(info->fan[13]), false);
  1398. root = api_add_int(root, "fan15", &(info->fan[14]), false);
  1399. root = api_add_int(root, "fan16", &(info->fan[15]), false);
  1400. root = api_add_int(root, "temp_num", &(info->temp_num), false);
  1401. root = api_add_int(root, "temp1", &(info->temp[0]), false);
  1402. root = api_add_int(root, "temp2", &(info->temp[1]), false);
  1403. root = api_add_int(root, "temp3", &(info->temp[2]), false);
  1404. root = api_add_int(root, "temp4", &(info->temp[3]), false);
  1405. root = api_add_int(root, "temp5", &(info->temp[4]), false);
  1406. root = api_add_int(root, "temp6", &(info->temp[5]), false);
  1407. root = api_add_int(root, "temp7", &(info->temp[6]), false);
  1408. root = api_add_int(root, "temp8", &(info->temp[7]), false);
  1409. root = api_add_int(root, "temp9", &(info->temp[8]), false);
  1410. root = api_add_int(root, "temp10", &(info->temp[9]), false);
  1411. root = api_add_int(root, "temp11", &(info->temp[10]), false);
  1412. root = api_add_int(root, "temp12", &(info->temp[11]), false);
  1413. root = api_add_int(root, "temp13", &(info->temp[12]), false);
  1414. root = api_add_int(root, "temp14", &(info->temp[13]), false);
  1415. root = api_add_int(root, "temp15", &(info->temp[14]), false);
  1416. root = api_add_int(root, "temp16", &(info->temp[15]), false);
  1417. root = api_add_int(root, "temp_avg", &(info->temp_avg), false);
  1418. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1419. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1420. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1421. /*
  1422. for (int i = 0; i < info->chain_num; ++i) {
  1423. char mcw[24];
  1424. sprintf(mcw, "match_work_count%d", i + 1);
  1425. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1426. }*/
  1427. root = api_add_int(root, "chain_acn1", &(info->chain_asic_num[0]), false);
  1428. root = api_add_int(root, "chain_acn2", &(info->chain_asic_num[1]), false);
  1429. root = api_add_int(root, "chain_acn3", &(info->chain_asic_num[2]), false);
  1430. root = api_add_int(root, "chain_acn4", &(info->chain_asic_num[3]), false);
  1431. root = api_add_int(root, "chain_acn5", &(info->chain_asic_num[4]), false);
  1432. root = api_add_int(root, "chain_acn6", &(info->chain_asic_num[5]), false);
  1433. root = api_add_int(root, "chain_acn7", &(info->chain_asic_num[6]), false);
  1434. root = api_add_int(root, "chain_acn8", &(info->chain_asic_num[7]), false);
  1435. root = api_add_int(root, "chain_acn9", &(info->chain_asic_num[8]), false);
  1436. root = api_add_int(root, "chain_acn10", &(info->chain_asic_num[9]), false);
  1437. root = api_add_int(root, "chain_acn11", &(info->chain_asic_num[10]), false);
  1438. root = api_add_int(root, "chain_acn12", &(info->chain_asic_num[11]), false);
  1439. root = api_add_int(root, "chain_acn13", &(info->chain_asic_num[12]), false);
  1440. root = api_add_int(root, "chain_acn14", &(info->chain_asic_num[13]), false);
  1441. root = api_add_int(root, "chain_acn15", &(info->chain_asic_num[14]), false);
  1442. root = api_add_int(root, "chain_acn16", &(info->chain_asic_num[15]), false);
  1443. //applog(LOG_ERR, "chain asic status:%s", info->chain_asic_status_t[0]);
  1444. root = api_add_string(root, "chain_acs1", info->chain_asic_status_t[0], false);
  1445. root = api_add_string(root, "chain_acs2", info->chain_asic_status_t[1], false);
  1446. root = api_add_string(root, "chain_acs3", info->chain_asic_status_t[2], false);
  1447. root = api_add_string(root, "chain_acs4", info->chain_asic_status_t[3], false);
  1448. root = api_add_string(root, "chain_acs5", info->chain_asic_status_t[4], false);
  1449. root = api_add_string(root, "chain_acs6", info->chain_asic_status_t[5], false);
  1450. root = api_add_string(root, "chain_acs7", info->chain_asic_status_t[6], false);
  1451. root = api_add_string(root, "chain_acs8", info->chain_asic_status_t[7], false);
  1452. root = api_add_string(root, "chain_acs9", info->chain_asic_status_t[8], false);
  1453. root = api_add_string(root, "chain_acs10", info->chain_asic_status_t[9], false);
  1454. root = api_add_string(root, "chain_acs11", info->chain_asic_status_t[10], false);
  1455. root = api_add_string(root, "chain_acs12", info->chain_asic_status_t[11], false);
  1456. root = api_add_string(root, "chain_acs13", info->chain_asic_status_t[12], false);
  1457. root = api_add_string(root, "chain_acs14", info->chain_asic_status_t[13], false);
  1458. root = api_add_string(root, "chain_acs15", info->chain_asic_status_t[14], false);
  1459. root = api_add_string(root, "chain_acs16", info->chain_asic_status_t[15], false);
  1460. //root = api_add_int(root, "chain_acs1", &(info->chain_asic_status[0]), false);
  1461. //root = api_add_int(root, "chain_acs2", &(info->chain_asic_status[1]), false);
  1462. //root = api_add_int(root, "chain_acs3", &(info->chain_asic_status[2]), false);
  1463. //root = api_add_int(root, "chain_acs4", &(info->chain_asic_status[3]), false);
  1464. return root;
  1465. }
  1466. static void bitmain_shutdown(struct thr_info *thr)
  1467. {
  1468. do_bitmain_close(thr);
  1469. }
  1470. static
  1471. const char *bitmain_set_baud(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1472. {
  1473. struct bitmain_info *info = proc->device_data;
  1474. const int baud = atoi(newvalue);
  1475. if (!valid_baud(baud))
  1476. return "Invalid baud setting";
  1477. info->baud = baud;
  1478. return NULL;
  1479. }
  1480. static
  1481. const char *bitmain_set_layout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1482. {
  1483. struct bitmain_info *info = proc->device_data;
  1484. char *endptr, *next_field;
  1485. const long int n_chains = strtol(newvalue, &endptr, 0);
  1486. if (endptr == newvalue || n_chains < 1)
  1487. return "Missing chain count";
  1488. long int n_asics = 0;
  1489. if (endptr[0] == ':' || endptr[1] == ',')
  1490. {
  1491. next_field = &endptr[1];
  1492. n_asics = strtol(next_field, &endptr, 0);
  1493. }
  1494. if (n_asics < 1)
  1495. return "Missing ASIC count";
  1496. if (n_asics > BITMAIN_DEFAULT_ASIC_NUM)
  1497. return "ASIC count too high";
  1498. info->chain_num = n_chains;
  1499. info->asic_num = n_asics;
  1500. return NULL;
  1501. }
  1502. static
  1503. const char *bitmain_set_timeout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1504. {
  1505. struct bitmain_info *info = proc->device_data;
  1506. const int timeout = atoi(newvalue);
  1507. if (timeout < 0 || timeout > 0xff)
  1508. return "Invalid timeout setting";
  1509. info->timeout = timeout;
  1510. return NULL;
  1511. }
  1512. static
  1513. const char *bitmain_set_clock(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1514. {
  1515. struct bitmain_info *info = proc->device_data;
  1516. const int freq = atoi(newvalue);
  1517. if (freq < BITMAIN_MIN_FREQUENCY || freq > BITMAIN_MAX_FREQUENCY)
  1518. return "Invalid clock frequency";
  1519. info->frequency = freq;
  1520. sprintf(info->frequency_t, "%d", freq);
  1521. return NULL;
  1522. }
  1523. static
  1524. const char *bitmain_set_reg_data(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1525. {
  1526. struct bitmain_info *info = proc->device_data;
  1527. uint8_t reg_data[4] = {0};
  1528. if (newvalue[0] == 'x')
  1529. ++newvalue;
  1530. size_t nvlen = strlen(newvalue);
  1531. if (nvlen > (sizeof(reg_data) * 2) || !nvlen || nvlen % 2)
  1532. return "reg_data must be a hex string of 2-8 digits (1-4 bytes)";
  1533. if (!hex2bin(reg_data, newvalue, nvlen / 2))
  1534. return "Invalid reg data hex";
  1535. memcpy(info->reg_data, reg_data, sizeof(reg_data));
  1536. return NULL;
  1537. }
  1538. static
  1539. const char *bitmain_set_voltage(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1540. {
  1541. struct bitmain_info *info = proc->device_data;
  1542. uint8_t voltage_data[2] = {0};
  1543. if (newvalue[0] == 'x')
  1544. ++newvalue;
  1545. else
  1546. voltage_usage:
  1547. return "voltage must be 'x' followed by a hex string of 1-4 digits (1-2 bytes)";
  1548. size_t nvlen = strlen(newvalue);
  1549. if (nvlen > (sizeof(voltage_data) * 2) || !nvlen || nvlen % 2)
  1550. goto voltage_usage;
  1551. if (!hex2bin(voltage_data, newvalue, nvlen / 2))
  1552. return "Invalid voltage data hex";
  1553. memcpy(info->voltage, voltage_data, sizeof(voltage_data));
  1554. bin2hex(info->voltage_t, voltage_data, 2);
  1555. info->voltage_t[5] = 0;
  1556. info->voltage_t[4] = info->voltage_t[3];
  1557. info->voltage_t[3] = info->voltage_t[2];
  1558. info->voltage_t[2] = info->voltage_t[1];
  1559. info->voltage_t[1] = '.';
  1560. return NULL;
  1561. }
  1562. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[] = {
  1563. {"baud", bitmain_set_baud, "serial baud rate"},
  1564. {"layout", bitmain_set_layout, "number of chains ':' number of ASICs per chain (eg: 32:8)"},
  1565. {"timeout", bitmain_set_timeout, "timeout"},
  1566. {"clock", bitmain_set_clock, "clock frequency"},
  1567. {"reg_data", bitmain_set_reg_data, "reg_data (eg: x0d82)"},
  1568. {"voltage", bitmain_set_voltage, "voltage (must be specified as 'x' and hex data; eg: x0725)"},
  1569. {NULL},
  1570. };
  1571. struct device_drv bitmain_drv = {
  1572. .dname = "bitmain",
  1573. .name = "BTM",
  1574. .drv_detect = bitmain_detect,
  1575. .thread_prepare = bitmain_prepare,
  1576. .minerloop = minerloop_queue,
  1577. .queue_append = bitmain_queue_append,
  1578. .queue_flush = bitmain_queue_flush,
  1579. .poll = bitmain_poll,
  1580. .get_api_stats = bitmain_api_stats,
  1581. .reinit_device = bitmain_init,
  1582. .thread_shutdown = bitmain_shutdown,
  1583. };