driver-avalon.c 18 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p,
  40. uint8_t miner_num_p)
  41. {
  42. static bool first = true;
  43. uint8_t timeout;
  44. uint8_t asic_num;
  45. uint8_t miner_num;
  46. struct cgpu_info *avalon;
  47. struct avalon_info *info;
  48. if (!at)
  49. return -1;
  50. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  51. return -1;
  52. timeout = timeout_p;
  53. miner_num = miner_num_p;
  54. asic_num = asic_num_p;
  55. if (thr) {
  56. avalon = thr->cgpu;
  57. info = avalon_info[avalon->device_id];
  58. timeout = info->timeout;
  59. miner_num = info->miner_count;
  60. asic_num = info->asic_count;
  61. }
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (reset) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (first && !at->reset) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = 1;
  81. return 0;
  82. }
  83. static inline void avalon_create_task(struct avalon_task *at,
  84. struct work *work)
  85. {
  86. memcpy(at->midstate, work->midstate, 32);
  87. memcpy(at->data, work->data + 64, 12);
  88. }
  89. static int avalon_send_task(int fd, const struct avalon_task *at,
  90. struct thr_info *thr)
  91. {
  92. size_t ret;
  93. int full;
  94. struct timespec p;
  95. uint8_t *buf;
  96. size_t nr_len;
  97. struct cgpu_info *avalon;
  98. struct avalon_info *info;
  99. uint64_t delay = 32000000; /* default 32ms for B19200 */
  100. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  101. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  102. if (!buf)
  103. return AVA_SEND_ERROR;
  104. memcpy(buf, at, AVALON_WRITE_SIZE);
  105. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  106. uint8_t tt = 0;
  107. tt = (buf[0] & 0x0f) << 4;
  108. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  109. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  110. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  111. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  112. buf[0] = tt;
  113. buf[4] = rev8(buf[4]);
  114. #endif
  115. if (opt_debug) {
  116. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  117. hexdump((uint8_t *)buf, nr_len);
  118. }
  119. ret = write(fd, buf, nr_len);
  120. free(buf);
  121. if (unlikely(ret != nr_len))
  122. return AVA_SEND_ERROR;
  123. if (thr) {
  124. avalon = thr->cgpu;
  125. info = avalon_info[avalon->device_id];
  126. delay = AVALON_WRITE_SIZE * 10 * 1000000000ULL;
  127. delay = delay / info->baud;
  128. }
  129. p.tv_sec = 0;
  130. p.tv_nsec = (long)delay + 4000000;
  131. nanosleep(&p, NULL);
  132. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  133. full = avalon_buffer_full(fd);
  134. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  135. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  136. if (full == AVA_BUFFER_EMPTY)
  137. return AVA_SEND_BUFFER_EMPTY;
  138. return AVA_SEND_BUFFER_FULL;
  139. }
  140. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  141. struct thr_info *thr, struct timeval *tv_finish)
  142. {
  143. ssize_t ret = 0;
  144. int rc = 0;
  145. int read_amount = AVALON_READ_SIZE;
  146. bool first = true;
  147. /* Read reply 1 byte at a time to get earliest tv_finish */
  148. while (true) {
  149. ret = read(fd, buf, 1);
  150. if (ret < 0)
  151. return AVA_GETS_ERROR;
  152. if (first && tv_finish != NULL)
  153. gettimeofday(tv_finish, NULL);
  154. if (ret >= read_amount)
  155. return AVA_GETS_OK;
  156. if (ret > 0) {
  157. buf += ret;
  158. read_amount -= ret;
  159. first = false;
  160. continue;
  161. }
  162. rc++;
  163. if (rc >= read_count) {
  164. if (opt_debug) {
  165. applog(LOG_ERR,
  166. "Avalon: No data in %.2f seconds",
  167. (float)rc/(float)TIME_FACTOR);
  168. }
  169. return AVA_GETS_TIMEOUT;
  170. }
  171. if (thr && thr->work_restart) {
  172. if (opt_debug) {
  173. applog(LOG_ERR,
  174. "Avalon: Work restart at %.2f seconds",
  175. (float)(rc)/(float)TIME_FACTOR);
  176. }
  177. return AVA_GETS_RESTART;
  178. }
  179. }
  180. }
  181. static int avalon_get_result(int fd, struct avalon_result *ar,
  182. struct thr_info *thr, struct timeval *tv_finish)
  183. {
  184. struct cgpu_info *avalon;
  185. struct avalon_info *info;
  186. uint8_t result[AVALON_READ_SIZE];
  187. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  188. if (thr) {
  189. avalon = thr->cgpu;
  190. info = avalon_info[avalon->device_id];
  191. read_count = info->read_count;
  192. }
  193. memset(result, 0, AVALON_READ_SIZE);
  194. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  195. if (ret == AVA_GETS_OK) {
  196. if (opt_debug) {
  197. applog(LOG_DEBUG, "Avalon: get:");
  198. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  199. }
  200. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  201. }
  202. return ret;
  203. }
  204. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  205. struct avalon_result *ar, uint32_t *nonce)
  206. {
  207. struct cgpu_info *avalon;
  208. struct avalon_info *info;
  209. int avalon_get_work_count, i;
  210. if (!work)
  211. return -1;
  212. avalon = thr->cgpu;
  213. info = avalon_info[avalon->device_id];
  214. avalon_get_work_count = info->miner_count;
  215. for (i = 0; i < avalon_get_work_count; i++) {
  216. if (work[i] &&
  217. !memcmp(ar->data, work[i]->data + 64, 12) &&
  218. !memcmp(ar->midstate, work[i]->midstate, 32))
  219. break;
  220. }
  221. if (i == avalon_get_work_count)
  222. return -1;
  223. *nonce = ar->nonce;
  224. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  225. *nonce = swab32(*nonce);
  226. #endif
  227. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  228. return i;
  229. }
  230. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  231. uint8_t miner_num_p)
  232. {
  233. struct avalon_task at;
  234. struct avalon_result ar;
  235. uint8_t *buf;
  236. int ret, i;
  237. struct timespec p;
  238. avalon_init_task(NULL,
  239. &at, 1, 0,
  240. AVALON_DEFAULT_FAN_PWM,
  241. timeout_p, asic_num_p, miner_num_p);
  242. ret = avalon_send_task(fd, &at, NULL);
  243. if (ret == AVA_SEND_ERROR)
  244. return 1;
  245. avalon_get_result(fd, &ar, NULL, NULL);
  246. buf = (uint8_t *)&ar;
  247. for (i = 0; i < 11; i++)
  248. if (buf[i] != 0)
  249. break;
  250. /* FIXME: add more avalon info base on return */
  251. if (i != 11) {
  252. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  253. return 1;
  254. }
  255. p.tv_sec = 1;
  256. p.tv_nsec = AVALON_RESET_PITCH;
  257. nanosleep(&p, NULL);
  258. applog(LOG_ERR,
  259. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  260. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  261. applog(LOG_ERR, "Avalon: Reset succeeded");
  262. return 0;
  263. }
  264. static void do_avalon_close(struct thr_info *thr)
  265. {
  266. struct cgpu_info *avalon = thr->cgpu;
  267. avalon_close(avalon->device_fd);
  268. avalon->device_fd = -1;
  269. /* FIXME: we should free the bulk0/1/2 */
  270. }
  271. static void set_timing_mode(struct cgpu_info *avalon)
  272. {
  273. struct avalon_info *info = avalon_info[avalon->device_id];
  274. info->Hs = ((info->timeout * AVALON_HASH_TIME_FACTOR) /
  275. (double)0xffffffff) / info->miner_count;
  276. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  277. info->read_count = (int)(info->fullnonce * TIME_FACTOR) - 1;
  278. }
  279. static void get_options(int this_option_offset, int *baud, int *miner_count,
  280. int *asic_count, int *timeout)
  281. {
  282. char err_buf[BUFSIZ+1];
  283. char buf[BUFSIZ+1];
  284. char *ptr, *comma, *colon, *colon2, *colon3;
  285. size_t max;
  286. int i, tmp;
  287. if (opt_avalon_options == NULL)
  288. buf[0] = '\0';
  289. else {
  290. ptr = opt_avalon_options;
  291. for (i = 0; i < this_option_offset; i++) {
  292. comma = strchr(ptr, ',');
  293. if (comma == NULL)
  294. break;
  295. ptr = comma + 1;
  296. }
  297. comma = strchr(ptr, ',');
  298. if (comma == NULL)
  299. max = strlen(ptr);
  300. else
  301. max = comma - ptr;
  302. if (max > BUFSIZ)
  303. max = BUFSIZ;
  304. strncpy(buf, ptr, max);
  305. buf[max] = '\0';
  306. }
  307. *baud = AVALON_IO_SPEED;
  308. *miner_count = AVALON_DEFAULT_MINER_NUM;
  309. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  310. *timeout = AVALON_DEFAULT_TIMEOUT;
  311. if (!(*buf))
  312. return;
  313. colon = strchr(buf, ':');
  314. if (colon)
  315. *(colon++) = '\0';
  316. tmp = atoi(buf);
  317. switch (tmp) {
  318. case 115200:
  319. *baud = 115200;
  320. break;
  321. case 57600:
  322. *baud = 57600;
  323. break;
  324. case 19200:
  325. *baud = 19200;
  326. break;
  327. default:
  328. sprintf(err_buf,
  329. "Invalid avalon-options for baud (%s) "
  330. "must be 115200, 57600 or 19200", buf);
  331. quit(1, err_buf);
  332. }
  333. if (colon && *colon) {
  334. colon2 = strchr(colon, ':');
  335. if (colon2)
  336. *(colon2++) = '\0';
  337. if (*colon) {
  338. tmp = atoi(colon);
  339. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  340. *miner_count = tmp;
  341. } else {
  342. sprintf(err_buf,
  343. "Invalid avalon-options for "
  344. "miner_count (%s) must be 1 ~ %d",
  345. colon, AVALON_DEFAULT_MINER_NUM);
  346. quit(1, err_buf);
  347. }
  348. }
  349. if (colon2 && *colon2) {
  350. colon3 = strchr(colon2, ':');
  351. if (colon3)
  352. *(colon3++) = '\0';
  353. tmp = atoi(colon2);
  354. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  355. *asic_count = tmp;
  356. else {
  357. sprintf(err_buf,
  358. "Invalid avalon-options for "
  359. "asic_count (%s) must be 1 ~ %d",
  360. colon2, AVALON_DEFAULT_ASIC_NUM);
  361. quit(1, err_buf);
  362. }
  363. if (colon3 && *colon3) {
  364. tmp = atoi(colon3);
  365. if (tmp > 0 && tmp <= 0xff)
  366. *timeout = tmp;
  367. else {
  368. sprintf(err_buf,
  369. "Invalid avalon-options for "
  370. "timeout (%s) must be 1 ~ %d",
  371. colon3, 0xff);
  372. quit(1, err_buf);
  373. }
  374. }
  375. }
  376. }
  377. }
  378. static bool avalon_detect_one(const char *devpath)
  379. {
  380. struct avalon_info *info;
  381. int fd, ret;
  382. int baud, miner_count, asic_count, timeout;
  383. int this_option_offset = ++option_offset;
  384. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  385. &timeout);
  386. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  387. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  388. devpath, baud, miner_count, asic_count, timeout);
  389. fd = avalon_open2(devpath, baud, true);
  390. if (unlikely(fd == -1)) {
  391. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  392. return false;
  393. }
  394. ret = avalon_reset(fd, timeout, asic_count, miner_count);
  395. avalon_close(fd);
  396. if (ret)
  397. return false;
  398. /* We have a real Avalon! */
  399. struct cgpu_info *avalon;
  400. avalon = calloc(1, sizeof(struct cgpu_info));
  401. avalon->api = &avalon_api;
  402. avalon->device_path = strdup(devpath);
  403. avalon->device_fd = -1;
  404. avalon->threads = AVALON_MINER_THREADS;
  405. add_cgpu(avalon);
  406. avalon_info = realloc(avalon_info,
  407. sizeof(struct avalon_info *) *
  408. (total_devices + 1));
  409. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  410. devpath, avalon->device_id);
  411. avalon_info[avalon->device_id] = (struct avalon_info *)
  412. malloc(sizeof(struct avalon_info));
  413. if (unlikely(!(avalon_info[avalon->device_id])))
  414. quit(1, "Failed to malloc avalon_info");
  415. info = avalon_info[avalon->device_id];
  416. memset(info, 0, sizeof(struct avalon_info));
  417. info->baud = baud;
  418. info->miner_count = miner_count;
  419. info->asic_count = asic_count;
  420. info->timeout = timeout;
  421. set_timing_mode(avalon);
  422. return true;
  423. }
  424. static inline void avalon_detect()
  425. {
  426. serial_detect(&avalon_api, avalon_detect_one);
  427. }
  428. static bool avalon_prepare(struct thr_info *thr)
  429. {
  430. struct cgpu_info *avalon = thr->cgpu;
  431. struct timeval now;
  432. int fd, ret;
  433. struct avalon_info *info = avalon_info[avalon->device_id];
  434. avalon->device_fd = -1;
  435. fd = avalon_open(avalon->device_path,
  436. avalon_info[avalon->device_id]->baud);
  437. if (unlikely(fd == -1)) {
  438. applog(LOG_ERR, "Avalon: Failed to open on %s",
  439. avalon->device_path);
  440. return false;
  441. }
  442. ret = avalon_reset(fd, info->timeout, info->asic_count,
  443. info->miner_count);
  444. if (ret)
  445. return false;
  446. avalon->device_fd = fd;
  447. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  448. gettimeofday(&now, NULL);
  449. get_datestamp(avalon->init, &now);
  450. return true;
  451. }
  452. static void avalon_free_work(struct thr_info *thr, struct work **work)
  453. {
  454. struct cgpu_info *avalon;
  455. struct avalon_info *info;
  456. int avalon_get_work_count, i;
  457. if (!work)
  458. return;
  459. avalon = thr->cgpu;
  460. info = avalon_info[avalon->device_id];
  461. avalon_get_work_count = info->miner_count;
  462. for (i = 0; i < avalon_get_work_count; i++)
  463. if (work[i]) {
  464. free_work(work[i]);
  465. work[i] = NULL;
  466. }
  467. }
  468. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  469. __maybe_unused int64_t max_nonce)
  470. {
  471. struct cgpu_info *avalon;
  472. int fd;
  473. int ret;
  474. int full;
  475. struct avalon_info *info;
  476. struct avalon_task at;
  477. struct avalon_result ar;
  478. static struct work *bulk0[AVALON_DEFAULT_MINER_NUM] = {
  479. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  480. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  481. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  482. static struct work *bulk1[AVALON_DEFAULT_MINER_NUM] = {
  483. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  484. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  485. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  486. static struct work *bulk2[AVALON_DEFAULT_MINER_NUM] = {
  487. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  488. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  489. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  490. struct work **work = NULL;
  491. int i, work_i0, work_i1, work_i2;
  492. int avalon_get_work_count;
  493. uint32_t nonce;
  494. int64_t hash_count;
  495. struct timeval tv_start, tv_finish, elapsed;
  496. int curr_hw_errors;
  497. bool was_hw_error;
  498. int64_t estimate_hashes;
  499. avalon = thr->cgpu;
  500. info = avalon_info[avalon->device_id];
  501. avalon_get_work_count = info->miner_count;
  502. if (avalon->device_fd == -1)
  503. if (!avalon_prepare(thr)) {
  504. applog(LOG_ERR, "AVA%i: Comms error",
  505. avalon->device_id);
  506. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  507. /* fail the device if the reopen attempt fails */
  508. return -1;
  509. }
  510. fd = avalon->device_fd;
  511. #ifndef WIN32
  512. tcflush(fd, TCOFLUSH);
  513. #endif
  514. work = bulk_work;
  515. for (i = 0; i < avalon_get_work_count; i++) {
  516. bulk0[i] = bulk1[i];
  517. bulk1[i] = bulk2[i];
  518. bulk2[i] = work[i];
  519. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  520. i, bulk0[i], bulk1[i], bulk2[i]);
  521. }
  522. i = 0;
  523. while (true) {
  524. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  525. avalon_create_task(&at, work[i]);
  526. ret = avalon_send_task(fd, &at, thr);
  527. if (ret == AVA_SEND_ERROR ||
  528. (ret == AVA_SEND_BUFFER_EMPTY &&
  529. (i + 1 == avalon_get_work_count))) {
  530. avalon_free_work(thr, bulk0);
  531. avalon_free_work(thr, bulk1);
  532. avalon_free_work(thr, bulk2);
  533. do_avalon_close(thr);
  534. applog(LOG_ERR, "AVA%i: Comms error",
  535. avalon->device_id);
  536. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  537. sleep(1);
  538. return 0; /* This should never happen */
  539. }
  540. work[i]->blk.nonce = 0xffffffff;
  541. if (ret == AVA_SEND_BUFFER_FULL)
  542. break;
  543. i++;
  544. }
  545. elapsed.tv_sec = elapsed.tv_usec = 0;
  546. gettimeofday(&tv_start, NULL);
  547. while(true) {
  548. full = avalon_buffer_full(fd);
  549. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  550. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  551. if (full == AVA_BUFFER_EMPTY)
  552. break;
  553. work_i0 = work_i1 = work_i2 = -1;
  554. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  555. if (ret == AVA_GETS_ERROR) {
  556. avalon_free_work(thr, bulk0);
  557. avalon_free_work(thr, bulk1);
  558. avalon_free_work(thr, bulk2);
  559. do_avalon_close(thr);
  560. applog(LOG_ERR,
  561. "AVA%i: Comms error", avalon->device_id);
  562. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  563. return 0;
  564. }
  565. /* aborted before becoming idle, get new work */
  566. if (ret == AVA_GETS_TIMEOUT) {
  567. timersub(&tv_finish, &tv_start, &elapsed);
  568. estimate_hashes = ((double)(elapsed.tv_sec) +
  569. ((double)(elapsed.tv_usec)) /
  570. ((double)1000000)) / info->Hs;
  571. /* If Serial-USB delay allowed the full nonce range to
  572. * complete it can't have done more than a full nonce
  573. */
  574. if (unlikely(estimate_hashes > 0xffffffff))
  575. estimate_hashes = 0xffffffff;
  576. applog(LOG_DEBUG,
  577. "Avalon: no nonce = 0x%08llx hashes "
  578. "(%ld.%06lds)",
  579. estimate_hashes, elapsed.tv_sec,
  580. elapsed.tv_usec);
  581. continue;
  582. }
  583. if (ret == AVA_GETS_RESTART) {
  584. avalon_free_work(thr, bulk0);
  585. avalon_free_work(thr, bulk1);
  586. avalon_free_work(thr, bulk2);
  587. continue;
  588. }
  589. avalon->temp = ar.temp0;
  590. work_i0 = avalon_decode_nonce(thr, bulk0, &ar, &nonce);
  591. work_i1 = avalon_decode_nonce(thr, bulk1, &ar, &nonce);
  592. work_i2 = avalon_decode_nonce(thr, bulk2, &ar, &nonce);
  593. curr_hw_errors = avalon->hw_errors;
  594. if (work_i0 >= 0)
  595. submit_nonce(thr, bulk0[work_i0], nonce);
  596. if (work_i1 >= 0)
  597. submit_nonce(thr, bulk1[work_i1], nonce);
  598. if (work_i2 >= 0)
  599. submit_nonce(thr, bulk2[work_i2], nonce);
  600. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  601. /* Force a USB close/reopen on any hw error */
  602. if (was_hw_error)
  603. do_avalon_close(thr);
  604. hash_count = nonce;
  605. hash_count++;
  606. hash_count *= info->asic_count;
  607. }
  608. avalon_free_work(thr, bulk0);
  609. if (opt_debug) {
  610. timersub(&tv_finish, &tv_start, &elapsed);
  611. applog(LOG_DEBUG,
  612. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  613. "(%ld.%06lds)",
  614. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  615. }
  616. applog(LOG_ERR,
  617. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  618. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  619. return hash_count;
  620. }
  621. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  622. {
  623. struct api_data *root = NULL;
  624. struct avalon_info *info = avalon_info[cgpu->device_id];
  625. root = api_add_int(root, "read_count", &(info->read_count), false);
  626. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  627. root = api_add_int(root, "baud", &(info->baud), false);
  628. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  629. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  630. return root;
  631. }
  632. static void avalon_shutdown(struct thr_info *thr)
  633. {
  634. do_avalon_close(thr);
  635. }
  636. struct device_api avalon_api = {
  637. .dname = "avalon",
  638. .name = "AVA",
  639. .api_detect = avalon_detect,
  640. .thread_prepare = avalon_prepare,
  641. .scanhash_queue = avalon_scanhash,
  642. .get_api_stats = avalon_api_stats,
  643. .thread_shutdown = avalon_shutdown,
  644. };