driver-avalon.c 28 KB

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  1. /*
  2. * Copyright 2012-2013 Xiangfu
  3. * Copyright 2012 Luke Dashjr
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "deviceapi.h"
  31. #include "elist.h"
  32. #include "miner.h"
  33. #include "fpgautils.h"
  34. #include "driver-avalon.h"
  35. #include "logging.h"
  36. static int option_offset = -1;
  37. struct avalon_info **avalon_info;
  38. struct device_api avalon_api;
  39. static inline uint8_t rev8(uint8_t d)
  40. {
  41. int i;
  42. uint8_t out = 0;
  43. /* from left to right */
  44. for (i = 0; i < 8; i++)
  45. if (d & (1 << i))
  46. out |= (1 << (7 - i));
  47. return out;
  48. }
  49. static int avalon_init_task(struct avalon_task *at,
  50. uint8_t reset, uint8_t ff, uint8_t fan,
  51. uint8_t timeout, uint8_t asic_num,
  52. uint8_t miner_num, uint8_t nonce_elf,
  53. uint8_t gate_miner, int frequency)
  54. {
  55. uint8_t *buf;
  56. static bool first = true;
  57. if (unlikely(!at))
  58. return -1;
  59. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  60. return -1;
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (unlikely(reset)) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (unlikely(first && !at->reset)) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = nonce_elf;
  80. at->gate_miner_elf = 1;
  81. at->asic_pll = 1;
  82. if (unlikely(gate_miner)) {
  83. at-> gate_miner = 1;
  84. at->asic_pll = 0;
  85. }
  86. buf = (uint8_t *)at;
  87. buf[5] = 0x00;
  88. buf[8] = 0x74;
  89. buf[9] = 0x01;
  90. buf[10] = 0x00;
  91. buf[11] = 0x00;
  92. if (frequency == 256) {
  93. buf[6] = 0x03;
  94. buf[7] = 0x08;
  95. } else if (frequency == 270) {
  96. buf[6] = 0x73;
  97. buf[7] = 0x08;
  98. } else if (frequency == 282) {
  99. buf[6] = 0xd3;
  100. buf[7] = 0x08;
  101. } else if (frequency == 300) {
  102. buf[6] = 0x63;
  103. buf[7] = 0x09;
  104. }
  105. return 0;
  106. }
  107. static inline void avalon_create_task(struct avalon_task *at,
  108. struct work *work)
  109. {
  110. memcpy(at->midstate, work->midstate, 32);
  111. memcpy(at->data, work->data + 64, 12);
  112. }
  113. static int avalon_send_task(int fd, const struct avalon_task *at,
  114. struct cgpu_info *avalon)
  115. {
  116. size_t ret;
  117. int full;
  118. struct timespec p;
  119. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  120. size_t nr_len;
  121. struct avalon_info *info;
  122. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  123. uint32_t nonce_range;
  124. int i;
  125. if (at->nonce_elf)
  126. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  127. else
  128. nr_len = AVALON_WRITE_SIZE;
  129. memcpy(buf, at, AVALON_WRITE_SIZE);
  130. if (at->nonce_elf) {
  131. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  132. for (i = 0; i < at->asic_num; i++) {
  133. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  134. (i * nonce_range & 0xff000000) >> 24;
  135. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  136. (i * nonce_range & 0x00ff0000) >> 16;
  137. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  138. (i * nonce_range & 0x0000ff00) >> 8;
  139. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  140. (i * nonce_range & 0x000000ff) >> 0;
  141. }
  142. }
  143. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  144. uint8_t tt = 0;
  145. tt = (buf[0] & 0x0f) << 4;
  146. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  147. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  148. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  149. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  150. buf[0] = tt;
  151. tt = (buf[4] & 0x0f) << 4;
  152. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  153. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  154. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  155. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  156. buf[4] = tt;
  157. #endif
  158. if (likely(avalon)) {
  159. info = avalon_info[avalon->device_id];
  160. delay = nr_len * 10 * 1000000000ULL;
  161. delay = delay / info->baud;
  162. }
  163. if (at->reset)
  164. nr_len = 1;
  165. if (opt_debug) {
  166. applog(LOG_DEBUG, "Avalon: Sent(%lu):", (unsigned long)nr_len);
  167. hexdump((uint8_t *)buf, nr_len);
  168. }
  169. ret = write(fd, buf, nr_len);
  170. if (unlikely(ret != nr_len))
  171. return AVA_SEND_ERROR;
  172. p.tv_sec = 0;
  173. p.tv_nsec = (long)delay + 4000000;
  174. nanosleep(&p, NULL);
  175. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  176. full = avalon_buffer_full(fd);
  177. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  178. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  179. if (unlikely(full == AVA_BUFFER_FULL))
  180. return AVA_SEND_BUFFER_FULL;
  181. return AVA_SEND_BUFFER_EMPTY;
  182. }
  183. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  184. struct thr_info *thr, struct timeval *tv_finish)
  185. {
  186. ssize_t ret = 0;
  187. int rc = 0;
  188. int read_amount = AVALON_READ_SIZE;
  189. bool first = true;
  190. /* Read reply 1 byte at a time to get earliest tv_finish */
  191. while (true) {
  192. ret = read(fd, buf, 1);
  193. if (ret < 0)
  194. return AVA_GETS_ERROR;
  195. if (first && tv_finish != NULL)
  196. gettimeofday(tv_finish, NULL);
  197. if (ret >= read_amount)
  198. return AVA_GETS_OK;
  199. if (ret > 0) {
  200. buf += ret;
  201. read_amount -= ret;
  202. first = false;
  203. continue;
  204. }
  205. rc++;
  206. if (rc >= read_count) {
  207. if (opt_debug) {
  208. applog(LOG_WARNING,
  209. "Avalon: No data in %.2f seconds",
  210. (float)rc/(float)AVALON_TIME_FACTOR);
  211. }
  212. return AVA_GETS_TIMEOUT;
  213. }
  214. if (thr && thr->work_restart) {
  215. if (opt_debug) {
  216. applog(LOG_WARNING,
  217. "Avalon: Work restart at %.2f seconds",
  218. (float)(rc)/(float)AVALON_TIME_FACTOR);
  219. }
  220. return AVA_GETS_RESTART;
  221. }
  222. }
  223. }
  224. static int avalon_get_result(int fd, struct avalon_result *ar,
  225. struct thr_info *thr, struct timeval *tv_finish)
  226. {
  227. struct cgpu_info *avalon;
  228. struct avalon_info *info;
  229. uint8_t result[AVALON_READ_SIZE];
  230. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  231. if (likely(thr)) {
  232. avalon = thr->cgpu;
  233. info = avalon_info[avalon->device_id];
  234. read_count = info->read_count;
  235. }
  236. memset(result, 0, AVALON_READ_SIZE);
  237. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  238. if (ret == AVA_GETS_OK) {
  239. if (opt_debug) {
  240. applog(LOG_DEBUG, "Avalon: get:");
  241. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  242. }
  243. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  244. }
  245. return ret;
  246. }
  247. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  248. struct avalon_result *ar, uint32_t *nonce)
  249. {
  250. struct cgpu_info *avalon;
  251. struct avalon_info *info;
  252. int avalon_get_work_count, i;
  253. if (unlikely(!work))
  254. return -1;
  255. avalon = thr->cgpu;
  256. info = avalon_info[avalon->device_id];
  257. avalon_get_work_count = info->miner_count;
  258. for (i = 0; i < avalon_get_work_count; i++) {
  259. if (work[i] &&
  260. !memcmp(ar->data, work[i]->data + 64, 12) &&
  261. !memcmp(ar->midstate, work[i]->midstate, 32))
  262. break;
  263. }
  264. if (i == avalon_get_work_count)
  265. return -1;
  266. info->matching_work[i]++;
  267. *nonce = ar->nonce;
  268. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  269. *nonce = swab32(*nonce);
  270. #endif
  271. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  272. info->matching_work[i]);
  273. return i;
  274. }
  275. static int avalon_reset(int fd, struct avalon_result *ar)
  276. {
  277. struct avalon_task at;
  278. uint8_t *buf;
  279. int ret, i = 0;
  280. struct timespec p;
  281. avalon_init_task(&at, 1, 0,
  282. AVALON_DEFAULT_FAN_MAX_PWM,
  283. AVALON_DEFAULT_TIMEOUT,
  284. AVALON_DEFAULT_ASIC_NUM,
  285. AVALON_DEFAULT_MINER_NUM,
  286. 0, 0,
  287. AVALON_DEFAULT_FREQUENCY);
  288. ret = avalon_send_task(fd, &at, NULL);
  289. if (ret == AVA_SEND_ERROR)
  290. return 1;
  291. avalon_get_result(fd, ar, NULL, NULL);
  292. buf = (uint8_t *)ar;
  293. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  294. buf[2] == 0xAA && buf[3] == 0x55) {
  295. for (i = 4; i < 11; i++)
  296. if (buf[i] != 0)
  297. break;
  298. }
  299. if (i != 11) {
  300. applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
  301. " (%d: %02x %02x %02x %02x)",
  302. i, buf[0], buf[1], buf[2], buf[3]);
  303. /* FIXME: return 1; */
  304. }
  305. p.tv_sec = 0;
  306. p.tv_nsec = AVALON_RESET_PITCH;
  307. nanosleep(&p, NULL);
  308. applog(LOG_WARNING, "Avalon: Reset succeeded");
  309. return 0;
  310. }
  311. static void avalon_idle(struct cgpu_info *avalon)
  312. {
  313. int i, ret;
  314. struct avalon_task at;
  315. int fd = avalon->device_fd;
  316. struct avalon_info *info = avalon_info[avalon->device_id];
  317. int avalon_get_work_count = info->miner_count;
  318. i = 0;
  319. while (true) {
  320. avalon_init_task(&at, 0, 0, info->fan_pwm,
  321. info->timeout, info->asic_count,
  322. info->miner_count, 1, 1, info->frequency);
  323. ret = avalon_send_task(fd, &at, avalon);
  324. if (unlikely(ret == AVA_SEND_ERROR ||
  325. (ret == AVA_SEND_BUFFER_EMPTY &&
  326. (i + 1 == avalon_get_work_count * 2)))) {
  327. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  328. return;
  329. }
  330. if (i + 1 == avalon_get_work_count * 2)
  331. break;
  332. if (ret == AVA_SEND_BUFFER_FULL)
  333. break;
  334. i++;
  335. }
  336. applog(LOG_ERR, "Avalon: Goto idle mode");
  337. }
  338. static void get_options(int this_option_offset, int *baud, int *miner_count,
  339. int *asic_count, int *timeout, int *frequency)
  340. {
  341. char buf[BUFSIZ+1];
  342. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  343. size_t max;
  344. int i, tmp;
  345. if (opt_avalon_options == NULL)
  346. buf[0] = '\0';
  347. else {
  348. ptr = opt_avalon_options;
  349. for (i = 0; i < this_option_offset; i++) {
  350. comma = strchr(ptr, ',');
  351. if (comma == NULL)
  352. break;
  353. ptr = comma + 1;
  354. }
  355. comma = strchr(ptr, ',');
  356. if (comma == NULL)
  357. max = strlen(ptr);
  358. else
  359. max = comma - ptr;
  360. if (max > BUFSIZ)
  361. max = BUFSIZ;
  362. strncpy(buf, ptr, max);
  363. buf[max] = '\0';
  364. }
  365. *baud = AVALON_IO_SPEED;
  366. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  367. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  368. *timeout = AVALON_DEFAULT_TIMEOUT;
  369. *frequency = AVALON_DEFAULT_FREQUENCY;
  370. if (!(*buf))
  371. return;
  372. colon = strchr(buf, ':');
  373. if (colon)
  374. *(colon++) = '\0';
  375. tmp = atoi(buf);
  376. switch (tmp) {
  377. case 115200:
  378. *baud = 115200;
  379. break;
  380. case 57600:
  381. *baud = 57600;
  382. break;
  383. case 38400:
  384. *baud = 38400;
  385. break;
  386. case 19200:
  387. *baud = 19200;
  388. break;
  389. default:
  390. quit(1,
  391. "Invalid avalon-options for baud (%s) "
  392. "must be 115200, 57600, 38400 or 19200", buf);
  393. }
  394. if (colon && *colon) {
  395. colon2 = strchr(colon, ':');
  396. if (colon2)
  397. *(colon2++) = '\0';
  398. if (*colon) {
  399. tmp = atoi(colon);
  400. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  401. *miner_count = tmp;
  402. } else {
  403. quit(1,
  404. "Invalid avalon-options for "
  405. "miner_count (%s) must be 1 ~ %d",
  406. colon, AVALON_DEFAULT_MINER_NUM);
  407. }
  408. }
  409. if (colon2 && *colon2) {
  410. colon3 = strchr(colon2, ':');
  411. if (colon3)
  412. *(colon3++) = '\0';
  413. tmp = atoi(colon2);
  414. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  415. *asic_count = tmp;
  416. else {
  417. quit(1,
  418. "Invalid avalon-options for "
  419. "asic_count (%s) must be 1 ~ %d",
  420. colon2, AVALON_DEFAULT_ASIC_NUM);
  421. }
  422. if (colon3 && *colon3) {
  423. colon4 = strchr(colon3, ':');
  424. if (colon4)
  425. *(colon4++) = '\0';
  426. tmp = atoi(colon3);
  427. if (tmp > 0 && tmp <= 0xff)
  428. *timeout = tmp;
  429. else {
  430. quit(1,
  431. "Invalid avalon-options for "
  432. "timeout (%s) must be 1 ~ %d",
  433. colon3, 0xff);
  434. }
  435. if (colon4 && *colon4) {
  436. tmp = atoi(colon4);
  437. switch (tmp) {
  438. case 256:
  439. case 270:
  440. case 282:
  441. case 300:
  442. *frequency = tmp;
  443. break;
  444. default:
  445. quit(1,
  446. "Invalid avalon-options for "
  447. "frequency must be 256/270/282/300");
  448. }
  449. }
  450. }
  451. }
  452. }
  453. }
  454. static bool avalon_detect_one(const char *devpath)
  455. {
  456. struct avalon_info *info;
  457. struct avalon_result ar;
  458. int fd, ret;
  459. int baud, miner_count, asic_count, timeout, frequency = 0;
  460. int this_option_offset = ++option_offset;
  461. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  462. &timeout, &frequency);
  463. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  464. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  465. devpath, baud, miner_count, asic_count, timeout, frequency);
  466. fd = avalon_open2(devpath, baud, true);
  467. if (unlikely(fd == -1)) {
  468. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  469. return false;
  470. }
  471. ret = avalon_reset(fd, &ar);
  472. if (ret) {
  473. ; /* FIXME: I think IT IS avalon and wait on reset;
  474. * avalon_close(fd);
  475. * return false; */
  476. }
  477. /* We have a real Avalon! */
  478. struct cgpu_info *avalon;
  479. avalon = calloc(1, sizeof(struct cgpu_info));
  480. avalon->api = &avalon_api;
  481. avalon->device_path = strdup(devpath);
  482. avalon->device_fd = fd;
  483. avalon->threads = AVALON_MINER_THREADS;
  484. add_cgpu(avalon);
  485. avalon_info = realloc(avalon_info,
  486. sizeof(struct avalon_info *) *
  487. (total_devices + 1));
  488. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  489. devpath, avalon->device_id);
  490. avalon_info[avalon->device_id] = (struct avalon_info *)
  491. malloc(sizeof(struct avalon_info));
  492. if (unlikely(!(avalon_info[avalon->device_id])))
  493. quit(1, "Failed to malloc avalon_info");
  494. info = avalon_info[avalon->device_id];
  495. memset(info, 0, sizeof(struct avalon_info));
  496. info->baud = baud;
  497. info->miner_count = miner_count;
  498. info->asic_count = asic_count;
  499. info->timeout = timeout;
  500. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  501. AVALON_TIME_FACTOR) / (float)info->miner_count;
  502. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  503. info->temp_max = 0;
  504. /* This is for check the temp/fan every 3~4s */
  505. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  506. if (info->temp_history_count <= 0)
  507. info->temp_history_count = 1;
  508. info->temp_history_index = 0;
  509. info->temp_sum = 0;
  510. info->temp_old = 0;
  511. info->frequency = frequency;
  512. /* Set asic to idle mode after detect */
  513. avalon_idle(avalon);
  514. avalon->device_fd = -1;
  515. avalon_close(fd);
  516. return true;
  517. }
  518. static inline void avalon_detect()
  519. {
  520. serial_detect(&avalon_api, avalon_detect_one);
  521. }
  522. static void avalon_init(struct cgpu_info *avalon)
  523. {
  524. struct avalon_result ar;
  525. int fd, ret;
  526. avalon->device_fd = -1;
  527. fd = avalon_open(avalon->device_path,
  528. avalon_info[avalon->device_id]->baud);
  529. if (unlikely(fd == -1)) {
  530. applog(LOG_ERR, "Avalon: Failed to open on %s",
  531. avalon->device_path);
  532. return;
  533. }
  534. ret = avalon_reset(fd, &ar);
  535. if (ret) {
  536. avalon_close(fd);
  537. return;
  538. }
  539. avalon->device_fd = fd;
  540. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  541. return;
  542. }
  543. static bool avalon_prepare(struct thr_info *thr)
  544. {
  545. struct cgpu_info *avalon = thr->cgpu;
  546. struct timeval now;
  547. avalon_init(avalon);
  548. if (avalon->device_fd == -1)
  549. return false;
  550. gettimeofday(&now, NULL);
  551. get_datestamp(avalon->init, &now);
  552. avalon->status = LIFE_INIT2;
  553. return true;
  554. }
  555. static void avalon_free_work(struct thr_info *thr, struct work **work)
  556. {
  557. struct cgpu_info *avalon;
  558. struct avalon_info *info;
  559. int i;
  560. if (unlikely(!work))
  561. return;
  562. avalon = thr->cgpu;
  563. info = avalon_info[avalon->device_id];
  564. for (i = 0; i < info->miner_count; i++)
  565. if (likely(work[i])) {
  566. free_work(work[i]);
  567. work[i] = NULL;
  568. }
  569. }
  570. static void do_avalon_close(struct thr_info *thr)
  571. {
  572. struct avalon_result ar;
  573. struct cgpu_info *avalon = thr->cgpu;
  574. struct avalon_info *info = avalon_info[avalon->device_id];
  575. nmsleep(1000);
  576. avalon_reset(avalon->device_fd, &ar);
  577. avalon_idle(avalon);
  578. avalon_close(avalon->device_fd);
  579. avalon->device_fd = -1;
  580. info->no_matching_work = 0;
  581. avalon_free_work(thr, info->bulk0);
  582. avalon_free_work(thr, info->bulk1);
  583. avalon_free_work(thr, info->bulk2);
  584. avalon_free_work(thr, info->bulk3);
  585. }
  586. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  587. {
  588. int max;
  589. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  590. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  591. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  592. info->temp0 = ar->temp0;
  593. info->temp1 = ar->temp1;
  594. info->temp2 = ar->temp2;
  595. if (ar->temp0 & 0x80) {
  596. ar->temp0 &= 0x7f;
  597. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  598. }
  599. if (ar->temp1 & 0x80) {
  600. ar->temp1 &= 0x7f;
  601. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  602. }
  603. if (ar->temp2 & 0x80) {
  604. ar->temp2 &= 0x7f;
  605. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  606. }
  607. *temp_avg = info->temp2;
  608. max = info->temp_max;
  609. if (info->temp0 > max)
  610. max = info->temp0;
  611. if (info->temp1 > max)
  612. max = info->temp1;
  613. if (info->temp2 > max)
  614. max = info->temp2;
  615. if (max >= 100) { /* FIXME: fix the root cause on fpga controller firmware */
  616. if (opt_debug) {
  617. applog(LOG_DEBUG, "Avalon: temp_max: %d", max);
  618. hexdump((uint8_t *)ar, AVALON_READ_SIZE);
  619. }
  620. return;
  621. }
  622. info->temp_max = max;
  623. }
  624. static inline void adjust_fan(struct avalon_info *info)
  625. {
  626. int temp_new;
  627. temp_new = info->temp_sum / info->temp_history_count;
  628. if (temp_new < 35) {
  629. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  630. info->temp_old = temp_new;
  631. } else if (temp_new > 55) {
  632. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  633. info->temp_old = temp_new;
  634. } else if (abs(temp_new - info->temp_old) >= 2) {
  635. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  636. info->temp_old = temp_new;
  637. }
  638. }
  639. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  640. __maybe_unused int64_t max_nonce)
  641. {
  642. struct cgpu_info *avalon;
  643. int fd, ret, full;
  644. struct avalon_info *info;
  645. struct avalon_task at;
  646. struct avalon_result ar;
  647. int i, work_i0, work_i1, work_i2, work_i3;
  648. int avalon_get_work_count;
  649. struct timeval tv_start, tv_finish, elapsed;
  650. uint32_t nonce;
  651. int64_t hash_count;
  652. static int first_try = 0;
  653. int result_count, result_wrong;
  654. avalon = thr->cgpu;
  655. info = avalon_info[avalon->device_id];
  656. avalon_get_work_count = info->miner_count;
  657. if (unlikely(avalon->device_fd == -1))
  658. if (!avalon_prepare(thr)) {
  659. applog(LOG_ERR, "AVA%i: Comms error(open)",
  660. avalon->device_id);
  661. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  662. /* fail the device if the reopen attempt fails */
  663. return -1;
  664. }
  665. fd = avalon->device_fd;
  666. #ifndef WIN32
  667. tcflush(fd, TCOFLUSH);
  668. #endif
  669. for (i = 0; i < avalon_get_work_count; i++) {
  670. info->bulk0[i] = info->bulk1[i];
  671. info->bulk1[i] = info->bulk2[i];
  672. info->bulk2[i] = info->bulk3[i];
  673. info->bulk3[i] = work[i];
  674. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  675. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  676. }
  677. i = 0;
  678. while (true) {
  679. avalon_init_task(&at, 0, 0, info->fan_pwm,
  680. info->timeout, info->asic_count,
  681. info->miner_count, 1, 0, info->frequency);
  682. avalon_create_task(&at, work[i]);
  683. ret = avalon_send_task(fd, &at, avalon);
  684. if (unlikely(ret == AVA_SEND_ERROR ||
  685. (ret == AVA_SEND_BUFFER_EMPTY &&
  686. (i + 1 == avalon_get_work_count) &&
  687. first_try))) {
  688. avalon_free_work(thr, info->bulk0);
  689. avalon_free_work(thr, info->bulk1);
  690. avalon_free_work(thr, info->bulk2);
  691. avalon_free_work(thr, info->bulk3);
  692. do_avalon_close(thr);
  693. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  694. avalon->device_id);
  695. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  696. first_try = 0;
  697. nmsleep(1000);
  698. return 0; /* This should never happen */
  699. }
  700. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  701. first_try = 1;
  702. return 0xffffffff;
  703. }
  704. work[i]->blk.nonce = 0xffffffff;
  705. if (ret == AVA_SEND_BUFFER_FULL)
  706. break;
  707. i++;
  708. }
  709. if (unlikely(first_try))
  710. first_try = 0;
  711. elapsed.tv_sec = elapsed.tv_usec = 0;
  712. gettimeofday(&tv_start, NULL);
  713. result_count = 0;
  714. result_wrong = 0;
  715. hash_count = 0;
  716. while (true) {
  717. work_i0 = work_i1 = work_i2 = work_i3 = -1;
  718. full = avalon_buffer_full(fd);
  719. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  720. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  721. if (unlikely(full == AVA_BUFFER_EMPTY))
  722. break;
  723. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  724. if (unlikely(ret == AVA_GETS_ERROR)) {
  725. avalon_free_work(thr, info->bulk0);
  726. avalon_free_work(thr, info->bulk1);
  727. avalon_free_work(thr, info->bulk2);
  728. avalon_free_work(thr, info->bulk3);
  729. do_avalon_close(thr);
  730. applog(LOG_ERR,
  731. "AVA%i: Comms error(read)", avalon->device_id);
  732. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  733. return 0;
  734. }
  735. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  736. timersub(&tv_finish, &tv_start, &elapsed);
  737. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  738. (long)elapsed.tv_sec, (long)elapsed.tv_usec);
  739. continue;
  740. }
  741. if (unlikely(ret == AVA_GETS_RESTART)) {
  742. avalon_free_work(thr, info->bulk0);
  743. avalon_free_work(thr, info->bulk1);
  744. avalon_free_work(thr, info->bulk2);
  745. avalon_free_work(thr, info->bulk3);
  746. continue;
  747. }
  748. result_count++;
  749. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  750. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  751. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  752. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  753. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  754. info->no_matching_work++;
  755. result_wrong++;
  756. if (opt_debug) {
  757. timersub(&tv_finish, &tv_start, &elapsed);
  758. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  759. " (%ld.%06lds)", info->no_matching_work,
  760. (long)elapsed.tv_sec, (long)elapsed.tv_usec);
  761. }
  762. continue;
  763. }
  764. if (work_i0 >= 0)
  765. submit_nonce(thr, info->bulk0[work_i0], nonce);
  766. if (work_i1 >= 0)
  767. submit_nonce(thr, info->bulk1[work_i1], nonce);
  768. if (work_i2 >= 0)
  769. submit_nonce(thr, info->bulk2[work_i2], nonce);
  770. if (work_i3 >= 0)
  771. submit_nonce(thr, info->bulk3[work_i3], nonce);
  772. hash_count += nonce;
  773. if (opt_debug) {
  774. timersub(&tv_finish, &tv_start, &elapsed);
  775. applog(LOG_DEBUG,
  776. "Avalon: nonce = 0x%08"PRIx32" = 0x%08"PRIx64" hashes "
  777. "(%ld.%06lds)", nonce, (uint64_t)hash_count,
  778. (long)elapsed.tv_sec, (long)elapsed.tv_usec);
  779. }
  780. }
  781. if (result_count == result_wrong) {
  782. /* This mean FPGA controller give all wrong result
  783. * try to reset the Avalon */
  784. avalon_free_work(thr, info->bulk0);
  785. avalon_free_work(thr, info->bulk1);
  786. avalon_free_work(thr, info->bulk2);
  787. avalon_free_work(thr, info->bulk3);
  788. do_avalon_close(thr);
  789. applog(LOG_ERR,
  790. "AVA%i: FPGA controller mess up", avalon->device_id);
  791. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  792. return 0;
  793. }
  794. avalon_free_work(thr, info->bulk0);
  795. record_temp_fan(info, &ar, &(avalon->temp));
  796. applog(LOG_INFO,
  797. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  798. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  799. info->fan0, info->fan1, info->fan2,
  800. info->temp0, info->temp1, info->temp2, info->temp_max);
  801. info->temp_history_index++;
  802. info->temp_sum += info->temp2;
  803. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  804. info->temp_history_index, info->temp_history_count, info->temp_old);
  805. if (info->temp_history_index == info->temp_history_count) {
  806. adjust_fan(info);
  807. info->temp_history_index = 0;
  808. info->temp_sum = 0;
  809. }
  810. /*
  811. * FIXME: Each work split to 10 pieces, each piece send to a
  812. * asic(256MHs). one work can be mulit-nonce back. it is not
  813. * easy calculate correct hash on such situation. so I simplely
  814. * add each nonce to hash_count. base on Utility/m hash_count*2
  815. * give a very good result.
  816. *
  817. * Any patch will be great.
  818. */
  819. return (hash_count * 2);
  820. }
  821. // minerloop_scanhash hacked to handle Avalon's many processors
  822. static
  823. void minerloop_avalon(struct thr_info *mythr)
  824. {
  825. const int thr_id = mythr->id;
  826. struct cgpu_info *cgpu = mythr->cgpu;
  827. const struct device_api *api = cgpu->api;
  828. struct timeval tv_start, tv_end;
  829. struct timeval tv_hashes;
  830. uint32_t max_nonce = api->can_limit_work ? api->can_limit_work(mythr) : 0xffffffff;
  831. int64_t hashes;
  832. struct avalon_info *info = avalon_info[cgpu->device_id];
  833. int i;
  834. int avalon_get_work_count = info->miner_count;
  835. struct work **work = calloc(1,
  836. avalon_get_work_count * sizeof(struct work *));
  837. if (!work)
  838. quit(1, "Faile on Avalon calloc");
  839. const bool primary = (!mythr->device_thread) || mythr->primary_thread;
  840. while (1) {
  841. mythr->work_restart = false;
  842. for (i = 0; i < avalon_get_work_count; i++)
  843. request_work(mythr);
  844. for (i = 0; i < avalon_get_work_count; i++) {
  845. work[i] = get_work(mythr);
  846. work[i]->blk.nonce = 0;
  847. }
  848. for (i = 0; i < avalon_get_work_count; i++) {
  849. if (api->prepare_work && !api->prepare_work(mythr, work[i])) {
  850. applog(LOG_ERR, "work prepare failed, exiting "
  851. "mining thread %d", thr_id);
  852. break;
  853. }
  854. gettimeofday(&(work[i]->tv_work_start), NULL);
  855. }
  856. do {
  857. thread_reportin(mythr);
  858. gettimeofday(&tv_start, NULL);
  859. hashes = api->scanhash_queue(mythr, work, max_nonce);
  860. gettimeofday(&tv_end, NULL);
  861. thread_reportin(mythr);
  862. timersub(&tv_end, &tv_start, &tv_hashes);
  863. if (!hashes_done(mythr, hashes, &tv_hashes, api->can_limit_work ? &max_nonce : NULL))
  864. goto disabled;
  865. if (unlikely(mythr->work_restart)) {
  866. /* Apart from device_thread 0, we stagger the
  867. * starting of every next thread to try and get
  868. * all devices busy before worrying about
  869. * getting work for their extra threads */
  870. if (!primary) {
  871. struct timespec rgtp;
  872. rgtp.tv_sec = 0;
  873. rgtp.tv_nsec = 250 * mythr->device_thread * 1000000;
  874. nanosleep(&rgtp, NULL);
  875. }
  876. break;
  877. }
  878. if (unlikely(mythr->pause || cgpu->deven != DEV_ENABLED))
  879. disabled:
  880. mt_disable(mythr);
  881. } while (false);
  882. }
  883. free(work);
  884. }
  885. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  886. {
  887. struct api_data *root = NULL;
  888. struct avalon_info *info = avalon_info[cgpu->device_id];
  889. root = api_add_int(root, "baud", &(info->baud), false);
  890. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  891. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  892. root = api_add_int(root, "read_count", &(info->read_count), false);
  893. root = api_add_int(root, "timeout", &(info->timeout), false);
  894. root = api_add_int(root, "frequency", &(info->frequency), false);
  895. root = api_add_int(root, "fan1", &(info->fan0), false);
  896. root = api_add_int(root, "fan2", &(info->fan1), false);
  897. root = api_add_int(root, "fan3", &(info->fan2), false);
  898. root = api_add_int(root, "temp1", &(info->temp0), false);
  899. root = api_add_int(root, "temp2", &(info->temp1), false);
  900. root = api_add_int(root, "temp3", &(info->temp2), false);
  901. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  902. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  903. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  904. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  905. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  906. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  907. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  908. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  909. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  910. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  911. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  912. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  913. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  914. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  915. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  916. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  917. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  918. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  919. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  920. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  921. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  922. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  923. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  924. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  925. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  926. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  927. return root;
  928. }
  929. static void avalon_shutdown(struct thr_info *thr)
  930. {
  931. do_avalon_close(thr);
  932. }
  933. struct device_api avalon_api = {
  934. .dname = "avalon",
  935. .name = "AVA",
  936. .api_detect = avalon_detect,
  937. .thread_prepare = avalon_prepare,
  938. .minerloop = minerloop_avalon,
  939. .scanhash_queue = avalon_scanhash,
  940. .get_api_stats = avalon_api_stats,
  941. .reinit_device = avalon_init,
  942. .thread_shutdown = avalon_shutdown,
  943. };