driver-avalon.c 23 KB

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  1. /*
  2. * Copyright 2012 Luke Dashjr
  3. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. /*
  12. * Those code should be works fine with V2 and V3 bitstream of Avalon.
  13. * Operation:
  14. * No detection implement.
  15. * Input: 64B = 32B midstate + 20B fill bytes + last 12 bytes of block head.
  16. * Return: send back 32bits immediately when Avalon found a valid nonce.
  17. * no query protocol implemented here, if no data send back in ~11.3
  18. * seconds (full cover time on 32bit nonce range by 380MH/s speed)
  19. * just send another work.
  20. * Notice:
  21. * 1. Avalon will start calculate when you push a work to them, even they
  22. * are busy.
  23. * 2. The 2 FPGAs on Avalon will distribute the job, one will calculate the
  24. * 0 ~ 7FFFFFFF, another one will cover the 80000000 ~ FFFFFFFF.
  25. * 3. It's possible for 2 FPGAs both find valid nonce in the meantime, the 2
  26. * valid nonce will all be send back.
  27. * 4. Avalon will stop work when: a valid nonce has been found or 32 bits
  28. * nonce range is completely calculated.
  29. */
  30. #include "config.h"
  31. #include <limits.h>
  32. #include <pthread.h>
  33. #include <stdio.h>
  34. #include <sys/time.h>
  35. #include <sys/types.h>
  36. #include <dirent.h>
  37. #include <unistd.h>
  38. #ifndef WIN32
  39. #include <termios.h>
  40. #include <sys/stat.h>
  41. #include <fcntl.h>
  42. #ifndef O_CLOEXEC
  43. #define O_CLOEXEC 0
  44. #endif
  45. #else
  46. #include <windows.h>
  47. #include <io.h>
  48. #endif
  49. #include "elist.h"
  50. #include "miner.h"
  51. #include "fpgautils.h"
  52. #include "driver-avalon.h"
  53. static struct timeval history_sec = { HISTORY_SEC, 0 };
  54. static const char *MODE_DEFAULT_STR = "default";
  55. static const char *MODE_SHORT_STR = "short";
  56. static const char *MODE_LONG_STR = "long";
  57. static const char *MODE_VALUE_STR = "value";
  58. static const char *MODE_UNKNOWN_STR = "unknown";
  59. // One for each possible device
  60. static struct AVALON_INFO **avalon_info;
  61. // Looking for options in --avalon-timing and --avalon-options:
  62. //
  63. // Code increments this each time we start to look at a device
  64. // However, this means that if other devices are checked by
  65. // the Avalon code (e.g. BFL) they will count in the option offset
  66. //
  67. // This, however, is deterministic so that's OK
  68. //
  69. // If we were to increment after successfully finding an Avalon
  70. // that would be random since an Avalon may fail and thus we'd
  71. // not be able to predict the option order
  72. //
  73. // This also assumes that serial_detect() checks them sequentially
  74. // and in the order specified on the command line
  75. //
  76. static int option_offset = -1;
  77. struct device_api avalon_api;
  78. static void rev(uint8_t *s, size_t l)
  79. {
  80. size_t i, j;
  81. uint8_t t;
  82. for (i = 0, j = l - 1; i < j; i++, j--) {
  83. t = s[i];
  84. s[i] = s[j];
  85. s[j] = t;
  86. }
  87. }
  88. static inline void avalon_create_task(uint8_t *ob_bin, struct work *work)
  89. {
  90. memset(ob_bin, 0, sizeof(ob_bin));
  91. memcpy(ob_bin, work->midstate, 32);
  92. memcpy(ob_bin + 52, work->data + 64, 12);
  93. rev(ob_bin, 32);
  94. rev(ob_bin + 52, 12);
  95. }
  96. static int avalon_gets(uint8_t *buf, int fd, struct timeval *tv_finish,
  97. struct thr_info *thr, int read_count)
  98. {
  99. ssize_t ret = 0;
  100. int rc = 0;
  101. int read_amount = AVALON_READ_SIZE;
  102. bool first = true;
  103. /* FIXME: we should set RTS to 0 and CTS to be 1, before read? */
  104. int done = avalon_task_done(fd);
  105. if (opt_debug)
  106. applog(LOG_DEBUG, "Avalon bulk task statue: %d", done);
  107. if (done) {
  108. /* TODO: return here. and tell avalon all task are done */
  109. }
  110. // Read reply 1 byte at a time to get earliest tv_finish
  111. while (true) {
  112. ret = read(fd, buf, 1);
  113. if (ret < 0)
  114. return AVA_GETS_ERROR;
  115. if (first)
  116. gettimeofday(tv_finish, NULL);
  117. if (ret >= read_amount)
  118. return AVA_GETS_OK;
  119. if (ret > 0) {
  120. buf += ret;
  121. read_amount -= ret;
  122. first = false;
  123. continue;
  124. }
  125. rc++;
  126. if (rc >= read_count) {
  127. if (opt_debug) {
  128. applog(LOG_DEBUG,
  129. "Avalon Read: No data in %.2f seconds",
  130. (float)rc/(float)TIME_FACTOR);
  131. }
  132. return AVA_GETS_TIMEOUT;
  133. }
  134. if (thr && thr->work_restart) {
  135. if (opt_debug) {
  136. applog(LOG_DEBUG,
  137. "Avalon Read: Work restart at %.2f seconds",
  138. (float)(rc)/(float)TIME_FACTOR);
  139. }
  140. return AVA_GETS_RESTART;
  141. }
  142. }
  143. }
  144. static int avalon_read_work(uint8_t *nonce_bin, int fd,
  145. struct timeval *tv_finish, struct thr_info *thr)
  146. {
  147. /* TODO: create a globle buffer match that buffer retrun the work*/
  148. struct cgpu_info *avalon = thr->cgpu;
  149. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  150. int ret;
  151. memset(nonce_bin, 0, AVALON_READ_SIZE);
  152. ret = avalon_gets(nonce_bin, fd, tv_finish, thr, info->read_count);
  153. return ret;
  154. }
  155. static int avalon_submit_nonce(uint8_t *ob_bin)
  156. {
  157. return 0;
  158. }
  159. static int avalon_send_task(int fd, const void *buf, size_t bufLen)
  160. {
  161. size_t ret;
  162. /* FIXME: we should set RTS to 1 and wait CTS became 1, before write? */
  163. int empty = avalon_buffer_empty(fd);
  164. if (empty < 0) {
  165. /* FIXME: ERROR */
  166. }
  167. if (!empty) {
  168. /* FIXME: the buffer was full */
  169. }
  170. ret = write(fd, buf, bufLen);
  171. if (unlikely(ret != bufLen))
  172. return 1;
  173. /* From the document. avalon needs some time space between two write */
  174. struct timespec p;
  175. p.tv_sec = 0;
  176. p.tv_nsec = 5 * 1000;
  177. nanosleep(&p, NULL);
  178. return 0;
  179. }
  180. #define avalon_close(fd) close(fd)
  181. static void do_avalon_close(struct thr_info *thr)
  182. {
  183. struct cgpu_info *avalon = thr->cgpu;
  184. avalon_close(avalon->device_fd);
  185. avalon->device_fd = -1;
  186. }
  187. static const char *timing_mode_str(enum timing_mode timing_mode)
  188. {
  189. switch(timing_mode) {
  190. case MODE_DEFAULT:
  191. return MODE_DEFAULT_STR;
  192. case MODE_SHORT:
  193. return MODE_SHORT_STR;
  194. case MODE_LONG:
  195. return MODE_LONG_STR;
  196. case MODE_VALUE:
  197. return MODE_VALUE_STR;
  198. default:
  199. return MODE_UNKNOWN_STR;
  200. }
  201. }
  202. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  203. {
  204. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  205. double Hs;
  206. char buf[BUFSIZ+1];
  207. char *ptr, *comma, *eq;
  208. size_t max;
  209. int i;
  210. if (opt_icarus_timing == NULL)
  211. buf[0] = '\0';
  212. else {
  213. ptr = opt_icarus_timing;
  214. for (i = 0; i < this_option_offset; i++) {
  215. comma = strchr(ptr, ',');
  216. if (comma == NULL)
  217. break;
  218. ptr = comma + 1;
  219. }
  220. comma = strchr(ptr, ',');
  221. if (comma == NULL)
  222. max = strlen(ptr);
  223. else
  224. max = comma - ptr;
  225. if (max > BUFSIZ)
  226. max = BUFSIZ;
  227. strncpy(buf, ptr, max);
  228. buf[max] = '\0';
  229. }
  230. info->Hs = 0;
  231. info->read_count = 0;
  232. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  233. info->Hs = AVALON_REV3_HASH_TIME;
  234. info->read_count = AVALON_READ_COUNT_TIMING;
  235. info->timing_mode = MODE_SHORT;
  236. info->do_avalon_timing = true;
  237. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  238. info->Hs = AVALON_REV3_HASH_TIME;
  239. info->read_count = AVALON_READ_COUNT_TIMING;
  240. info->timing_mode = MODE_LONG;
  241. info->do_avalon_timing = true;
  242. } else if ((Hs = atof(buf)) != 0) {
  243. info->Hs = Hs / NANOSEC;
  244. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  245. if ((eq = strchr(buf, '=')) != NULL)
  246. info->read_count = atoi(eq+1);
  247. if (info->read_count < 1)
  248. info->read_count =
  249. (int)(info->fullnonce * TIME_FACTOR) - 1;
  250. if (unlikely(info->read_count < 1))
  251. info->read_count = 1;
  252. info->timing_mode = MODE_VALUE;
  253. info->do_avalon_timing = false;
  254. } else {
  255. // Anything else in buf just uses DEFAULT mode
  256. info->Hs = AVALON_REV3_HASH_TIME;
  257. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  258. if ((eq = strchr(buf, '=')) != NULL)
  259. info->read_count = atoi(eq+1);
  260. if (info->read_count < 1)
  261. info->read_count =
  262. (int)(info->fullnonce * TIME_FACTOR) - 1;
  263. info->timing_mode = MODE_DEFAULT;
  264. info->do_avalon_timing = false;
  265. }
  266. info->min_data_count = MIN_DATA_COUNT;
  267. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  268. avalon->device_id, timing_mode_str(info->timing_mode),
  269. info->read_count, info->Hs);
  270. }
  271. static uint32_t mask(int work_division)
  272. {
  273. char err_buf[BUFSIZ+1];
  274. uint32_t nonce_mask = 0x7fffffff;
  275. // yes we can calculate these,
  276. // but this way it's easy to see what they are
  277. switch (work_division) {
  278. case 1:
  279. nonce_mask = 0xffffffff;
  280. break;
  281. case 2:
  282. nonce_mask = 0x7fffffff;
  283. break;
  284. case 4:
  285. nonce_mask = 0x3fffffff;
  286. break;
  287. case 8:
  288. nonce_mask = 0x1fffffff;
  289. break;
  290. default:
  291. sprintf(err_buf,
  292. "Invalid2 avalon-options for work_division (%d)"
  293. " must be 1, 2, 4 or 8", work_division);
  294. quit(1, err_buf);
  295. }
  296. return nonce_mask;
  297. }
  298. static void get_options(int this_option_offset, int *baud, int *work_division,
  299. int *asic_count)
  300. {
  301. char err_buf[BUFSIZ+1];
  302. char buf[BUFSIZ+1];
  303. char *ptr, *comma, *colon, *colon2;
  304. size_t max;
  305. int i, tmp;
  306. if (opt_icarus_options == NULL)
  307. buf[0] = '\0';
  308. else {
  309. ptr = opt_icarus_options;
  310. for (i = 0; i < this_option_offset; i++) {
  311. comma = strchr(ptr, ',');
  312. if (comma == NULL)
  313. break;
  314. ptr = comma + 1;
  315. }
  316. comma = strchr(ptr, ',');
  317. if (comma == NULL)
  318. max = strlen(ptr);
  319. else
  320. max = comma - ptr;
  321. if (max > BUFSIZ)
  322. max = BUFSIZ;
  323. strncpy(buf, ptr, max);
  324. buf[max] = '\0';
  325. }
  326. *baud = AVALON_IO_SPEED;
  327. *work_division = 2;
  328. *asic_count = 2;
  329. if (*buf) {
  330. colon = strchr(buf, ':');
  331. if (colon)
  332. *(colon++) = '\0';
  333. if (*buf) {
  334. tmp = atoi(buf);
  335. switch (tmp) {
  336. case 115200:
  337. *baud = 115200;
  338. break;
  339. case 57600:
  340. *baud = 57600;
  341. break;
  342. default:
  343. sprintf(err_buf,
  344. "Invalid avalon-options for baud (%s) "
  345. "must be 115200 or 57600", buf);
  346. quit(1, err_buf);
  347. }
  348. }
  349. if (colon && *colon) {
  350. colon2 = strchr(colon, ':');
  351. if (colon2)
  352. *(colon2++) = '\0';
  353. if (*colon) {
  354. tmp = atoi(colon);
  355. if (tmp == 1 || tmp == 2 ||
  356. tmp == 4 || tmp == 8) {
  357. *work_division = tmp;
  358. // default to the same
  359. *asic_count = tmp;
  360. } else {
  361. sprintf(err_buf,
  362. "Invalid avalon-options for "
  363. "work_division (%s) must be 1,"
  364. " 2, 4 or 8", colon);
  365. quit(1, err_buf);
  366. }
  367. }
  368. if (colon2 && *colon2) {
  369. tmp = atoi(colon2);
  370. if (tmp > 0 && tmp <= *work_division)
  371. *asic_count = tmp;
  372. else {
  373. sprintf(err_buf,
  374. "Invalid avalon-options for "
  375. "asic_count (%s) must be >0 "
  376. "and <=work_division (%d)",
  377. colon2, *work_division);
  378. quit(1, err_buf);
  379. }
  380. }
  381. }
  382. }
  383. }
  384. static bool avalon_detect_one(const char *devpath)
  385. {
  386. int this_option_offset = ++option_offset;
  387. struct AVALON_INFO *info;
  388. struct timeval tv_start, tv_finish;
  389. int fd;
  390. // Block 171874 nonce = (0xa2870100) = 0x000187a2
  391. // N.B. golden_ob MUST take less time to calculate
  392. // than the timeout set in avalon_open()
  393. // This one takes ~0.53ms on Rev3 Avalon
  394. const char golden_ob[] =
  395. "4679ba4ec99876bf4bfe086082b40025"
  396. "4df6c356451471139a3afa71e48f544a"
  397. "00000000000000000000000000000000"
  398. "0000000087320b1a1426674f2fa722ce";
  399. const char golden_nonce[] = "000187a2";
  400. const uint32_t golden_nonce_val = 0x000187a2;
  401. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  402. char *nonce_hex;
  403. int baud, work_division, asic_count;
  404. get_options(this_option_offset, &baud, &work_division, &asic_count);
  405. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  406. fd = avalon_open2(devpath, baud, true);
  407. if (unlikely(fd == -1)) {
  408. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  409. return false;
  410. }
  411. hex2bin(ob_bin, golden_ob, sizeof(ob_bin));
  412. avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  413. gettimeofday(&tv_start, NULL);
  414. memset(nonce_bin, 0, sizeof(nonce_bin));
  415. avalon_gets(nonce_bin, fd, &tv_finish, NULL, 1);
  416. avalon_close(fd);
  417. nonce_hex = bin2hex(nonce_bin, sizeof(nonce_bin));
  418. if (strncmp(nonce_hex, golden_nonce, 8)) {
  419. applog(LOG_ERR,
  420. "Avalon Detect: "
  421. "Test failed at %s: get %s, should: %s",
  422. devpath, nonce_hex, golden_nonce);
  423. free(nonce_hex);
  424. return false;
  425. }
  426. applog(LOG_DEBUG,
  427. "Avalon Detect: "
  428. "Test succeeded at %s: got %s",
  429. devpath, nonce_hex);
  430. free(nonce_hex);
  431. /* We have a real Avalon! */
  432. struct cgpu_info *avalon;
  433. avalon = calloc(1, sizeof(struct cgpu_info));
  434. avalon->api = &avalon_api;
  435. avalon->device_path = strdup(devpath);
  436. avalon->device_fd = -1;
  437. avalon->threads = AVALON_MINER_THREADS;
  438. add_cgpu(avalon);
  439. avalon_info = realloc(avalon_info,
  440. sizeof(struct AVALON_INFO *) *
  441. (total_devices + 1));
  442. applog(LOG_INFO, "Found Avalon at %s, mark as %d",
  443. devpath, avalon->device_id);
  444. applog(LOG_DEBUG,
  445. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  446. avalon->device_id, baud, work_division, asic_count);
  447. // Since we are adding a new device on the end it
  448. // needs to always be allocated
  449. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  450. malloc(sizeof(struct AVALON_INFO));
  451. if (unlikely(!(avalon_info[avalon->device_id])))
  452. quit(1, "Failed to malloc AVALON_INFO");
  453. info = avalon_info[avalon->device_id];
  454. // Initialise everything to zero for a new device
  455. memset(info, 0, sizeof(struct AVALON_INFO));
  456. info->baud = baud;
  457. info->work_division = work_division;
  458. info->asic_count = asic_count;
  459. info->nonce_mask = mask(work_division);
  460. info->golden_hashes = (golden_nonce_val & info->nonce_mask) *
  461. asic_count;
  462. timersub(&tv_finish, &tv_start, &(info->golden_tv));
  463. set_timing_mode(this_option_offset, avalon);
  464. return true;
  465. }
  466. static void avalon_detect()
  467. {
  468. serial_detect(&avalon_api, avalon_detect_one);
  469. }
  470. static bool avalon_prepare(struct thr_info *thr)
  471. {
  472. struct cgpu_info *avalon = thr->cgpu;
  473. struct timeval now;
  474. avalon->device_fd = -1;
  475. int fd = avalon_open(avalon->device_path,
  476. avalon_info[avalon->device_id]->baud);
  477. if (unlikely(-1 == fd)) {
  478. applog(LOG_ERR, "Failed to open Avalon on %s",
  479. avalon->device_path);
  480. return false;
  481. }
  482. avalon->device_fd = fd;
  483. applog(LOG_INFO, "Opened Avalon on %s", avalon->device_path);
  484. gettimeofday(&now, NULL);
  485. get_datestamp(avalon->init, &now);
  486. return true;
  487. }
  488. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  489. __maybe_unused int64_t max_nonce)
  490. {
  491. struct cgpu_info *avalon;
  492. int fd;
  493. int ret;
  494. struct AVALON_INFO *info;
  495. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  496. char *ob_hex;
  497. uint32_t nonce;
  498. int64_t hash_count;
  499. struct timeval tv_start, tv_finish, elapsed;
  500. struct timeval tv_history_start, tv_history_finish;
  501. double Ti, Xi;
  502. int curr_hw_errors, i;
  503. bool was_hw_error;
  504. struct AVALON_HISTORY *history0, *history;
  505. int count;
  506. double Hs, W, fullnonce;
  507. int read_count;
  508. int64_t estimate_hashes;
  509. uint32_t values;
  510. int64_t hash_count_range;
  511. avalon = thr->cgpu;
  512. info = avalon_info[avalon->device_id];
  513. if (avalon->device_fd == -1)
  514. if (!avalon_prepare(thr)) {
  515. applog(LOG_ERR, "AVA%i: Comms error",
  516. avalon->device_id);
  517. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  518. // fail the device if the reopen attempt fails
  519. return -1;
  520. }
  521. fd = avalon->device_fd;
  522. #ifndef WIN32
  523. tcflush(fd, TCOFLUSH);
  524. #endif
  525. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  526. avalon_create_task(ob_bin, work[i]);
  527. ret = avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  528. if (opt_debug) {
  529. ob_hex = bin2hex(ob_bin, sizeof(ob_bin));
  530. applog(LOG_DEBUG, "Avalon %d sent: %s",
  531. avalon->device_id, ob_hex);
  532. free(ob_hex);
  533. }
  534. if (ret) {
  535. do_avalon_close(thr);
  536. applog(LOG_ERR, "AVA%i: Comms error",
  537. avalon->device_id);
  538. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  539. return 0; /* This should never happen */
  540. }
  541. }
  542. elapsed.tv_sec = elapsed.tv_usec = 0;
  543. gettimeofday(&tv_start, NULL);
  544. /* FIXME: all read should be in another function
  545. Avalon return: reserved_nonce_midstate_data,
  546. count != AVALON_GET_WORK_COUNT */
  547. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  548. ret = avalon_read_work(nonce_bin, fd, &tv_finish, thr);
  549. if (ret == AVA_GETS_ERROR ) {
  550. do_avalon_close(thr);
  551. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  552. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  553. return 0;
  554. }
  555. work[0]->blk.nonce = 0xffffffff;
  556. }
  557. // aborted before becoming idle, get new work
  558. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  559. timersub(&tv_finish, &tv_start, &elapsed);
  560. // ONLY up to just when it aborted
  561. // We didn't read a reply so we don't subtract AVALON_READ_TIME
  562. estimate_hashes = ((double)(elapsed.tv_sec) +
  563. ((double)(elapsed.tv_usec)) /
  564. ((double)1000000)) / info->Hs;
  565. // If some Serial-USB delay allowed the full nonce range to
  566. // complete it can't have done more than a full nonce
  567. if (unlikely(estimate_hashes > 0xffffffff))
  568. estimate_hashes = 0xffffffff;
  569. if (opt_debug) {
  570. applog(LOG_DEBUG,
  571. "Avalon %d no nonce = 0x%08llx hashes "
  572. "(%ld.%06lds)",
  573. avalon->device_id, estimate_hashes,
  574. elapsed.tv_sec, elapsed.tv_usec);
  575. }
  576. return estimate_hashes;
  577. }
  578. memcpy((char *)&nonce, nonce_bin, sizeof(nonce_bin));
  579. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  580. nonce = swab32(nonce);
  581. #endif
  582. curr_hw_errors = avalon->hw_errors;
  583. submit_nonce(thr, work[0], nonce);
  584. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  585. // Force a USB close/reopen on any hw error
  586. if (was_hw_error)
  587. do_avalon_close(thr);
  588. hash_count = (nonce & info->nonce_mask);
  589. hash_count++;
  590. hash_count *= info->asic_count;
  591. if (opt_debug || info->do_avalon_timing)
  592. timersub(&tv_finish, &tv_start, &elapsed);
  593. if (opt_debug) {
  594. applog(LOG_DEBUG,
  595. "Avalon %d nonce = 0x%08x = 0x%08llx hashes "
  596. "(%ld.%06lds)",
  597. avalon->device_id, nonce, hash_count,
  598. elapsed.tv_sec, elapsed.tv_usec);
  599. }
  600. // ignore possible end condition values ... and hw errors
  601. if (info->do_avalon_timing
  602. && !was_hw_error
  603. && ((nonce & info->nonce_mask) > END_CONDITION)
  604. && ((nonce & info->nonce_mask) <
  605. (info->nonce_mask & ~END_CONDITION))) {
  606. gettimeofday(&tv_history_start, NULL);
  607. history0 = &(info->history[0]);
  608. if (history0->values == 0)
  609. timeradd(&tv_start, &history_sec, &(history0->finish));
  610. Ti = (double)(elapsed.tv_sec)
  611. + ((double)(elapsed.tv_usec))/((double)1000000)
  612. - ((double)AVALON_READ_TIME(info->baud));
  613. Xi = (double)hash_count;
  614. history0->sumXiTi += Xi * Ti;
  615. history0->sumXi += Xi;
  616. history0->sumTi += Ti;
  617. history0->sumXi2 += Xi * Xi;
  618. history0->values++;
  619. if (history0->hash_count_max < hash_count)
  620. history0->hash_count_max = hash_count;
  621. if (history0->hash_count_min > hash_count ||
  622. history0->hash_count_min == 0)
  623. history0->hash_count_min = hash_count;
  624. if (history0->values >= info->min_data_count
  625. && timercmp(&tv_start, &(history0->finish), >)) {
  626. for (i = INFO_HISTORY; i > 0; i--)
  627. memcpy(&(info->history[i]),
  628. &(info->history[i-1]),
  629. sizeof(struct AVALON_HISTORY));
  630. // Initialise history0 to zero for summary calculation
  631. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  632. // We just completed a history data set
  633. // So now recalc read_count based on the
  634. // whole history thus we will
  635. // initially get more accurate until it
  636. // completes INFO_HISTORY
  637. // total data sets
  638. count = 0;
  639. for (i = 1 ; i <= INFO_HISTORY; i++) {
  640. history = &(info->history[i]);
  641. if (history->values >= MIN_DATA_COUNT) {
  642. count++;
  643. history0->sumXiTi += history->sumXiTi;
  644. history0->sumXi += history->sumXi;
  645. history0->sumTi += history->sumTi;
  646. history0->sumXi2 += history->sumXi2;
  647. history0->values += history->values;
  648. if (history0->hash_count_max < history->hash_count_max)
  649. history0->hash_count_max = history->hash_count_max;
  650. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  651. history0->hash_count_min = history->hash_count_min;
  652. }
  653. }
  654. // All history data
  655. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  656. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  657. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  658. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  659. values = history0->values;
  660. // Initialise history0 to zero for next data set
  661. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  662. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  663. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  664. info->Hs = Hs;
  665. info->read_count = read_count;
  666. info->fullnonce = fullnonce;
  667. info->count = count;
  668. info->W = W;
  669. info->values = values;
  670. info->hash_count_range = hash_count_range;
  671. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  672. info->min_data_count *= 2;
  673. else if (info->timing_mode == MODE_SHORT)
  674. info->do_avalon_timing = false;
  675. // applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);
  676. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  677. avalon->device_id, Hs, W, read_count, fullnonce);
  678. }
  679. info->history_count++;
  680. gettimeofday(&tv_history_finish, NULL);
  681. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  682. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  683. }
  684. return hash_count;
  685. }
  686. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  687. {
  688. struct api_data *root = NULL;
  689. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  690. // Warning, access to these is not locked - but we don't really
  691. // care since hashing performance is way more important than
  692. // locking access to displaying API debug 'stats'
  693. // If locking becomes an issue for any of them, use copy_data=true also
  694. root = api_add_int(root, "read_count", &(info->read_count), false);
  695. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  696. root = api_add_int(root, "count", &(info->count), false);
  697. root = api_add_hs(root, "Hs", &(info->Hs), false);
  698. root = api_add_double(root, "W", &(info->W), false);
  699. root = api_add_uint(root, "total_values", &(info->values), false);
  700. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  701. root = api_add_uint64(root, "history_count", &(info->history_count),
  702. false);
  703. root = api_add_timeval(root, "history_time", &(info->history_time),
  704. false);
  705. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  706. false);
  707. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  708. false);
  709. root = api_add_const(root, "timing_mode",
  710. timing_mode_str(info->timing_mode), false);
  711. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  712. false);
  713. root = api_add_int(root, "baud", &(info->baud), false);
  714. root = api_add_int(root, "work_division", &(info->work_division),
  715. false);
  716. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  717. return root;
  718. }
  719. static void avalon_shutdown(struct thr_info *thr)
  720. {
  721. do_avalon_close(thr);
  722. }
  723. struct device_api avalon_api = {
  724. .dname = "avalon",
  725. .name = "AVA",
  726. .api_detect = avalon_detect,
  727. .get_api_stats = avalon_api_stats,
  728. .thread_prepare = avalon_prepare,
  729. .scanhash_queue = avalon_scanhash,
  730. .thread_shutdown = avalon_shutdown,
  731. };