driver-avalon.c 33 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  41. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN;
  42. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX;
  43. bool opt_avalon_auto;
  44. static int option_offset = -1;
  45. struct device_drv avalon_drv;
  46. static int avalon_init_task(struct avalon_task *at,
  47. uint8_t reset, uint8_t ff, uint8_t fan,
  48. uint8_t timeout, uint8_t asic_num,
  49. uint8_t miner_num, uint8_t nonce_elf,
  50. uint8_t gate_miner, int frequency)
  51. {
  52. uint16_t *lefreq16;
  53. uint8_t *buf;
  54. static bool first = true;
  55. if (unlikely(!at))
  56. return -1;
  57. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  58. return -1;
  59. memset(at, 0, sizeof(struct avalon_task));
  60. if (unlikely(reset)) {
  61. at->reset = 1;
  62. at->fan_eft = 1;
  63. at->timer_eft = 1;
  64. first = true;
  65. }
  66. at->flush_fifo = (ff ? 1 : 0);
  67. at->fan_eft = (fan ? 1 : 0);
  68. if (unlikely(first && !at->reset)) {
  69. at->fan_eft = 1;
  70. at->timer_eft = 1;
  71. first = false;
  72. }
  73. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  74. at->timeout_data = timeout;
  75. at->asic_num = asic_num;
  76. at->miner_num = miner_num;
  77. at->nonce_elf = nonce_elf;
  78. at->gate_miner_elf = 1;
  79. at->asic_pll = 1;
  80. if (unlikely(gate_miner)) {
  81. at-> gate_miner = 1;
  82. at->asic_pll = 0;
  83. }
  84. buf = (uint8_t *)at;
  85. buf[5] = 0x00;
  86. buf[8] = 0x74;
  87. buf[9] = 0x01;
  88. buf[10] = 0x00;
  89. buf[11] = 0x00;
  90. lefreq16 = (uint16_t *)&buf[6];
  91. *lefreq16 = htole16(frequency * 8);
  92. return 0;
  93. }
  94. static inline void avalon_create_task(struct avalon_task *at,
  95. struct work *work)
  96. {
  97. memcpy(at->midstate, work->midstate, 32);
  98. memcpy(at->data, work->data + 64, 12);
  99. }
  100. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  101. {
  102. int err, amount;
  103. err = usb_write(avalon, buf, len, &amount, ep);
  104. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  105. avalon->device_id, err);
  106. if (unlikely(err != 0)) {
  107. applog(LOG_WARNING, "usb_write error on avalon_write");
  108. return AVA_SEND_ERROR;
  109. }
  110. if (amount != len) {
  111. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  112. return AVA_SEND_ERROR;
  113. }
  114. return AVA_SEND_OK;
  115. }
  116. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  117. {
  118. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  119. int delay, ret, i, ep = C_AVALON_TASK;
  120. struct avalon_info *info;
  121. uint32_t nonce_range;
  122. size_t nr_len;
  123. if (at->nonce_elf)
  124. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  125. else
  126. nr_len = AVALON_WRITE_SIZE;
  127. memcpy(buf, at, AVALON_WRITE_SIZE);
  128. if (at->nonce_elf) {
  129. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  130. for (i = 0; i < at->asic_num; i++) {
  131. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  132. (i * nonce_range & 0xff000000) >> 24;
  133. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  134. (i * nonce_range & 0x00ff0000) >> 16;
  135. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  136. (i * nonce_range & 0x0000ff00) >> 8;
  137. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  138. (i * nonce_range & 0x000000ff) >> 0;
  139. }
  140. }
  141. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  142. uint8_t tt = 0;
  143. tt = (buf[0] & 0x0f) << 4;
  144. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  145. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  146. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  147. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  148. buf[0] = tt;
  149. tt = (buf[4] & 0x0f) << 4;
  150. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  151. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  152. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  153. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  154. buf[4] = tt;
  155. #endif
  156. info = avalon->device_data;
  157. delay = nr_len * 10 * 1000000;
  158. delay = delay / info->baud;
  159. if (at->reset) {
  160. ep = C_AVALON_RESET;
  161. nr_len = 1;
  162. }
  163. if (opt_debug) {
  164. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  165. hexdump(buf, nr_len);
  166. }
  167. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  168. delay += 4000;
  169. nusleep(delay);
  170. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  171. return ret;
  172. }
  173. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  174. struct avalon_info *info, struct avalon_result *ar,
  175. struct work *work)
  176. {
  177. uint32_t nonce;
  178. info = avalon->device_data;
  179. info->matching_work[work->subid]++;
  180. nonce = htole32(ar->nonce);
  181. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  182. return submit_nonce(thr, work, nonce);
  183. }
  184. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  185. static void wait_avalon_ready(struct cgpu_info *avalon)
  186. {
  187. while (avalon_buffer_full(avalon)) {
  188. nmsleep(40);
  189. }
  190. }
  191. #define AVALON_CTS (1 << 4)
  192. static inline bool avalon_cts(char c)
  193. {
  194. return (c & AVALON_CTS);
  195. }
  196. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  197. size_t bufsize, int timeout, int ep)
  198. {
  199. struct avalon_info *info = avalon->device_data;
  200. size_t total = 0, readsize = bufsize + 2;
  201. char readbuf[AVALON_READBUF_SIZE];
  202. int err, amount, ofs = 2, cp;
  203. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  204. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  205. avalon->drv->name, avalon->device_id, err);
  206. if (amount < 2)
  207. goto out;
  208. /* Use the fact that we're reading the status with the buffer to tell
  209. * the write thread it should send more work without needing to call
  210. * avalon_buffer_full directly. */
  211. if (avalon_cts(buf[0]))
  212. cgsem_post(&info->write_sem);
  213. /* The first 2 of every 64 bytes are status on FTDIRL */
  214. while (amount > 2) {
  215. cp = amount - 2;
  216. if (cp > 62)
  217. cp = 62;
  218. memcpy(&buf[total], &readbuf[ofs], cp);
  219. total += cp;
  220. amount -= cp + 2;
  221. ofs += 64;
  222. }
  223. out:
  224. return total;
  225. }
  226. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  227. {
  228. struct avalon_result ar;
  229. int ret, i, spare;
  230. struct avalon_task at;
  231. uint8_t *buf, *tmp;
  232. struct timespec p;
  233. /* Send reset, then check for result */
  234. avalon_init_task(&at, 1, 0,
  235. AVALON_DEFAULT_FAN_MAX_PWM,
  236. AVALON_DEFAULT_TIMEOUT,
  237. AVALON_DEFAULT_ASIC_NUM,
  238. AVALON_DEFAULT_MINER_NUM,
  239. 0, 0,
  240. AVALON_DEFAULT_FREQUENCY);
  241. wait_avalon_ready(avalon);
  242. ret = avalon_send_task(&at, avalon);
  243. if (unlikely(ret == AVA_SEND_ERROR))
  244. return -1;
  245. if (!initial) {
  246. applog(LOG_ERR, "AVA%d reset sequence sent", avalon->device_id);
  247. return 0;
  248. }
  249. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  250. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  251. /* What do these sleeps do?? */
  252. p.tv_sec = 0;
  253. p.tv_nsec = AVALON_RESET_PITCH;
  254. nanosleep(&p, NULL);
  255. /* Look for the first occurrence of 0xAA, the reset response should be:
  256. * AA 55 AA 55 00 00 00 00 00 00 */
  257. spare = ret - 10;
  258. buf = tmp = (uint8_t *)&ar;
  259. if (opt_debug) {
  260. applog(LOG_DEBUG, "AVA%d reset: get:", avalon->device_id);
  261. hexdump(tmp, AVALON_READ_SIZE);
  262. }
  263. for (i = 0; i <= spare; i++) {
  264. buf = &tmp[i];
  265. if (buf[0] == 0xAA)
  266. break;
  267. }
  268. i = 0;
  269. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  270. buf[2] == 0xAA && buf[3] == 0x55) {
  271. for (i = 4; i < 11; i++)
  272. if (buf[i] != 0)
  273. break;
  274. }
  275. if (i != 11) {
  276. applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
  277. " (%d: %02x %02x %02x %02x)", avalon->device_id,
  278. i, buf[0], buf[1], buf[2], buf[3]);
  279. /* FIXME: return 1; */
  280. } else
  281. applog(LOG_WARNING, "AVA%d: Reset succeeded",
  282. avalon->device_id);
  283. return 0;
  284. }
  285. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  286. int *asic_count, int *timeout, int *frequency)
  287. {
  288. char buf[BUFSIZ+1];
  289. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  290. size_t max;
  291. int i, tmp;
  292. if (opt_avalon_options == NULL)
  293. buf[0] = '\0';
  294. else {
  295. ptr = opt_avalon_options;
  296. for (i = 0; i < this_option_offset; i++) {
  297. comma = strchr(ptr, ',');
  298. if (comma == NULL)
  299. break;
  300. ptr = comma + 1;
  301. }
  302. comma = strchr(ptr, ',');
  303. if (comma == NULL)
  304. max = strlen(ptr);
  305. else
  306. max = comma - ptr;
  307. if (max > BUFSIZ)
  308. max = BUFSIZ;
  309. strncpy(buf, ptr, max);
  310. buf[max] = '\0';
  311. }
  312. if (!(*buf))
  313. return false;
  314. colon = strchr(buf, ':');
  315. if (colon)
  316. *(colon++) = '\0';
  317. tmp = atoi(buf);
  318. switch (tmp) {
  319. case 115200:
  320. *baud = 115200;
  321. break;
  322. case 57600:
  323. *baud = 57600;
  324. break;
  325. case 38400:
  326. *baud = 38400;
  327. break;
  328. case 19200:
  329. *baud = 19200;
  330. break;
  331. default:
  332. quit(1, "Invalid avalon-options for baud (%s) "
  333. "must be 115200, 57600, 38400 or 19200", buf);
  334. }
  335. if (colon && *colon) {
  336. colon2 = strchr(colon, ':');
  337. if (colon2)
  338. *(colon2++) = '\0';
  339. if (*colon) {
  340. tmp = atoi(colon);
  341. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  342. *miner_count = tmp;
  343. } else {
  344. quit(1, "Invalid avalon-options for "
  345. "miner_count (%s) must be 1 ~ %d",
  346. colon, AVALON_DEFAULT_MINER_NUM);
  347. }
  348. }
  349. if (colon2 && *colon2) {
  350. colon3 = strchr(colon2, ':');
  351. if (colon3)
  352. *(colon3++) = '\0';
  353. tmp = atoi(colon2);
  354. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  355. *asic_count = tmp;
  356. else {
  357. quit(1, "Invalid avalon-options for "
  358. "asic_count (%s) must be 1 ~ %d",
  359. colon2, AVALON_DEFAULT_ASIC_NUM);
  360. }
  361. if (colon3 && *colon3) {
  362. colon4 = strchr(colon3, ':');
  363. if (colon4)
  364. *(colon4++) = '\0';
  365. tmp = atoi(colon3);
  366. if (tmp > 0 && tmp <= 0xff)
  367. *timeout = tmp;
  368. else {
  369. quit(1, "Invalid avalon-options for "
  370. "timeout (%s) must be 1 ~ %d",
  371. colon3, 0xff);
  372. }
  373. if (colon4 && *colon4) {
  374. tmp = atoi(colon4);
  375. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  376. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  377. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  378. }
  379. *frequency = tmp;
  380. }
  381. }
  382. }
  383. }
  384. return true;
  385. }
  386. char *set_avalon_fan(char *arg)
  387. {
  388. int val1, val2, ret;
  389. ret = sscanf(arg, "%d-%d", &val1, &val2);
  390. if (ret < 1)
  391. return "No values passed to avalon-fan";
  392. if (ret == 1)
  393. val2 = val1;
  394. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  395. return "Invalid value passed to avalon-fan";
  396. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  397. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  398. return NULL;
  399. }
  400. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  401. {
  402. int i;
  403. info->idle = true;
  404. wait_avalon_ready(avalon);
  405. /* Send idle to all miners */
  406. for (i = 0; i < info->miner_count; i++) {
  407. struct avalon_task at;
  408. if (unlikely(avalon_buffer_full(avalon)))
  409. break;
  410. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  411. info->asic_count, info->miner_count, 1, 1,
  412. info->frequency);
  413. avalon_send_task(&at, avalon);
  414. }
  415. applog(LOG_WARNING, "AVA%i: Idling %d miners", avalon->device_id, i);
  416. wait_avalon_ready(avalon);
  417. }
  418. static void avalon_initialise(struct cgpu_info *avalon)
  419. {
  420. int err, interface;
  421. if (avalon->usbinfo.nodev)
  422. return;
  423. interface = avalon->usbdev->found->interface;
  424. // Reset
  425. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  426. FTDI_VALUE_RESET, interface, C_RESET);
  427. applog(LOG_DEBUG, "%s%i: reset got err %d",
  428. avalon->drv->name, avalon->device_id, err);
  429. if (avalon->usbinfo.nodev)
  430. return;
  431. // Set latency
  432. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  433. AVALON_LATENCY, interface, C_LATENCY);
  434. applog(LOG_DEBUG, "%s%i: latency got err %d",
  435. avalon->drv->name, avalon->device_id, err);
  436. if (avalon->usbinfo.nodev)
  437. return;
  438. // Set data
  439. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  440. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  441. applog(LOG_DEBUG, "%s%i: data got err %d",
  442. avalon->drv->name, avalon->device_id, err);
  443. if (avalon->usbinfo.nodev)
  444. return;
  445. // Set the baud
  446. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  447. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  448. C_SETBAUD);
  449. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  450. avalon->drv->name, avalon->device_id, err);
  451. if (avalon->usbinfo.nodev)
  452. return;
  453. // Set Modem Control
  454. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  455. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  456. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  457. avalon->drv->name, avalon->device_id, err);
  458. if (avalon->usbinfo.nodev)
  459. return;
  460. // Set Flow Control
  461. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  462. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  463. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  464. avalon->drv->name, avalon->device_id, err);
  465. if (avalon->usbinfo.nodev)
  466. return;
  467. /* Avalon repeats the following */
  468. // Set Modem Control
  469. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  470. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  471. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  472. avalon->drv->name, avalon->device_id, err);
  473. if (avalon->usbinfo.nodev)
  474. return;
  475. // Set Flow Control
  476. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  477. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  478. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  479. avalon->drv->name, avalon->device_id, err);
  480. }
  481. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  482. {
  483. int baud, miner_count, asic_count, timeout, frequency = 0;
  484. int this_option_offset = ++option_offset;
  485. struct avalon_info *info;
  486. struct cgpu_info *avalon;
  487. bool configured;
  488. int ret;
  489. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  490. configured = get_options(this_option_offset, &baud, &miner_count,
  491. &asic_count, &timeout, &frequency);
  492. if (!usb_init(avalon, dev, found))
  493. goto shin;
  494. /* Even though this is an FTDI type chip, we want to do the parsing
  495. * all ourselves so set it to std usb type */
  496. avalon->usbdev->usb_type = USB_TYPE_STD;
  497. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  498. /* We have a real Avalon! */
  499. avalon_initialise(avalon);
  500. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  501. if (unlikely(!(avalon->device_data)))
  502. quit(1, "Failed to calloc avalon_info data");
  503. info = avalon->device_data;
  504. if (configured) {
  505. info->baud = baud;
  506. info->miner_count = miner_count;
  507. info->asic_count = asic_count;
  508. info->timeout = timeout;
  509. info->frequency = frequency;
  510. } else {
  511. info->baud = AVALON_IO_SPEED;
  512. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  513. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  514. info->timeout = AVALON_DEFAULT_TIMEOUT;
  515. info->frequency = AVALON_DEFAULT_FREQUENCY;
  516. }
  517. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  518. info->temp_max = 0;
  519. /* This is for check the temp/fan every 3~4s */
  520. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  521. if (info->temp_history_count <= 0)
  522. info->temp_history_count = 1;
  523. info->temp_history_index = 0;
  524. info->temp_sum = 0;
  525. info->temp_old = 0;
  526. if (!add_cgpu(avalon))
  527. goto unshin;
  528. ret = avalon_reset(avalon, true);
  529. if (ret && !configured)
  530. goto unshin;
  531. update_usb_stats(avalon);
  532. avalon_idle(avalon, info);
  533. applog(LOG_DEBUG, "Avalon Detected: %s "
  534. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  535. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  536. info->frequency);
  537. return true;
  538. unshin:
  539. usb_uninit(avalon);
  540. shin:
  541. free(avalon->device_data);
  542. avalon->device_data = NULL;
  543. avalon = usb_free_cgpu(avalon);
  544. return false;
  545. }
  546. static void avalon_detect(void)
  547. {
  548. usb_detect(&avalon_drv, avalon_detect_one);
  549. }
  550. static void avalon_init(struct cgpu_info *avalon)
  551. {
  552. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  553. }
  554. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  555. {
  556. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  557. (char *)ar->data, 64, 12);
  558. }
  559. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  560. struct avalon_result *ar);
  561. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  562. {
  563. if (unlikely(info->idle))
  564. return;
  565. applog(LOG_INFO, "%s%d: No matching work - HW error",
  566. thr->cgpu->drv->name, thr->cgpu->device_id);
  567. inc_hw_errors(thr);
  568. info->no_matching_work++;
  569. }
  570. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  571. struct thr_info *thr, char *buf, int *offset)
  572. {
  573. int i, spare = *offset - AVALON_READ_SIZE;
  574. bool found = false;
  575. for (i = 0; i <= spare; i++) {
  576. struct avalon_result *ar;
  577. struct work *work;
  578. ar = (struct avalon_result *)&buf[i];
  579. work = avalon_valid_result(avalon, ar);
  580. if (work) {
  581. bool gettemp = false;
  582. found = true;
  583. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  584. mutex_lock(&info->lock);
  585. if (!info->nonces++)
  586. gettemp = true;
  587. info->auto_nonces++;
  588. mutex_unlock(&info->lock);
  589. } else if (opt_avalon_auto) {
  590. mutex_lock(&info->lock);
  591. info->auto_hw++;
  592. mutex_unlock(&info->lock);
  593. }
  594. if (gettemp)
  595. avalon_update_temps(avalon, info, ar);
  596. break;
  597. }
  598. }
  599. if (!found) {
  600. spare = *offset - AVALON_READ_SIZE;
  601. /* We are buffering and haven't accumulated one more corrupt
  602. * work result. */
  603. if (spare < (int)AVALON_READ_SIZE)
  604. return;
  605. avalon_inc_nvw(info, thr);
  606. } else {
  607. spare = AVALON_READ_SIZE + i;
  608. if (i) {
  609. if (i >= (int)AVALON_READ_SIZE)
  610. avalon_inc_nvw(info, thr);
  611. else
  612. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  613. }
  614. }
  615. *offset -= spare;
  616. memmove(buf, buf + spare, *offset);
  617. }
  618. static void avalon_running_reset(struct cgpu_info *avalon,
  619. struct avalon_info *info)
  620. {
  621. avalon_reset(avalon, false);
  622. avalon_idle(avalon, info);
  623. avalon->results = 0;
  624. info->reset = false;
  625. }
  626. static void *avalon_get_results(void *userdata)
  627. {
  628. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  629. struct avalon_info *info = avalon->device_data;
  630. int offset = 0, read_delay = 0, ret = 0;
  631. const int rsize = AVALON_FTDI_READSIZE;
  632. char readbuf[AVALON_READBUF_SIZE];
  633. struct thr_info *thr = info->thr;
  634. struct timeval tv_start, tv_end;
  635. char threadname[24];
  636. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  637. RenameThread(threadname);
  638. while (likely(!avalon->shutdown)) {
  639. unsigned char buf[rsize];
  640. struct timeval tv_diff;
  641. int us_diff;
  642. if (offset >= (int)AVALON_READ_SIZE)
  643. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  644. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  645. /* This should never happen */
  646. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  647. offset = 0;
  648. }
  649. if (unlikely(info->reset)) {
  650. avalon_running_reset(avalon, info);
  651. /* Discard anything in the buffer */
  652. offset = 0;
  653. }
  654. /* As the usb read returns after just 1ms, sleep long enough
  655. * to leave the interface idle for writes to occur, but do not
  656. * sleep if we have been receiving data as more may be coming. */
  657. if (ret < 1) {
  658. cgtime(&tv_end);
  659. timersub(&tv_end, &tv_start, &tv_diff);
  660. /* Assume it has not been > 1 second so ignore tv_sec */
  661. us_diff = tv_diff.tv_usec;
  662. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  663. if (likely(read_delay >= 1000))
  664. nusleep(read_delay);
  665. }
  666. cgtime(&tv_start);
  667. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  668. C_AVALON_READ);
  669. if (ret < 1)
  670. continue;
  671. if (opt_debug) {
  672. applog(LOG_DEBUG, "Avalon: get:");
  673. hexdump((uint8_t *)buf, ret);
  674. }
  675. memcpy(&readbuf[offset], &buf, ret);
  676. offset += ret;
  677. }
  678. return NULL;
  679. }
  680. static void avalon_rotate_array(struct cgpu_info *avalon)
  681. {
  682. avalon->queued = 0;
  683. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  684. avalon->work_array = 0;
  685. }
  686. static void avalon_set_timeout(struct avalon_info *info)
  687. {
  688. info->timeout = AVALON_TIMEOUT_FACTOR / info->frequency;
  689. }
  690. static void avalon_inc_freq(struct avalon_info *info)
  691. {
  692. info->frequency += 2;
  693. if (info->frequency > AVALON_MAX_FREQUENCY)
  694. info->frequency = AVALON_MAX_FREQUENCY;
  695. avalon_set_timeout(info);
  696. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  697. info->frequency, info->timeout);
  698. }
  699. static void avalon_dec_freq(struct avalon_info *info)
  700. {
  701. info->frequency -= 1;
  702. if (info->frequency < AVALON_MIN_FREQUENCY)
  703. info->frequency = AVALON_MIN_FREQUENCY;
  704. avalon_set_timeout(info);
  705. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  706. info->frequency, info->timeout);
  707. }
  708. static void avalon_reset_auto(struct avalon_info *info)
  709. {
  710. info->auto_queued =
  711. info->auto_nonces =
  712. info->auto_hw = 0;
  713. }
  714. static void *avalon_send_tasks(void *userdata)
  715. {
  716. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  717. struct avalon_info *info = avalon->device_data;
  718. const int avalon_get_work_count = info->miner_count;
  719. char threadname[24];
  720. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  721. RenameThread(threadname);
  722. while (likely(!avalon->shutdown)) {
  723. int start_count, end_count, i, j, ret;
  724. struct avalon_task at;
  725. int idled = 0;
  726. while (avalon_buffer_full(avalon))
  727. cgsem_wait(&info->write_sem);
  728. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  729. mutex_lock(&info->lock);
  730. if (!info->optimal) {
  731. applog(LOG_WARNING, "AVA%i: Above optimal temperature, throttling",
  732. avalon->device_id);
  733. avalon_dec_freq(info);
  734. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  735. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  736. int total = info->auto_nonces + info->auto_hw;
  737. /* Try to keep hw errors ~1% */
  738. if (info->auto_hw * 200 < total)
  739. avalon_inc_freq(info);
  740. else if (info->auto_hw * 100 > total)
  741. avalon_dec_freq(info);
  742. }
  743. avalon_reset_auto(info);
  744. mutex_unlock(&info->lock);
  745. }
  746. mutex_lock(&info->qlock);
  747. start_count = avalon->work_array * avalon_get_work_count;
  748. end_count = start_count + avalon_get_work_count;
  749. for (i = start_count, j = 0; i < end_count; i++, j++) {
  750. if (avalon_buffer_full(avalon)) {
  751. applog(LOG_INFO,
  752. "AVA%i: Buffer full after only %d of %d work queued",
  753. avalon->device_id, j, avalon_get_work_count);
  754. break;
  755. }
  756. if (likely(j < avalon->queued && !info->overheat)) {
  757. info->idle = false;
  758. avalon_init_task(&at, 0, 0, info->fan_pwm,
  759. info->timeout, info->asic_count,
  760. info->miner_count, 1, 0, info->frequency);
  761. avalon_create_task(&at, avalon->works[i]);
  762. info->auto_queued++;
  763. } else {
  764. idled++;
  765. avalon_init_task(&at, 0, 0, info->fan_pwm,
  766. info->timeout, info->asic_count,
  767. info->miner_count, 1, 1, info->frequency);
  768. /* Reset the auto_queued count if we end up
  769. * idling any miners. */
  770. avalon_reset_auto(info);
  771. }
  772. ret = avalon_send_task(&at, avalon);
  773. if (unlikely(ret == AVA_SEND_ERROR)) {
  774. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  775. avalon->device_id);
  776. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  777. info->reset = true;
  778. break;
  779. }
  780. }
  781. avalon_rotate_array(avalon);
  782. pthread_cond_signal(&info->qcond);
  783. mutex_unlock(&info->qlock);
  784. if (unlikely(idled && !info->idle)) {
  785. info->idle = true;
  786. applog(LOG_WARNING, "AVA%i: Idled %d miners",
  787. avalon->device_id, idled);
  788. }
  789. }
  790. return NULL;
  791. }
  792. static bool avalon_prepare(struct thr_info *thr)
  793. {
  794. struct cgpu_info *avalon = thr->cgpu;
  795. struct avalon_info *info = avalon->device_data;
  796. struct timeval now;
  797. free(avalon->works);
  798. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  799. AVALON_ARRAY_SIZE);
  800. if (!avalon->works)
  801. quit(1, "Failed to calloc avalon works in avalon_prepare");
  802. info->thr = thr;
  803. mutex_init(&info->lock);
  804. mutex_init(&info->qlock);
  805. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  806. quit(1, "Failed to pthread_cond_init avalon qcond");
  807. cgsem_init(&info->write_sem);
  808. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  809. quit(1, "Failed to create avalon read_thr");
  810. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  811. quit(1, "Failed to create avalon write_thr");
  812. avalon_init(avalon);
  813. cgtime(&now);
  814. get_datestamp(avalon->init, &now);
  815. return true;
  816. }
  817. static void do_avalon_close(struct thr_info *thr)
  818. {
  819. struct cgpu_info *avalon = thr->cgpu;
  820. struct avalon_info *info = avalon->device_data;
  821. pthread_join(info->read_thr, NULL);
  822. pthread_join(info->write_thr, NULL);
  823. avalon_running_reset(avalon, info);
  824. info->no_matching_work = 0;
  825. cgsem_destroy(&info->write_sem);
  826. }
  827. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  828. {
  829. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  830. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  831. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  832. info->temp0 = ar->temp0;
  833. info->temp1 = ar->temp1;
  834. info->temp2 = ar->temp2;
  835. if (ar->temp0 & 0x80) {
  836. ar->temp0 &= 0x7f;
  837. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  838. }
  839. if (ar->temp1 & 0x80) {
  840. ar->temp1 &= 0x7f;
  841. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  842. }
  843. if (ar->temp2 & 0x80) {
  844. ar->temp2 &= 0x7f;
  845. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  846. }
  847. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  848. if (info->temp0 > info->temp_max)
  849. info->temp_max = info->temp0;
  850. if (info->temp1 > info->temp_max)
  851. info->temp_max = info->temp1;
  852. if (info->temp2 > info->temp_max)
  853. info->temp_max = info->temp2;
  854. }
  855. static void temp_rise(struct avalon_info *info, int temp)
  856. {
  857. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  858. info->fan_pwm = AVALON_PWM_MAX;
  859. return;
  860. }
  861. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  862. info->fan_pwm += 10;
  863. else if (temp > opt_avalon_temp)
  864. info->fan_pwm += 5;
  865. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  866. info->fan_pwm += 1;
  867. else
  868. return;
  869. if (info->fan_pwm > opt_avalon_fan_max)
  870. info->fan_pwm = opt_avalon_fan_max;
  871. }
  872. static void temp_drop(struct avalon_info *info, int temp)
  873. {
  874. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  875. info->fan_pwm = opt_avalon_fan_min;
  876. return;
  877. }
  878. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  879. info->fan_pwm -= 10;
  880. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  881. info->fan_pwm -= 5;
  882. else if (temp < opt_avalon_temp)
  883. info->fan_pwm -= 1;
  884. if (info->fan_pwm < opt_avalon_fan_min)
  885. info->fan_pwm = opt_avalon_fan_min;
  886. }
  887. static inline void adjust_fan(struct avalon_info *info)
  888. {
  889. int temp_new;
  890. temp_new = info->temp_sum / info->temp_history_count;
  891. if (temp_new > info->temp_old)
  892. temp_rise(info, temp_new);
  893. else if (temp_new < info->temp_old)
  894. temp_drop(info, temp_new);
  895. else {
  896. /* temp_new == info->temp_old */
  897. if (temp_new > opt_avalon_temp)
  898. temp_rise(info, temp_new);
  899. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  900. temp_drop(info, temp_new);
  901. }
  902. info->temp_old = temp_new;
  903. if (info->temp_old <= opt_avalon_temp)
  904. info->optimal = true;
  905. else
  906. info->optimal = false;
  907. }
  908. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  909. struct avalon_result *ar)
  910. {
  911. record_temp_fan(info, ar, &(avalon->temp));
  912. applog(LOG_INFO,
  913. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  914. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  915. info->fan0, info->fan1, info->fan2,
  916. info->temp0, info->temp1, info->temp2, info->temp_max);
  917. info->temp_history_index++;
  918. info->temp_sum += avalon->temp;
  919. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  920. info->temp_history_index, info->temp_history_count, info->temp_old);
  921. if (info->temp_history_index == info->temp_history_count) {
  922. adjust_fan(info);
  923. info->temp_history_index = 0;
  924. info->temp_sum = 0;
  925. }
  926. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  927. applog(LOG_WARNING, "AVA%d overheat! Idling", avalon->device_id);
  928. info->overheat = true;
  929. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  930. applog(LOG_WARNING, "AVA%d cooled, restarting", avalon->device_id);
  931. info->overheat = false;
  932. }
  933. }
  934. static void get_avalon_statline_before(char *buf, struct cgpu_info *avalon)
  935. {
  936. struct avalon_info *info = avalon->device_data;
  937. int lowfan = 10000;
  938. /* Find the lowest fan speed of the ASIC cooling fans. */
  939. if (info->fan1 >= 0 && info->fan1 < lowfan)
  940. lowfan = info->fan1;
  941. if (info->fan2 >= 0 && info->fan2 < lowfan)
  942. lowfan = info->fan2;
  943. tailsprintf(buf, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  944. }
  945. /* We use a replacement algorithm to only remove references to work done from
  946. * the buffer when we need the extra space for new work. */
  947. static bool avalon_fill(struct cgpu_info *avalon)
  948. {
  949. struct avalon_info *info = avalon->device_data;
  950. int subid, slot, mc;
  951. struct work *work;
  952. bool ret = true;
  953. mc = info->miner_count;
  954. mutex_lock(&info->qlock);
  955. if (avalon->queued >= mc)
  956. goto out_unlock;
  957. work = get_queued(avalon);
  958. if (unlikely(!work)) {
  959. ret = false;
  960. goto out_unlock;
  961. }
  962. subid = avalon->queued++;
  963. work->subid = subid;
  964. slot = avalon->work_array * mc + subid;
  965. if (likely(avalon->works[slot]))
  966. work_completed(avalon, avalon->works[slot]);
  967. avalon->works[slot] = work;
  968. if (avalon->queued < mc)
  969. ret = false;
  970. out_unlock:
  971. mutex_unlock(&info->qlock);
  972. return ret;
  973. }
  974. static int64_t avalon_scanhash(struct thr_info *thr)
  975. {
  976. struct cgpu_info *avalon = thr->cgpu;
  977. struct avalon_info *info = avalon->device_data;
  978. const int miner_count = info->miner_count;
  979. struct timeval now, then, tdiff;
  980. int64_t hash_count, us_timeout;
  981. struct timespec abstime;
  982. /* Half nonce range */
  983. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  984. tdiff.tv_sec = us_timeout / 1000000;
  985. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  986. cgtime(&now);
  987. timeradd(&now, &tdiff, &then);
  988. abstime.tv_sec = then.tv_sec;
  989. abstime.tv_nsec = then.tv_usec * 1000;
  990. /* Wait until avalon_send_tasks signals us that it has completed
  991. * sending its work or a full nonce range timeout has occurred */
  992. mutex_lock(&info->qlock);
  993. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  994. mutex_unlock(&info->qlock);
  995. mutex_lock(&info->lock);
  996. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  997. avalon->results += info->nonces;
  998. if (avalon->results > miner_count)
  999. avalon->results = miner_count;
  1000. if (!info->idle && !info->reset)
  1001. avalon->results -= miner_count / 3;
  1002. else
  1003. avalon->results = miner_count;
  1004. info->nonces = 0;
  1005. mutex_unlock(&info->lock);
  1006. /* Check for nothing but consecutive bad results or consistently less
  1007. * results than we should be getting and reset the FPGA if necessary */
  1008. if (avalon->results < -miner_count && !info->reset) {
  1009. applog(LOG_ERR, "AVA%d: Result return rate low, resetting!",
  1010. avalon->device_id);
  1011. info->reset = true;
  1012. }
  1013. if (unlikely(avalon->usbinfo.nodev)) {
  1014. applog(LOG_ERR, "AVA%d: Device disappeared, shutting down thread",
  1015. avalon->device_id);
  1016. avalon->shutdown = true;
  1017. }
  1018. /* This hashmeter is just a utility counter based on returned shares */
  1019. return hash_count;
  1020. }
  1021. static void avalon_flush_work(struct cgpu_info *avalon)
  1022. {
  1023. struct avalon_info *info = avalon->device_data;
  1024. mutex_lock(&info->qlock);
  1025. /* Will overwrite any work queued */
  1026. avalon->queued = 0;
  1027. pthread_cond_signal(&info->qcond);
  1028. mutex_unlock(&info->qlock);
  1029. }
  1030. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1031. {
  1032. struct api_data *root = NULL;
  1033. struct avalon_info *info = cgpu->device_data;
  1034. int i;
  1035. root = api_add_int(root, "baud", &(info->baud), false);
  1036. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1037. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1038. root = api_add_int(root, "timeout", &(info->timeout), false);
  1039. root = api_add_int(root, "frequency", &(info->frequency), false);
  1040. root = api_add_int(root, "fan1", &(info->fan0), false);
  1041. root = api_add_int(root, "fan2", &(info->fan1), false);
  1042. root = api_add_int(root, "fan3", &(info->fan2), false);
  1043. root = api_add_int(root, "temp1", &(info->temp0), false);
  1044. root = api_add_int(root, "temp2", &(info->temp1), false);
  1045. root = api_add_int(root, "temp3", &(info->temp2), false);
  1046. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1047. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1048. for (i = 0; i < info->miner_count; i++) {
  1049. char mcw[24];
  1050. sprintf(mcw, "match_work_count%d", i + 1);
  1051. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1052. }
  1053. return root;
  1054. }
  1055. static void avalon_shutdown(struct thr_info *thr)
  1056. {
  1057. do_avalon_close(thr);
  1058. }
  1059. struct device_drv avalon_drv = {
  1060. .drv_id = DRIVER_AVALON,
  1061. .dname = "avalon",
  1062. .name = "AVA",
  1063. .drv_detect = avalon_detect,
  1064. .thread_prepare = avalon_prepare,
  1065. .hash_work = hash_queued_work,
  1066. .queue_full = avalon_fill,
  1067. .scanwork = avalon_scanhash,
  1068. .flush_work = avalon_flush_work,
  1069. .get_api_stats = avalon_api_stats,
  1070. .get_statline_before = get_avalon_statline_before,
  1071. .reinit_device = avalon_init,
  1072. .thread_shutdown = avalon_shutdown,
  1073. };