driver-avalon.c 42 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #include <time.h>
  22. #ifndef WIN32
  23. #include <sys/select.h>
  24. #include <termios.h>
  25. #include <sys/stat.h>
  26. #include <fcntl.h>
  27. #ifndef O_CLOEXEC
  28. #define O_CLOEXEC 0
  29. #endif
  30. #else
  31. #include "compat.h"
  32. #include <windows.h>
  33. #include <io.h>
  34. #endif
  35. #include "elist.h"
  36. #include "miner.h"
  37. #include "usbutils.h"
  38. #include "driver-avalon.h"
  39. #include "hexdump.c"
  40. #include "util.h"
  41. int opt_avalon_temp = AVALON_TEMP_TARGET;
  42. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  43. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  44. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  45. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  46. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  47. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  48. bool opt_avalon_auto;
  49. static int option_offset = -1;
  50. static int avalon_init_task(struct avalon_task *at,
  51. uint8_t reset, uint8_t ff, uint8_t fan,
  52. uint8_t timeout, uint8_t asic_num,
  53. uint8_t miner_num, uint8_t nonce_elf,
  54. uint8_t gate_miner, int frequency)
  55. {
  56. uint16_t *lefreq16;
  57. uint8_t *buf;
  58. static bool first = true;
  59. if (unlikely(!at))
  60. return -1;
  61. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  62. return -1;
  63. memset(at, 0, sizeof(struct avalon_task));
  64. if (unlikely(reset)) {
  65. at->reset = 1;
  66. at->fan_eft = 1;
  67. at->timer_eft = 1;
  68. first = true;
  69. }
  70. at->flush_fifo = (ff ? 1 : 0);
  71. at->fan_eft = (fan ? 1 : 0);
  72. if (unlikely(first && !at->reset)) {
  73. at->fan_eft = 1;
  74. at->timer_eft = 1;
  75. first = false;
  76. }
  77. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  78. at->timeout_data = timeout;
  79. at->asic_num = asic_num;
  80. at->miner_num = miner_num;
  81. at->nonce_elf = nonce_elf;
  82. at->gate_miner_elf = 1;
  83. at->asic_pll = 1;
  84. if (unlikely(gate_miner)) {
  85. at-> gate_miner = 1;
  86. at->asic_pll = 0;
  87. }
  88. buf = (uint8_t *)at;
  89. buf[5] = 0x00;
  90. buf[8] = 0x74;
  91. buf[9] = 0x01;
  92. buf[10] = 0x00;
  93. buf[11] = 0x00;
  94. lefreq16 = (uint16_t *)&buf[6];
  95. *lefreq16 = htole16(frequency * 8);
  96. return 0;
  97. }
  98. static inline void avalon_create_task(struct avalon_task *at,
  99. struct work *work)
  100. {
  101. memcpy(at->midstate, work->midstate, 32);
  102. memcpy(at->data, work->data + 64, 12);
  103. }
  104. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  105. {
  106. int err, amount;
  107. err = usb_write(avalon, buf, len, &amount, ep);
  108. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  109. avalon->device_id, err);
  110. if (unlikely(err != 0)) {
  111. applog(LOG_WARNING, "usb_write error on avalon_write");
  112. return AVA_SEND_ERROR;
  113. }
  114. if (amount != len) {
  115. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  116. return AVA_SEND_ERROR;
  117. }
  118. return AVA_SEND_OK;
  119. }
  120. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  121. {
  122. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  123. int delay, ret, i, ep = C_AVALON_TASK;
  124. struct avalon_info *info;
  125. cgtimer_t ts_start;
  126. uint32_t nonce_range;
  127. size_t nr_len;
  128. if (at->nonce_elf)
  129. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  130. else
  131. nr_len = AVALON_WRITE_SIZE;
  132. memcpy(buf, at, AVALON_WRITE_SIZE);
  133. if (at->nonce_elf) {
  134. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  135. for (i = 0; i < at->asic_num; i++) {
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  137. (i * nonce_range & 0xff000000) >> 24;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  139. (i * nonce_range & 0x00ff0000) >> 16;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  141. (i * nonce_range & 0x0000ff00) >> 8;
  142. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  143. (i * nonce_range & 0x000000ff) >> 0;
  144. }
  145. }
  146. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  147. uint8_t tt = 0;
  148. tt = (buf[0] & 0x0f) << 4;
  149. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  150. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  151. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  152. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  153. buf[0] = tt;
  154. tt = (buf[4] & 0x0f) << 4;
  155. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  156. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  157. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  158. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  159. buf[4] = tt;
  160. #endif
  161. info = avalon->device_data;
  162. delay = nr_len * 10 * 1000000;
  163. delay = delay / info->baud;
  164. delay += 4000;
  165. if (at->reset) {
  166. ep = C_AVALON_RESET;
  167. nr_len = 1;
  168. }
  169. if (opt_debug) {
  170. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  171. hexdump(buf, nr_len);
  172. }
  173. cgsleep_prepare_r(&ts_start);
  174. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  175. cgsleep_us_r(&ts_start, delay);
  176. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  177. return ret;
  178. }
  179. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  180. struct avalon_info *info, struct avalon_result *ar,
  181. struct work *work)
  182. {
  183. uint32_t nonce;
  184. info = avalon->device_data;
  185. info->matching_work[work->subid]++;
  186. nonce = htole32(ar->nonce);
  187. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  188. return submit_nonce(thr, work, nonce);
  189. }
  190. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  191. static void wait_avalon_ready(struct cgpu_info *avalon)
  192. {
  193. while (avalon_buffer_full(avalon)) {
  194. cgsleep_ms(40);
  195. }
  196. }
  197. #define AVALON_CTS (1 << 4)
  198. static inline bool avalon_cts(char c)
  199. {
  200. return (c & AVALON_CTS);
  201. }
  202. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  203. size_t bufsize, int timeout, int ep)
  204. {
  205. size_t total = 0, readsize = bufsize + 2;
  206. char readbuf[AVALON_READBUF_SIZE];
  207. int err, amount, ofs = 2, cp;
  208. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  209. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  210. avalon->drv->name, avalon->device_id, err);
  211. if (amount < 2)
  212. goto out;
  213. /* The first 2 of every 64 bytes are status on FTDIRL */
  214. while (amount > 2) {
  215. cp = amount - 2;
  216. if (cp > 62)
  217. cp = 62;
  218. memcpy(&buf[total], &readbuf[ofs], cp);
  219. total += cp;
  220. amount -= cp + 2;
  221. ofs += 64;
  222. }
  223. out:
  224. return total;
  225. }
  226. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  227. {
  228. struct avalon_result ar;
  229. int ret, i, spare;
  230. struct avalon_task at;
  231. uint8_t *buf, *tmp;
  232. struct timespec p;
  233. struct avalon_info *info = avalon->device_data;
  234. /* Send reset, then check for result */
  235. avalon_init_task(&at, 1, 0,
  236. AVALON_DEFAULT_FAN_MAX_PWM,
  237. AVALON_DEFAULT_TIMEOUT,
  238. AVALON_DEFAULT_ASIC_NUM,
  239. AVALON_DEFAULT_MINER_NUM,
  240. 0, 0,
  241. AVALON_DEFAULT_FREQUENCY);
  242. wait_avalon_ready(avalon);
  243. ret = avalon_send_task(&at, avalon);
  244. if (unlikely(ret == AVA_SEND_ERROR))
  245. return -1;
  246. if (!initial) {
  247. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  248. return 0;
  249. }
  250. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  251. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  252. /* What do these sleeps do?? */
  253. p.tv_sec = 0;
  254. p.tv_nsec = AVALON_RESET_PITCH;
  255. nanosleep(&p, NULL);
  256. /* Look for the first occurrence of 0xAA, the reset response should be:
  257. * AA 55 AA 55 00 00 00 00 00 00 */
  258. spare = ret - 10;
  259. buf = tmp = (uint8_t *)&ar;
  260. if (opt_debug) {
  261. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  262. hexdump(tmp, AVALON_READ_SIZE);
  263. }
  264. for (i = 0; i <= spare; i++) {
  265. buf = &tmp[i];
  266. if (buf[0] == 0xAA)
  267. break;
  268. }
  269. i = 0;
  270. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  271. buf[2] == 0xAA && buf[3] == 0x55) {
  272. for (i = 4; i < 11; i++)
  273. if (buf[i] != 0)
  274. break;
  275. }
  276. if (i != 11) {
  277. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  278. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  279. i, buf[0], buf[1], buf[2], buf[3]);
  280. /* FIXME: return 1; */
  281. } else {
  282. /* buf[44]: minor
  283. * buf[45]: day
  284. * buf[46]: year,month, d6: 201306
  285. */
  286. info->ctlr_ver = ((buf[46] >> 4) + 2000) * 1000000 +
  287. (buf[46] & 0x0f) * 10000 +
  288. buf[45] * 100 + buf[44];
  289. applog(LOG_WARNING, "%s%d: Reset succeeded (Controller version: %d)",
  290. avalon->drv->name, avalon->device_id, info->ctlr_ver);
  291. }
  292. return 0;
  293. }
  294. static int avalon_calc_timeout(int frequency)
  295. {
  296. return AVALON_TIMEOUT_FACTOR / frequency;
  297. }
  298. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  299. int *asic_count, int *timeout, int *frequency)
  300. {
  301. char buf[BUFSIZ+1];
  302. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  303. bool timeout_default;
  304. size_t max;
  305. int i, tmp;
  306. if (opt_avalon_options == NULL)
  307. buf[0] = '\0';
  308. else {
  309. ptr = opt_avalon_options;
  310. for (i = 0; i < this_option_offset; i++) {
  311. comma = strchr(ptr, ',');
  312. if (comma == NULL)
  313. break;
  314. ptr = comma + 1;
  315. }
  316. comma = strchr(ptr, ',');
  317. if (comma == NULL)
  318. max = strlen(ptr);
  319. else
  320. max = comma - ptr;
  321. if (max > BUFSIZ)
  322. max = BUFSIZ;
  323. strncpy(buf, ptr, max);
  324. buf[max] = '\0';
  325. }
  326. if (!(*buf))
  327. return false;
  328. colon = strchr(buf, ':');
  329. if (colon)
  330. *(colon++) = '\0';
  331. tmp = atoi(buf);
  332. switch (tmp) {
  333. case 115200:
  334. *baud = 115200;
  335. break;
  336. case 57600:
  337. *baud = 57600;
  338. break;
  339. case 38400:
  340. *baud = 38400;
  341. break;
  342. case 19200:
  343. *baud = 19200;
  344. break;
  345. default:
  346. quit(1, "Invalid avalon-options for baud (%s) "
  347. "must be 115200, 57600, 38400 or 19200", buf);
  348. }
  349. if (colon && *colon) {
  350. colon2 = strchr(colon, ':');
  351. if (colon2)
  352. *(colon2++) = '\0';
  353. if (*colon) {
  354. tmp = atoi(colon);
  355. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  356. *miner_count = tmp;
  357. } else {
  358. quit(1, "Invalid avalon-options for "
  359. "miner_count (%s) must be 1 ~ %d",
  360. colon, AVALON_DEFAULT_MINER_NUM);
  361. }
  362. }
  363. if (colon2 && *colon2) {
  364. colon3 = strchr(colon2, ':');
  365. if (colon3)
  366. *(colon3++) = '\0';
  367. tmp = atoi(colon2);
  368. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  369. *asic_count = tmp;
  370. else {
  371. quit(1, "Invalid avalon-options for "
  372. "asic_count (%s) must be 1 ~ %d",
  373. colon2, AVALON_DEFAULT_ASIC_NUM);
  374. }
  375. timeout_default = false;
  376. if (colon3 && *colon3) {
  377. colon4 = strchr(colon3, ':');
  378. if (colon4)
  379. *(colon4++) = '\0';
  380. if (tolower(*colon3) == 'd')
  381. timeout_default = true;
  382. else {
  383. tmp = atoi(colon3);
  384. if (tmp > 0 && tmp <= 0xff)
  385. *timeout = tmp;
  386. else {
  387. quit(1, "Invalid avalon-options for "
  388. "timeout (%s) must be 1 ~ %d",
  389. colon3, 0xff);
  390. }
  391. }
  392. if (colon4 && *colon4) {
  393. tmp = atoi(colon4);
  394. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  395. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  396. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  397. }
  398. *frequency = tmp;
  399. if (timeout_default)
  400. *timeout = avalon_calc_timeout(*frequency);
  401. }
  402. }
  403. }
  404. }
  405. return true;
  406. }
  407. char *set_avalon_fan(char *arg)
  408. {
  409. int val1, val2, ret;
  410. ret = sscanf(arg, "%d-%d", &val1, &val2);
  411. if (ret < 1)
  412. return "No values passed to avalon-fan";
  413. if (ret == 1)
  414. val2 = val1;
  415. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  416. return "Invalid value passed to avalon-fan";
  417. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  418. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  419. return NULL;
  420. }
  421. char *set_avalon_freq(char *arg)
  422. {
  423. int val1, val2, ret;
  424. ret = sscanf(arg, "%d-%d", &val1, &val2);
  425. if (ret < 1)
  426. return "No values passed to avalon-freq";
  427. if (ret == 1)
  428. val2 = val1;
  429. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  430. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  431. val2 < val1)
  432. return "Invalid value passed to avalon-freq";
  433. opt_avalon_freq_min = val1;
  434. opt_avalon_freq_max = val2;
  435. return NULL;
  436. }
  437. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  438. {
  439. int i;
  440. wait_avalon_ready(avalon);
  441. /* Send idle to all miners */
  442. for (i = 0; i < info->miner_count; i++) {
  443. struct avalon_task at;
  444. if (unlikely(avalon_buffer_full(avalon)))
  445. break;
  446. info->idle++;
  447. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  448. info->asic_count, info->miner_count, 1, 1,
  449. info->frequency);
  450. avalon_send_task(&at, avalon);
  451. }
  452. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  453. wait_avalon_ready(avalon);
  454. }
  455. static void avalon_initialise(struct cgpu_info *avalon)
  456. {
  457. int err, interface;
  458. if (avalon->usbinfo.nodev)
  459. return;
  460. interface = usb_interface(avalon);
  461. // Reset
  462. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  463. FTDI_VALUE_RESET, interface, C_RESET);
  464. applog(LOG_DEBUG, "%s%i: reset got err %d",
  465. avalon->drv->name, avalon->device_id, err);
  466. if (avalon->usbinfo.nodev)
  467. return;
  468. // Set latency
  469. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  470. AVALON_LATENCY, interface, C_LATENCY);
  471. applog(LOG_DEBUG, "%s%i: latency got err %d",
  472. avalon->drv->name, avalon->device_id, err);
  473. if (avalon->usbinfo.nodev)
  474. return;
  475. // Set data
  476. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  477. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  478. applog(LOG_DEBUG, "%s%i: data got err %d",
  479. avalon->drv->name, avalon->device_id, err);
  480. if (avalon->usbinfo.nodev)
  481. return;
  482. // Set the baud
  483. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  484. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  485. C_SETBAUD);
  486. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  487. avalon->drv->name, avalon->device_id, err);
  488. if (avalon->usbinfo.nodev)
  489. return;
  490. // Set Modem Control
  491. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  492. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  493. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  494. avalon->drv->name, avalon->device_id, err);
  495. if (avalon->usbinfo.nodev)
  496. return;
  497. // Set Flow Control
  498. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  499. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  500. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  501. avalon->drv->name, avalon->device_id, err);
  502. if (avalon->usbinfo.nodev)
  503. return;
  504. /* Avalon repeats the following */
  505. // Set Modem Control
  506. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  507. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  508. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  509. avalon->drv->name, avalon->device_id, err);
  510. if (avalon->usbinfo.nodev)
  511. return;
  512. // Set Flow Control
  513. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  514. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  515. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  516. avalon->drv->name, avalon->device_id, err);
  517. }
  518. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  519. {
  520. uint8_t buf[2];
  521. int err;
  522. if (usb_ident(avalon) == IDENT_BTB) {
  523. buf[0] = (uint8_t)core_voltage;
  524. buf[1] = (uint8_t)(core_voltage >> 8);
  525. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  526. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  527. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  528. if (unlikely(err < 0)) {
  529. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  530. avalon->drv->name, avalon->device_id, err);
  531. return false;
  532. } else {
  533. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  534. avalon->drv->name, avalon->device_id,
  535. core_voltage);
  536. }
  537. return true;
  538. }
  539. return false;
  540. }
  541. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  542. {
  543. uint8_t buf[2];
  544. int err;
  545. int amount;
  546. if (usb_ident(avalon) == IDENT_BTB) {
  547. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  548. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  549. (char *)buf, sizeof(buf), &amount,
  550. C_BB_GET_VOLTAGE);
  551. if (unlikely(err != 0 || amount != 2)) {
  552. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  553. avalon->drv->name, avalon->device_id, err, amount);
  554. return 0;
  555. } else {
  556. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  557. }
  558. } else {
  559. return 0;
  560. }
  561. }
  562. static void bitburner_get_version(struct cgpu_info *avalon)
  563. {
  564. struct avalon_info *info = avalon->device_data;
  565. uint8_t buf[3];
  566. int err;
  567. int amount;
  568. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  569. BITBURNER_VALUE, BITBURNER_INDEX_GET_VERSION,
  570. (char *)buf, sizeof(buf), &amount,
  571. C_GETVERSION);
  572. if (unlikely(err != 0 || amount != sizeof(buf))) {
  573. applog(LOG_DEBUG, "%s%i: GetVersion failed: err=%d, amt=%d assuming %d.%d.%d",
  574. avalon->drv->name, avalon->device_id, err, amount,
  575. BITBURNER_VERSION1, BITBURNER_VERSION2, BITBURNER_VERSION3);
  576. info->version1 = BITBURNER_VERSION1;
  577. info->version2 = BITBURNER_VERSION2;
  578. info->version3 = BITBURNER_VERSION3;
  579. } else {
  580. info->version1 = buf[0];
  581. info->version2 = buf[1];
  582. info->version3 = buf[2];
  583. }
  584. }
  585. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  586. {
  587. int baud, miner_count, asic_count, timeout, frequency;
  588. int this_option_offset = ++option_offset;
  589. struct avalon_info *info;
  590. struct cgpu_info *avalon;
  591. bool configured;
  592. int ret;
  593. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  594. baud = AVALON_IO_SPEED;
  595. miner_count = AVALON_DEFAULT_MINER_NUM;
  596. asic_count = AVALON_DEFAULT_ASIC_NUM;
  597. timeout = AVALON_DEFAULT_TIMEOUT;
  598. frequency = AVALON_DEFAULT_FREQUENCY;
  599. configured = get_options(this_option_offset, &baud, &miner_count,
  600. &asic_count, &timeout, &frequency);
  601. if (!usb_init(avalon, dev, found))
  602. goto shin;
  603. /* Even though this is an FTDI type chip, we want to do the parsing
  604. * all ourselves so set it to std usb type */
  605. avalon->usbdev->usb_type = USB_TYPE_STD;
  606. usb_set_pps(avalon, AVALON_USB_PACKETSIZE);
  607. /* We have a real Avalon! */
  608. avalon_initialise(avalon);
  609. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  610. if (unlikely(!(avalon->device_data)))
  611. quit(1, "Failed to calloc avalon_info data");
  612. info = avalon->device_data;
  613. if (configured) {
  614. info->baud = baud;
  615. info->miner_count = miner_count;
  616. info->asic_count = asic_count;
  617. info->timeout = timeout;
  618. info->frequency = frequency;
  619. } else {
  620. info->baud = AVALON_IO_SPEED;
  621. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  622. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  623. info->timeout = AVALON_DEFAULT_TIMEOUT;
  624. info->frequency = AVALON_DEFAULT_FREQUENCY;
  625. }
  626. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  627. info->temp_max = 0;
  628. /* This is for check the temp/fan every 3~4s */
  629. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  630. if (info->temp_history_count <= 0)
  631. info->temp_history_count = 1;
  632. info->temp_history_index = 0;
  633. info->temp_sum = 0;
  634. info->temp_old = 0;
  635. if (!add_cgpu(avalon))
  636. goto unshin;
  637. ret = avalon_reset(avalon, true);
  638. if (ret && !configured)
  639. goto unshin;
  640. update_usb_stats(avalon);
  641. avalon_idle(avalon, info);
  642. applog(LOG_DEBUG, "Avalon Detected: %s "
  643. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  644. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  645. info->frequency);
  646. if (usb_ident(avalon) == IDENT_BTB) {
  647. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  648. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  649. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  650. opt_bitburner_core_voltage,
  651. BITBURNER_MIN_COREMV,
  652. BITBURNER_MAX_COREMV);
  653. } else
  654. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  655. bitburner_get_version(avalon);
  656. }
  657. return true;
  658. unshin:
  659. usb_uninit(avalon);
  660. shin:
  661. free(avalon->device_data);
  662. avalon->device_data = NULL;
  663. avalon = usb_free_cgpu(avalon);
  664. return false;
  665. }
  666. static void avalon_detect(bool __maybe_unused hotplug)
  667. {
  668. usb_detect(&avalon_drv, avalon_detect_one);
  669. }
  670. static void avalon_init(struct cgpu_info *avalon)
  671. {
  672. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  673. }
  674. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  675. {
  676. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  677. (char *)ar->data, 64, 12);
  678. }
  679. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  680. struct avalon_result *ar);
  681. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  682. {
  683. applog(LOG_INFO, "%s%d: No matching work - HW error",
  684. thr->cgpu->drv->name, thr->cgpu->device_id);
  685. inc_hw_errors(thr);
  686. info->no_matching_work++;
  687. }
  688. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  689. struct thr_info *thr, char *buf, int *offset)
  690. {
  691. int i, spare = *offset - AVALON_READ_SIZE;
  692. bool found = false;
  693. for (i = 0; i <= spare; i++) {
  694. struct avalon_result *ar;
  695. struct work *work;
  696. ar = (struct avalon_result *)&buf[i];
  697. work = avalon_valid_result(avalon, ar);
  698. if (work) {
  699. bool gettemp = false;
  700. found = true;
  701. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  702. mutex_lock(&info->lock);
  703. if (!info->nonces++)
  704. gettemp = true;
  705. info->auto_nonces++;
  706. mutex_unlock(&info->lock);
  707. } else if (opt_avalon_auto) {
  708. mutex_lock(&info->lock);
  709. info->auto_hw++;
  710. mutex_unlock(&info->lock);
  711. }
  712. free_work(work);
  713. if (gettemp)
  714. avalon_update_temps(avalon, info, ar);
  715. break;
  716. }
  717. }
  718. if (!found) {
  719. spare = *offset - AVALON_READ_SIZE;
  720. /* We are buffering and haven't accumulated one more corrupt
  721. * work result. */
  722. if (spare < (int)AVALON_READ_SIZE)
  723. return;
  724. avalon_inc_nvw(info, thr);
  725. } else {
  726. spare = AVALON_READ_SIZE + i;
  727. if (i) {
  728. if (i >= (int)AVALON_READ_SIZE)
  729. avalon_inc_nvw(info, thr);
  730. else
  731. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  732. }
  733. }
  734. *offset -= spare;
  735. memmove(buf, buf + spare, *offset);
  736. }
  737. static void avalon_running_reset(struct cgpu_info *avalon,
  738. struct avalon_info *info)
  739. {
  740. avalon_reset(avalon, false);
  741. avalon_idle(avalon, info);
  742. avalon->results = 0;
  743. info->reset = false;
  744. }
  745. static void *avalon_get_results(void *userdata)
  746. {
  747. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  748. struct avalon_info *info = avalon->device_data;
  749. const int rsize = AVALON_FTDI_READSIZE;
  750. char readbuf[AVALON_READBUF_SIZE];
  751. struct thr_info *thr = info->thr;
  752. cgtimer_t ts_start;
  753. int offset = 0, ret = 0;
  754. char threadname[24];
  755. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  756. RenameThread(threadname);
  757. cgsleep_prepare_r(&ts_start);
  758. while (likely(!avalon->shutdown)) {
  759. unsigned char buf[rsize];
  760. if (offset >= (int)AVALON_READ_SIZE)
  761. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  762. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  763. /* This should never happen */
  764. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  765. offset = 0;
  766. }
  767. if (unlikely(info->reset)) {
  768. avalon_running_reset(avalon, info);
  769. /* Discard anything in the buffer */
  770. offset = 0;
  771. }
  772. /* As the usb read returns after just 1ms, sleep long enough
  773. * to leave the interface idle for writes to occur, but do not
  774. * sleep if we have been receiving data, and we do not yet have
  775. * a full result as more may be coming. */
  776. if (ret < 1 || offset == 0)
  777. cgsleep_ms_r(&ts_start, AVALON_READ_TIMEOUT);
  778. cgsleep_prepare_r(&ts_start);
  779. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  780. C_AVALON_READ);
  781. if (ret < 1)
  782. continue;
  783. if (opt_debug) {
  784. applog(LOG_DEBUG, "Avalon: get:");
  785. hexdump((uint8_t *)buf, ret);
  786. }
  787. memcpy(&readbuf[offset], &buf, ret);
  788. offset += ret;
  789. }
  790. return NULL;
  791. }
  792. static void avalon_rotate_array(struct cgpu_info *avalon)
  793. {
  794. avalon->queued = 0;
  795. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  796. avalon->work_array = 0;
  797. }
  798. static void bitburner_rotate_array(struct cgpu_info *avalon)
  799. {
  800. avalon->queued = 0;
  801. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  802. avalon->work_array = 0;
  803. }
  804. static void avalon_set_timeout(struct avalon_info *info)
  805. {
  806. info->timeout = avalon_calc_timeout(info->frequency);
  807. }
  808. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  809. {
  810. struct avalon_info *info = avalon->device_data;
  811. info->frequency = frequency;
  812. if (info->frequency > opt_avalon_freq_max)
  813. info->frequency = opt_avalon_freq_max;
  814. if (info->frequency < opt_avalon_freq_min)
  815. info->frequency = opt_avalon_freq_min;
  816. avalon_set_timeout(info);
  817. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  818. avalon->drv->name, avalon->device_id,
  819. info->frequency, info->timeout);
  820. }
  821. static void avalon_inc_freq(struct avalon_info *info)
  822. {
  823. info->frequency += 2;
  824. if (info->frequency > opt_avalon_freq_max)
  825. info->frequency = opt_avalon_freq_max;
  826. avalon_set_timeout(info);
  827. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  828. info->frequency, info->timeout);
  829. }
  830. static void avalon_dec_freq(struct avalon_info *info)
  831. {
  832. info->frequency -= 1;
  833. if (info->frequency < opt_avalon_freq_min)
  834. info->frequency = opt_avalon_freq_min;
  835. avalon_set_timeout(info);
  836. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  837. info->frequency, info->timeout);
  838. }
  839. static void avalon_reset_auto(struct avalon_info *info)
  840. {
  841. info->auto_queued =
  842. info->auto_nonces =
  843. info->auto_hw = 0;
  844. }
  845. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  846. {
  847. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  848. mutex_lock(&info->lock);
  849. if (!info->optimal) {
  850. if (info->fan_pwm >= opt_avalon_fan_max) {
  851. applog(LOG_WARNING,
  852. "%s%i: Above optimal temperature, throttling",
  853. avalon->drv->name, avalon->device_id);
  854. avalon_dec_freq(info);
  855. }
  856. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  857. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  858. int total = info->auto_nonces + info->auto_hw;
  859. /* Try to keep hw errors < 2% */
  860. if (info->auto_hw * 100 < total)
  861. avalon_inc_freq(info);
  862. else if (info->auto_hw * 66 > total)
  863. avalon_dec_freq(info);
  864. }
  865. avalon_reset_auto(info);
  866. mutex_unlock(&info->lock);
  867. }
  868. }
  869. static void *avalon_send_tasks(void *userdata)
  870. {
  871. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  872. struct avalon_info *info = avalon->device_data;
  873. const int avalon_get_work_count = info->miner_count;
  874. char threadname[24];
  875. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  876. RenameThread(threadname);
  877. while (likely(!avalon->shutdown)) {
  878. int start_count, end_count, i, j, ret;
  879. cgtimer_t ts_start;
  880. struct avalon_task at;
  881. bool idled = false;
  882. int64_t us_timeout;
  883. while (avalon_buffer_full(avalon))
  884. cgsleep_ms(40);
  885. avalon_adjust_freq(info, avalon);
  886. /* A full nonce range */
  887. us_timeout = 0x100000000ll / info->asic_count / info->frequency;
  888. cgsleep_prepare_r(&ts_start);
  889. mutex_lock(&info->qlock);
  890. start_count = avalon->work_array * avalon_get_work_count;
  891. end_count = start_count + avalon_get_work_count;
  892. for (i = start_count, j = 0; i < end_count; i++, j++) {
  893. if (avalon_buffer_full(avalon)) {
  894. applog(LOG_INFO,
  895. "%s%i: Buffer full after only %d of %d work queued",
  896. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  897. break;
  898. }
  899. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  900. avalon_init_task(&at, 0, 0, info->fan_pwm,
  901. info->timeout, info->asic_count,
  902. info->miner_count, 1, 0, info->frequency);
  903. avalon_create_task(&at, avalon->works[i]);
  904. info->auto_queued++;
  905. } else {
  906. int idle_freq = info->frequency;
  907. if (!info->idle++)
  908. idled = true;
  909. if (unlikely(info->overheat && opt_avalon_auto))
  910. idle_freq = AVALON_MIN_FREQUENCY;
  911. avalon_init_task(&at, 0, 0, info->fan_pwm,
  912. info->timeout, info->asic_count,
  913. info->miner_count, 1, 1, idle_freq);
  914. /* Reset the auto_queued count if we end up
  915. * idling any miners. */
  916. avalon_reset_auto(info);
  917. }
  918. ret = avalon_send_task(&at, avalon);
  919. if (unlikely(ret == AVA_SEND_ERROR)) {
  920. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  921. avalon->drv->name, avalon->device_id);
  922. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  923. info->reset = true;
  924. break;
  925. }
  926. }
  927. avalon_rotate_array(avalon);
  928. pthread_cond_signal(&info->qcond);
  929. mutex_unlock(&info->qlock);
  930. if (unlikely(idled)) {
  931. applog(LOG_WARNING, "%s%i: Idled %d miners",
  932. avalon->drv->name, avalon->device_id, idled);
  933. }
  934. /* Sleep how long it would take to complete a full nonce range
  935. * at the current frequency using the clock_nanosleep function
  936. * timed from before we started loading new work so it will
  937. * fall short of the full duration. */
  938. cgsleep_us_r(&ts_start, us_timeout);
  939. }
  940. return NULL;
  941. }
  942. static void *bitburner_send_tasks(void *userdata)
  943. {
  944. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  945. struct avalon_info *info = avalon->device_data;
  946. const int avalon_get_work_count = info->miner_count;
  947. char threadname[24];
  948. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  949. RenameThread(threadname);
  950. while (likely(!avalon->shutdown)) {
  951. int start_count, end_count, i, j, ret;
  952. struct avalon_task at;
  953. bool idled = false;
  954. while (avalon_buffer_full(avalon))
  955. cgsleep_ms(40);
  956. avalon_adjust_freq(info, avalon);
  957. /* Give other threads a chance to acquire qlock. */
  958. i = 0;
  959. do {
  960. cgsleep_ms(40);
  961. } while (!avalon->shutdown && i++ < 15
  962. && avalon->queued < avalon_get_work_count);
  963. mutex_lock(&info->qlock);
  964. start_count = avalon->work_array * avalon_get_work_count;
  965. end_count = start_count + avalon_get_work_count;
  966. for (i = start_count, j = 0; i < end_count; i++, j++) {
  967. while (avalon_buffer_full(avalon))
  968. cgsleep_ms(40);
  969. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  970. avalon_init_task(&at, 0, 0, info->fan_pwm,
  971. info->timeout, info->asic_count,
  972. info->miner_count, 1, 0, info->frequency);
  973. avalon_create_task(&at, avalon->works[i]);
  974. info->auto_queued++;
  975. } else {
  976. int idle_freq = info->frequency;
  977. if (!info->idle++)
  978. idled = true;
  979. if (unlikely(info->overheat && opt_avalon_auto))
  980. idle_freq = AVALON_MIN_FREQUENCY;
  981. avalon_init_task(&at, 0, 0, info->fan_pwm,
  982. info->timeout, info->asic_count,
  983. info->miner_count, 1, 1, idle_freq);
  984. /* Reset the auto_queued count if we end up
  985. * idling any miners. */
  986. avalon_reset_auto(info);
  987. }
  988. ret = avalon_send_task(&at, avalon);
  989. if (unlikely(ret == AVA_SEND_ERROR)) {
  990. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  991. avalon->drv->name, avalon->device_id);
  992. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  993. info->reset = true;
  994. break;
  995. }
  996. }
  997. bitburner_rotate_array(avalon);
  998. pthread_cond_signal(&info->qcond);
  999. mutex_unlock(&info->qlock);
  1000. if (unlikely(idled)) {
  1001. applog(LOG_WARNING, "%s%i: Idled %d miners",
  1002. avalon->drv->name, avalon->device_id, idled);
  1003. }
  1004. }
  1005. return NULL;
  1006. }
  1007. static bool avalon_prepare(struct thr_info *thr)
  1008. {
  1009. struct cgpu_info *avalon = thr->cgpu;
  1010. struct avalon_info *info = avalon->device_data;
  1011. int array_size = AVALON_ARRAY_SIZE;
  1012. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  1013. if (usb_ident(avalon) == IDENT_BTB) {
  1014. array_size = BITBURNER_ARRAY_SIZE;
  1015. write_thread_fn = bitburner_send_tasks;
  1016. }
  1017. free(avalon->works);
  1018. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  1019. array_size);
  1020. if (!avalon->works)
  1021. quit(1, "Failed to calloc avalon works in avalon_prepare");
  1022. info->thr = thr;
  1023. mutex_init(&info->lock);
  1024. mutex_init(&info->qlock);
  1025. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1026. quit(1, "Failed to pthread_cond_init avalon qcond");
  1027. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  1028. quit(1, "Failed to create avalon read_thr");
  1029. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  1030. quit(1, "Failed to create avalon write_thr");
  1031. avalon_init(avalon);
  1032. return true;
  1033. }
  1034. static void do_avalon_close(struct thr_info *thr)
  1035. {
  1036. struct cgpu_info *avalon = thr->cgpu;
  1037. struct avalon_info *info = avalon->device_data;
  1038. pthread_join(info->read_thr, NULL);
  1039. pthread_join(info->write_thr, NULL);
  1040. avalon_running_reset(avalon, info);
  1041. info->no_matching_work = 0;
  1042. }
  1043. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  1044. {
  1045. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1046. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1047. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1048. info->temp0 = ar->temp0;
  1049. info->temp1 = ar->temp1;
  1050. info->temp2 = ar->temp2;
  1051. if (ar->temp0 & 0x80) {
  1052. ar->temp0 &= 0x7f;
  1053. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1054. }
  1055. if (ar->temp1 & 0x80) {
  1056. ar->temp1 &= 0x7f;
  1057. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1058. }
  1059. if (ar->temp2 & 0x80) {
  1060. ar->temp2 &= 0x7f;
  1061. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1062. }
  1063. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  1064. if (info->temp0 > info->temp_max)
  1065. info->temp_max = info->temp0;
  1066. if (info->temp1 > info->temp_max)
  1067. info->temp_max = info->temp1;
  1068. if (info->temp2 > info->temp_max)
  1069. info->temp_max = info->temp2;
  1070. }
  1071. static void temp_rise(struct avalon_info *info, int temp)
  1072. {
  1073. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1074. info->fan_pwm = AVALON_PWM_MAX;
  1075. return;
  1076. }
  1077. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1078. info->fan_pwm += 10;
  1079. else if (temp > opt_avalon_temp)
  1080. info->fan_pwm += 5;
  1081. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1082. info->fan_pwm += 1;
  1083. else
  1084. return;
  1085. if (info->fan_pwm > opt_avalon_fan_max)
  1086. info->fan_pwm = opt_avalon_fan_max;
  1087. }
  1088. static void temp_drop(struct avalon_info *info, int temp)
  1089. {
  1090. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1091. info->fan_pwm = opt_avalon_fan_min;
  1092. return;
  1093. }
  1094. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1095. info->fan_pwm -= 10;
  1096. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1097. info->fan_pwm -= 5;
  1098. else if (temp < opt_avalon_temp)
  1099. info->fan_pwm -= 1;
  1100. if (info->fan_pwm < opt_avalon_fan_min)
  1101. info->fan_pwm = opt_avalon_fan_min;
  1102. }
  1103. static inline void adjust_fan(struct avalon_info *info)
  1104. {
  1105. int temp_new;
  1106. temp_new = info->temp_sum / info->temp_history_count;
  1107. if (temp_new > info->temp_old)
  1108. temp_rise(info, temp_new);
  1109. else if (temp_new < info->temp_old)
  1110. temp_drop(info, temp_new);
  1111. else {
  1112. /* temp_new == info->temp_old */
  1113. if (temp_new > opt_avalon_temp)
  1114. temp_rise(info, temp_new);
  1115. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1116. temp_drop(info, temp_new);
  1117. }
  1118. info->temp_old = temp_new;
  1119. if (info->temp_old <= opt_avalon_temp)
  1120. info->optimal = true;
  1121. else
  1122. info->optimal = false;
  1123. }
  1124. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1125. struct avalon_result *ar)
  1126. {
  1127. record_temp_fan(info, ar, &(avalon->temp));
  1128. applog(LOG_INFO,
  1129. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1130. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1131. info->fan0, info->fan1, info->fan2,
  1132. info->temp0, info->temp1, info->temp2, info->temp_max);
  1133. info->temp_history_index++;
  1134. info->temp_sum += avalon->temp;
  1135. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1136. info->temp_history_index, info->temp_history_count, info->temp_old);
  1137. if (usb_ident(avalon) == IDENT_BTB) {
  1138. info->core_voltage = bitburner_get_core_voltage(avalon);
  1139. }
  1140. if (info->temp_history_index == info->temp_history_count) {
  1141. adjust_fan(info);
  1142. info->temp_history_index = 0;
  1143. info->temp_sum = 0;
  1144. }
  1145. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1146. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1147. info->overheat = true;
  1148. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1149. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1150. info->overheat = false;
  1151. }
  1152. }
  1153. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1154. {
  1155. struct avalon_info *info = avalon->device_data;
  1156. int lowfan = 10000;
  1157. if (usb_ident(avalon) == IDENT_BTB) {
  1158. int temp = info->temp0;
  1159. if (info->temp2 > temp)
  1160. temp = info->temp2;
  1161. if (temp > 99)
  1162. temp = 99;
  1163. if (temp < 0)
  1164. temp = 0;
  1165. tailsprintf(buf, bufsiz, "%2dC %3d %4dmV | ", temp, info->frequency, info->core_voltage);
  1166. } else {
  1167. /* Find the lowest fan speed of the ASIC cooling fans. */
  1168. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1169. lowfan = info->fan1;
  1170. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1171. lowfan = info->fan2;
  1172. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1173. }
  1174. }
  1175. /* We use a replacement algorithm to only remove references to work done from
  1176. * the buffer when we need the extra space for new work. */
  1177. static bool avalon_fill(struct cgpu_info *avalon)
  1178. {
  1179. struct avalon_info *info = avalon->device_data;
  1180. int subid, slot, mc;
  1181. struct work *work;
  1182. bool ret = true;
  1183. mc = info->miner_count;
  1184. mutex_lock(&info->qlock);
  1185. if (avalon->queued >= mc)
  1186. goto out_unlock;
  1187. work = get_queued(avalon);
  1188. if (unlikely(!work)) {
  1189. ret = false;
  1190. goto out_unlock;
  1191. }
  1192. subid = avalon->queued++;
  1193. work->subid = subid;
  1194. slot = avalon->work_array * mc + subid;
  1195. if (likely(avalon->works[slot]))
  1196. work_completed(avalon, avalon->works[slot]);
  1197. avalon->works[slot] = work;
  1198. if (avalon->queued < mc)
  1199. ret = false;
  1200. out_unlock:
  1201. mutex_unlock(&info->qlock);
  1202. return ret;
  1203. }
  1204. static int64_t avalon_scanhash(struct thr_info *thr)
  1205. {
  1206. struct cgpu_info *avalon = thr->cgpu;
  1207. struct avalon_info *info = avalon->device_data;
  1208. const int miner_count = info->miner_count;
  1209. struct timeval now, then, tdiff;
  1210. int64_t hash_count, us_timeout;
  1211. struct timespec abstime;
  1212. /* Half nonce range */
  1213. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1214. us_to_timeval(&tdiff, us_timeout);
  1215. cgtime(&now);
  1216. timeradd(&now, &tdiff, &then);
  1217. timeval_to_spec(&abstime, &then);
  1218. /* Wait until avalon_send_tasks signals us that it has completed
  1219. * sending its work or a full nonce range timeout has occurred */
  1220. mutex_lock(&info->qlock);
  1221. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1222. mutex_unlock(&info->qlock);
  1223. mutex_lock(&info->lock);
  1224. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1225. avalon->results += info->nonces + info->idle;
  1226. if (avalon->results > miner_count)
  1227. avalon->results = miner_count;
  1228. if (!info->reset)
  1229. avalon->results--;
  1230. info->nonces = info->idle = 0;
  1231. mutex_unlock(&info->lock);
  1232. /* Check for nothing but consecutive bad results or consistently less
  1233. * results than we should be getting and reset the FPGA if necessary */
  1234. if (usb_ident(avalon) != IDENT_BTB) {
  1235. if (avalon->results < -miner_count && !info->reset) {
  1236. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1237. avalon->drv->name, avalon->device_id);
  1238. info->reset = true;
  1239. }
  1240. }
  1241. if (unlikely(avalon->usbinfo.nodev)) {
  1242. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1243. avalon->drv->name, avalon->device_id);
  1244. avalon->shutdown = true;
  1245. }
  1246. /* This hashmeter is just a utility counter based on returned shares */
  1247. return hash_count;
  1248. }
  1249. static void avalon_flush_work(struct cgpu_info *avalon)
  1250. {
  1251. struct avalon_info *info = avalon->device_data;
  1252. mutex_lock(&info->qlock);
  1253. /* Will overwrite any work queued */
  1254. avalon->queued = 0;
  1255. pthread_cond_signal(&info->qcond);
  1256. mutex_unlock(&info->qlock);
  1257. }
  1258. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1259. {
  1260. struct api_data *root = NULL;
  1261. struct avalon_info *info = cgpu->device_data;
  1262. char buf[64];
  1263. int i;
  1264. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1265. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1266. root = api_add_int(root, "baud", &(info->baud), false);
  1267. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1268. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1269. root = api_add_int(root, "timeout", &(info->timeout), false);
  1270. root = api_add_int(root, "frequency", &(info->frequency), false);
  1271. root = api_add_int(root, "fan1", &(info->fan0), false);
  1272. root = api_add_int(root, "fan2", &(info->fan1), false);
  1273. root = api_add_int(root, "fan3", &(info->fan2), false);
  1274. root = api_add_int(root, "temp1", &(info->temp0), false);
  1275. root = api_add_int(root, "temp2", &(info->temp1), false);
  1276. root = api_add_int(root, "temp3", &(info->temp2), false);
  1277. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1278. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1279. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1280. for (i = 0; i < info->miner_count; i++) {
  1281. char mcw[24];
  1282. sprintf(mcw, "match_work_count%d", i + 1);
  1283. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1284. }
  1285. if (usb_ident(cgpu) == IDENT_BTB) {
  1286. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1287. snprintf(buf, sizeof(buf), "%"PRIu8".%"PRIu8".%"PRIu8,
  1288. info->version1, info->version2, info->version3);
  1289. root = api_add_string(root, "version", buf, true);
  1290. }
  1291. root = api_add_uint32(root, "Controller Version", &(info->ctlr_ver), false);
  1292. return root;
  1293. }
  1294. static void avalon_shutdown(struct thr_info *thr)
  1295. {
  1296. do_avalon_close(thr);
  1297. }
  1298. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1299. {
  1300. int val;
  1301. if (strcasecmp(option, "help") == 0) {
  1302. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1303. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1304. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1305. return replybuf;
  1306. }
  1307. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1308. if (usb_ident(avalon) != IDENT_BTB) {
  1309. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1310. return replybuf;
  1311. }
  1312. if (!setting || !*setting) {
  1313. sprintf(replybuf, "missing millivolts setting");
  1314. return replybuf;
  1315. }
  1316. val = atoi(setting);
  1317. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1318. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1319. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1320. return replybuf;
  1321. }
  1322. if (bitburner_set_core_voltage(avalon, val))
  1323. return NULL;
  1324. else {
  1325. sprintf(replybuf, "Set millivolts failed");
  1326. return replybuf;
  1327. }
  1328. }
  1329. if (strcasecmp(option, "freq") == 0) {
  1330. if (!setting || !*setting) {
  1331. sprintf(replybuf, "missing freq setting");
  1332. return replybuf;
  1333. }
  1334. val = atoi(setting);
  1335. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1336. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1337. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1338. return replybuf;
  1339. }
  1340. avalon_set_freq(avalon, val);
  1341. return NULL;
  1342. }
  1343. sprintf(replybuf, "Unknown option: %s", option);
  1344. return replybuf;
  1345. }
  1346. struct device_drv avalon_drv = {
  1347. .drv_id = DRIVER_avalon,
  1348. .dname = "avalon",
  1349. .name = "AVA",
  1350. .drv_detect = avalon_detect,
  1351. .thread_prepare = avalon_prepare,
  1352. .hash_work = hash_queued_work,
  1353. .queue_full = avalon_fill,
  1354. .scanwork = avalon_scanhash,
  1355. .flush_work = avalon_flush_work,
  1356. .get_api_stats = avalon_api_stats,
  1357. .get_statline_before = get_avalon_statline_before,
  1358. .set_device = avalon_set_device,
  1359. .reinit_device = avalon_init,
  1360. .thread_shutdown = avalon_shutdown,
  1361. };