driver-avalon.c 19 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p,
  40. uint8_t miner_num_p)
  41. {
  42. static bool first = true;
  43. uint8_t timeout;
  44. uint8_t asic_num;
  45. uint8_t miner_num;
  46. struct cgpu_info *avalon;
  47. struct avalon_info *info;
  48. if (!at)
  49. return -1;
  50. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  51. return -1;
  52. timeout = timeout_p;
  53. miner_num = miner_num_p;
  54. asic_num = asic_num_p;
  55. if (thr) {
  56. avalon = thr->cgpu;
  57. info = avalon_info[avalon->device_id];
  58. timeout = info->timeout;
  59. miner_num = info->miner_count;
  60. asic_num = info->asic_count;
  61. }
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (reset) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (first && !at->reset) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = 1;
  81. return 0;
  82. }
  83. static inline void avalon_create_task(struct avalon_task *at,
  84. struct work *work)
  85. {
  86. memcpy(at->midstate, work->midstate, 32);
  87. memcpy(at->data, work->data + 64, 12);
  88. }
  89. static int avalon_send_task(int fd, const struct avalon_task *at,
  90. struct thr_info *thr)
  91. {
  92. size_t ret;
  93. int full;
  94. struct timespec p;
  95. uint8_t *buf;
  96. size_t nr_len;
  97. struct cgpu_info *avalon;
  98. struct avalon_info *info;
  99. uint64_t delay = 32000000; /* default 32ms for B19200 */
  100. uint32_t nonce_range;
  101. int i;
  102. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  103. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  104. if (!buf)
  105. return AVA_SEND_ERROR;
  106. memcpy(buf, at, AVALON_WRITE_SIZE);
  107. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  108. /* FIXME: the nonce_range */
  109. for (i = 0; i < at->asic_num; i++) {
  110. buf[AVALON_WRITE_SIZE + (i * 4) + 0] = (i * nonce_range & 0xff000000) >> 24;
  111. buf[AVALON_WRITE_SIZE + (i * 4) + 1] = (i * nonce_range & 0x00ff0000) >> 16;
  112. buf[AVALON_WRITE_SIZE + (i * 4) + 2] = (i * nonce_range & 0x0000ff00) >> 8;
  113. buf[AVALON_WRITE_SIZE + (i * 4) + 3] = (i * nonce_range & 0x000000ff) >> 0;
  114. }
  115. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  116. uint8_t tt = 0;
  117. tt = (buf[0] & 0x0f) << 4;
  118. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  119. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  120. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  121. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  122. buf[0] = tt;
  123. buf[4] = rev8(buf[4]);
  124. #endif
  125. if (opt_debug) {
  126. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  127. hexdump((uint8_t *)buf, nr_len);
  128. }
  129. ret = write(fd, buf, nr_len);
  130. free(buf);
  131. if (unlikely(ret != nr_len))
  132. return AVA_SEND_ERROR;
  133. if (thr) {
  134. avalon = thr->cgpu;
  135. info = avalon_info[avalon->device_id];
  136. delay = nr_len * 10 * 1000000000ULL;
  137. delay = delay / info->baud;
  138. }
  139. p.tv_sec = 0;
  140. p.tv_nsec = (long)delay + 4000000;
  141. nanosleep(&p, NULL);
  142. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  143. full = avalon_buffer_full(fd);
  144. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  145. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  146. if (full == AVA_BUFFER_EMPTY)
  147. return AVA_SEND_BUFFER_EMPTY;
  148. return AVA_SEND_BUFFER_FULL;
  149. }
  150. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  151. struct thr_info *thr, struct timeval *tv_finish)
  152. {
  153. ssize_t ret = 0;
  154. int rc = 0;
  155. int read_amount = AVALON_READ_SIZE;
  156. bool first = true;
  157. /* Read reply 1 byte at a time to get earliest tv_finish */
  158. while (true) {
  159. ret = read(fd, buf, 1);
  160. if (ret < 0)
  161. return AVA_GETS_ERROR;
  162. if (first && tv_finish != NULL)
  163. gettimeofday(tv_finish, NULL);
  164. if (ret >= read_amount)
  165. return AVA_GETS_OK;
  166. if (ret > 0) {
  167. buf += ret;
  168. read_amount -= ret;
  169. first = false;
  170. continue;
  171. }
  172. rc++;
  173. if (rc >= read_count) {
  174. if (opt_debug) {
  175. applog(LOG_ERR,
  176. "Avalon: No data in %.2f seconds",
  177. (float)rc/(float)TIME_FACTOR);
  178. }
  179. return AVA_GETS_TIMEOUT;
  180. }
  181. if (thr && thr->work_restart) {
  182. if (opt_debug) {
  183. applog(LOG_ERR,
  184. "Avalon: Work restart at %.2f seconds",
  185. (float)(rc)/(float)TIME_FACTOR);
  186. }
  187. return AVA_GETS_RESTART;
  188. }
  189. }
  190. }
  191. static int avalon_get_result(int fd, struct avalon_result *ar,
  192. struct thr_info *thr, struct timeval *tv_finish)
  193. {
  194. struct cgpu_info *avalon;
  195. struct avalon_info *info;
  196. uint8_t result[AVALON_READ_SIZE];
  197. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  198. if (thr) {
  199. avalon = thr->cgpu;
  200. info = avalon_info[avalon->device_id];
  201. read_count = info->read_count;
  202. }
  203. memset(result, 0, AVALON_READ_SIZE);
  204. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  205. if (ret == AVA_GETS_OK) {
  206. if (opt_debug) {
  207. applog(LOG_DEBUG, "Avalon: get:");
  208. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  209. }
  210. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  211. }
  212. return ret;
  213. }
  214. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  215. struct avalon_result *ar, uint32_t *nonce)
  216. {
  217. struct cgpu_info *avalon;
  218. struct avalon_info *info;
  219. int avalon_get_work_count, i;
  220. if (!work)
  221. return -1;
  222. avalon = thr->cgpu;
  223. info = avalon_info[avalon->device_id];
  224. avalon_get_work_count = info->miner_count;
  225. for (i = 0; i < avalon_get_work_count; i++) {
  226. if (work[i] &&
  227. !memcmp(ar->data, work[i]->data + 64, 12) &&
  228. !memcmp(ar->midstate, work[i]->midstate, 32))
  229. break;
  230. }
  231. if (i == avalon_get_work_count)
  232. return -1;
  233. *nonce = ar->nonce;
  234. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  235. *nonce = swab32(*nonce);
  236. #endif
  237. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  238. return i;
  239. }
  240. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  241. uint8_t miner_num_p)
  242. {
  243. struct avalon_task at;
  244. struct avalon_result ar;
  245. uint8_t *buf;
  246. int ret, i;
  247. struct timespec p;
  248. avalon_init_task(NULL,
  249. &at, 1, 0,
  250. AVALON_DEFAULT_FAN_PWM,
  251. timeout_p, asic_num_p, miner_num_p);
  252. ret = avalon_send_task(fd, &at, NULL);
  253. if (ret == AVA_SEND_ERROR)
  254. return 1;
  255. avalon_get_result(fd, &ar, NULL, NULL);
  256. buf = (uint8_t *)&ar;
  257. for (i = 0; i < 11; i++)
  258. if (buf[i] != 0)
  259. break;
  260. /* FIXME: add more avalon info base on return */
  261. if (i != 11) {
  262. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  263. return 1;
  264. }
  265. p.tv_sec = 1;
  266. p.tv_nsec = AVALON_RESET_PITCH;
  267. nanosleep(&p, NULL);
  268. applog(LOG_ERR,
  269. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  270. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  271. applog(LOG_ERR, "Avalon: Reset succeeded");
  272. return 0;
  273. }
  274. static void do_avalon_close(struct thr_info *thr)
  275. {
  276. struct cgpu_info *avalon = thr->cgpu;
  277. avalon_close(avalon->device_fd);
  278. avalon->device_fd = -1;
  279. /* FIXME: we should free the bulk0/1/2 */
  280. }
  281. static void set_timing_mode(struct cgpu_info *avalon)
  282. {
  283. struct avalon_info *info = avalon_info[avalon->device_id];
  284. info->Hs = ((info->timeout * AVALON_HASH_TIME_FACTOR) / (double)0xffffffff);
  285. info->fullnonce = info->timeout * AVALON_HASH_TIME_FACTOR;
  286. info->read_count = ((int)(info->fullnonce * TIME_FACTOR) - 1) / info->miner_count;
  287. }
  288. static void get_options(int this_option_offset, int *baud, int *miner_count,
  289. int *asic_count, int *timeout)
  290. {
  291. char err_buf[BUFSIZ+1];
  292. char buf[BUFSIZ+1];
  293. char *ptr, *comma, *colon, *colon2, *colon3;
  294. size_t max;
  295. int i, tmp;
  296. if (opt_avalon_options == NULL)
  297. buf[0] = '\0';
  298. else {
  299. ptr = opt_avalon_options;
  300. for (i = 0; i < this_option_offset; i++) {
  301. comma = strchr(ptr, ',');
  302. if (comma == NULL)
  303. break;
  304. ptr = comma + 1;
  305. }
  306. comma = strchr(ptr, ',');
  307. if (comma == NULL)
  308. max = strlen(ptr);
  309. else
  310. max = comma - ptr;
  311. if (max > BUFSIZ)
  312. max = BUFSIZ;
  313. strncpy(buf, ptr, max);
  314. buf[max] = '\0';
  315. }
  316. *baud = AVALON_IO_SPEED;
  317. *miner_count = AVALON_DEFAULT_MINER_NUM;
  318. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  319. *timeout = AVALON_DEFAULT_TIMEOUT;
  320. if (!(*buf))
  321. return;
  322. colon = strchr(buf, ':');
  323. if (colon)
  324. *(colon++) = '\0';
  325. tmp = atoi(buf);
  326. switch (tmp) {
  327. case 115200:
  328. *baud = 115200;
  329. break;
  330. case 57600:
  331. *baud = 57600;
  332. break;
  333. case 19200:
  334. *baud = 19200;
  335. break;
  336. default:
  337. sprintf(err_buf,
  338. "Invalid avalon-options for baud (%s) "
  339. "must be 115200, 57600 or 19200", buf);
  340. quit(1, err_buf);
  341. }
  342. if (colon && *colon) {
  343. colon2 = strchr(colon, ':');
  344. if (colon2)
  345. *(colon2++) = '\0';
  346. if (*colon) {
  347. tmp = atoi(colon);
  348. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  349. *miner_count = tmp;
  350. } else {
  351. sprintf(err_buf,
  352. "Invalid avalon-options for "
  353. "miner_count (%s) must be 1 ~ %d",
  354. colon, AVALON_DEFAULT_MINER_NUM);
  355. quit(1, err_buf);
  356. }
  357. }
  358. if (colon2 && *colon2) {
  359. colon3 = strchr(colon2, ':');
  360. if (colon3)
  361. *(colon3++) = '\0';
  362. tmp = atoi(colon2);
  363. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  364. *asic_count = tmp;
  365. else {
  366. sprintf(err_buf,
  367. "Invalid avalon-options for "
  368. "asic_count (%s) must be 1 ~ %d",
  369. colon2, AVALON_DEFAULT_ASIC_NUM);
  370. quit(1, err_buf);
  371. }
  372. if (colon3 && *colon3) {
  373. tmp = atoi(colon3);
  374. if (tmp > 0 && tmp <= 0xff)
  375. *timeout = tmp;
  376. else {
  377. sprintf(err_buf,
  378. "Invalid avalon-options for "
  379. "timeout (%s) must be 1 ~ %d",
  380. colon3, 0xff);
  381. quit(1, err_buf);
  382. }
  383. }
  384. }
  385. }
  386. }
  387. static bool avalon_detect_one(const char *devpath)
  388. {
  389. struct avalon_info *info;
  390. int fd, ret;
  391. int baud, miner_count, asic_count, timeout;
  392. int this_option_offset = ++option_offset;
  393. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  394. &timeout);
  395. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  396. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  397. devpath, baud, miner_count, asic_count, timeout);
  398. fd = avalon_open2(devpath, baud, true);
  399. if (unlikely(fd == -1)) {
  400. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  401. return false;
  402. }
  403. ret = avalon_reset(fd, timeout, asic_count, miner_count);
  404. avalon_close(fd);
  405. if (ret)
  406. return false;
  407. /* We have a real Avalon! */
  408. struct cgpu_info *avalon;
  409. avalon = calloc(1, sizeof(struct cgpu_info));
  410. avalon->api = &avalon_api;
  411. avalon->device_path = strdup(devpath);
  412. avalon->device_fd = -1;
  413. avalon->threads = AVALON_MINER_THREADS;
  414. add_cgpu(avalon);
  415. avalon_info = realloc(avalon_info,
  416. sizeof(struct avalon_info *) *
  417. (total_devices + 1));
  418. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  419. devpath, avalon->device_id);
  420. avalon_info[avalon->device_id] = (struct avalon_info *)
  421. malloc(sizeof(struct avalon_info));
  422. if (unlikely(!(avalon_info[avalon->device_id])))
  423. quit(1, "Failed to malloc avalon_info");
  424. info = avalon_info[avalon->device_id];
  425. memset(info, 0, sizeof(struct avalon_info));
  426. info->baud = baud;
  427. info->miner_count = miner_count;
  428. info->asic_count = asic_count;
  429. info->timeout = timeout;
  430. set_timing_mode(avalon);
  431. return true;
  432. }
  433. static inline void avalon_detect()
  434. {
  435. serial_detect(&avalon_api, avalon_detect_one);
  436. }
  437. static bool avalon_prepare(struct thr_info *thr)
  438. {
  439. struct cgpu_info *avalon = thr->cgpu;
  440. struct timeval now;
  441. int fd, ret;
  442. struct avalon_info *info = avalon_info[avalon->device_id];
  443. avalon->device_fd = -1;
  444. fd = avalon_open(avalon->device_path,
  445. avalon_info[avalon->device_id]->baud);
  446. if (unlikely(fd == -1)) {
  447. applog(LOG_ERR, "Avalon: Failed to open on %s",
  448. avalon->device_path);
  449. return false;
  450. }
  451. ret = avalon_reset(fd, info->timeout, info->asic_count,
  452. info->miner_count);
  453. if (ret)
  454. return false;
  455. avalon->device_fd = fd;
  456. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  457. gettimeofday(&now, NULL);
  458. get_datestamp(avalon->init, &now);
  459. return true;
  460. }
  461. static void avalon_free_work(struct thr_info *thr, struct work **work)
  462. {
  463. struct cgpu_info *avalon;
  464. struct avalon_info *info;
  465. int avalon_get_work_count, i;
  466. if (!work)
  467. return;
  468. avalon = thr->cgpu;
  469. info = avalon_info[avalon->device_id];
  470. avalon_get_work_count = info->miner_count;
  471. for (i = 0; i < avalon_get_work_count; i++)
  472. if (work[i]) {
  473. free_work(work[i]);
  474. work[i] = NULL;
  475. }
  476. }
  477. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  478. __maybe_unused int64_t max_nonce)
  479. {
  480. struct cgpu_info *avalon;
  481. int fd;
  482. int ret;
  483. int full;
  484. struct avalon_info *info;
  485. struct avalon_task at;
  486. struct avalon_result ar;
  487. static struct work *bulk0[AVALON_DEFAULT_MINER_NUM] = {
  488. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  489. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  490. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  491. static struct work *bulk1[AVALON_DEFAULT_MINER_NUM] = {
  492. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  493. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  494. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  495. static struct work *bulk2[AVALON_DEFAULT_MINER_NUM] = {
  496. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  497. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  498. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  499. struct work **work = NULL;
  500. int i, work_i0, work_i1, work_i2;
  501. int avalon_get_work_count;
  502. uint32_t nonce;
  503. int64_t hash_count;
  504. struct timeval tv_start, tv_finish, elapsed;
  505. int curr_hw_errors;
  506. bool was_hw_error;
  507. int64_t estimate_hashes;
  508. avalon = thr->cgpu;
  509. info = avalon_info[avalon->device_id];
  510. avalon_get_work_count = info->miner_count;
  511. if (avalon->device_fd == -1)
  512. if (!avalon_prepare(thr)) {
  513. applog(LOG_ERR, "AVA%i: Comms error",
  514. avalon->device_id);
  515. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  516. /* fail the device if the reopen attempt fails */
  517. return -1;
  518. }
  519. fd = avalon->device_fd;
  520. #ifndef WIN32
  521. tcflush(fd, TCOFLUSH);
  522. #endif
  523. work = bulk_work;
  524. for (i = 0; i < avalon_get_work_count; i++) {
  525. bulk0[i] = bulk1[i];
  526. bulk1[i] = bulk2[i];
  527. bulk2[i] = work[i];
  528. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  529. i, bulk0[i], bulk1[i], bulk2[i]);
  530. }
  531. i = 0;
  532. while (true) {
  533. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  534. avalon_create_task(&at, work[i]);
  535. ret = avalon_send_task(fd, &at, thr);
  536. if (ret == AVA_SEND_ERROR ||
  537. (ret == AVA_SEND_BUFFER_EMPTY &&
  538. (i + 1 == avalon_get_work_count))) {
  539. avalon_free_work(thr, bulk0);
  540. avalon_free_work(thr, bulk1);
  541. avalon_free_work(thr, bulk2);
  542. do_avalon_close(thr);
  543. applog(LOG_ERR, "AVA%i: Comms error",
  544. avalon->device_id);
  545. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  546. sleep(1);
  547. return 0; /* This should never happen */
  548. }
  549. work[i]->blk.nonce = 0xffffffff;
  550. if (ret == AVA_SEND_BUFFER_FULL)
  551. break;
  552. i++;
  553. }
  554. elapsed.tv_sec = elapsed.tv_usec = 0;
  555. gettimeofday(&tv_start, NULL);
  556. while(true) {
  557. full = avalon_buffer_full(fd);
  558. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  559. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  560. if (full == AVA_BUFFER_EMPTY)
  561. break;
  562. work_i0 = work_i1 = work_i2 = -1;
  563. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  564. if (ret == AVA_GETS_ERROR) {
  565. avalon_free_work(thr, bulk0);
  566. avalon_free_work(thr, bulk1);
  567. avalon_free_work(thr, bulk2);
  568. do_avalon_close(thr);
  569. applog(LOG_ERR,
  570. "AVA%i: Comms error", avalon->device_id);
  571. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  572. return 0;
  573. }
  574. /* aborted before becoming idle, get new work */
  575. if (ret == AVA_GETS_TIMEOUT) {
  576. timersub(&tv_finish, &tv_start, &elapsed);
  577. estimate_hashes = ((double)(elapsed.tv_sec) +
  578. ((double)(elapsed.tv_usec)) /
  579. ((double)1000000)) / info->Hs;
  580. /* If Serial-USB delay allowed the full nonce range to
  581. * complete it can't have done more than a full nonce
  582. */
  583. if (unlikely(estimate_hashes > 0xffffffff))
  584. estimate_hashes = 0xffffffff;
  585. applog(LOG_DEBUG,
  586. "Avalon: no nonce = 0x%08llx hashes "
  587. "(%ld.%06lds)",
  588. estimate_hashes, elapsed.tv_sec,
  589. elapsed.tv_usec);
  590. continue;
  591. }
  592. if (ret == AVA_GETS_RESTART) {
  593. avalon_free_work(thr, bulk0);
  594. avalon_free_work(thr, bulk1);
  595. avalon_free_work(thr, bulk2);
  596. continue;
  597. }
  598. avalon->temp = ar.temp0;
  599. work_i0 = avalon_decode_nonce(thr, bulk0, &ar, &nonce);
  600. work_i1 = avalon_decode_nonce(thr, bulk1, &ar, &nonce);
  601. work_i2 = avalon_decode_nonce(thr, bulk2, &ar, &nonce);
  602. curr_hw_errors = avalon->hw_errors;
  603. if (work_i0 >= 0)
  604. submit_nonce(thr, bulk0[work_i0], nonce);
  605. if (work_i1 >= 0)
  606. submit_nonce(thr, bulk1[work_i1], nonce);
  607. if (work_i2 >= 0)
  608. submit_nonce(thr, bulk2[work_i2], nonce);
  609. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  610. /* Force a USB close/reopen on any hw error */
  611. if (was_hw_error)
  612. do_avalon_close(thr);
  613. hash_count = nonce;
  614. hash_count++;
  615. hash_count *= info->asic_count;
  616. }
  617. avalon_free_work(thr, bulk0);
  618. if (opt_debug) {
  619. timersub(&tv_finish, &tv_start, &elapsed);
  620. applog(LOG_DEBUG,
  621. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  622. "(%ld.%06lds)",
  623. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  624. }
  625. applog(LOG_ERR,
  626. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  627. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  628. return hash_count;
  629. }
  630. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  631. {
  632. struct api_data *root = NULL;
  633. struct avalon_info *info = avalon_info[cgpu->device_id];
  634. root = api_add_int(root, "read_count", &(info->read_count), false);
  635. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  636. root = api_add_int(root, "baud", &(info->baud), false);
  637. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  638. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  639. return root;
  640. }
  641. static void avalon_shutdown(struct thr_info *thr)
  642. {
  643. do_avalon_close(thr);
  644. }
  645. struct device_api avalon_api = {
  646. .dname = "avalon",
  647. .name = "AVA",
  648. .api_detect = avalon_detect,
  649. .thread_prepare = avalon_prepare,
  650. .scanhash_queue = avalon_scanhash,
  651. .get_api_stats = avalon_api_stats,
  652. .thread_shutdown = avalon_shutdown,
  653. };