driver-avalon.c 20 KB

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  1. /*
  2. * Copyright 2013 Xiangfu
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int no_matching_work = 0;
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p,
  40. uint8_t miner_num_p)
  41. {
  42. static bool first = true;
  43. uint8_t timeout;
  44. uint8_t asic_num;
  45. uint8_t miner_num;
  46. struct cgpu_info *avalon;
  47. struct avalon_info *info;
  48. if (!at)
  49. return -1;
  50. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  51. return -1;
  52. timeout = timeout_p;
  53. miner_num = miner_num_p;
  54. asic_num = asic_num_p;
  55. if (thr) {
  56. avalon = thr->cgpu;
  57. info = avalon_info[avalon->device_id];
  58. timeout = info->timeout;
  59. miner_num = info->miner_count;
  60. asic_num = info->asic_count;
  61. }
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (reset) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (first && !at->reset) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = 1;
  81. return 0;
  82. }
  83. static inline void avalon_create_task(struct avalon_task *at,
  84. struct work *work)
  85. {
  86. memcpy(at->midstate, work->midstate, 32);
  87. memcpy(at->data, work->data + 64, 12);
  88. }
  89. static int avalon_send_task(int fd, const struct avalon_task *at,
  90. struct thr_info *thr)
  91. {
  92. size_t ret;
  93. int full;
  94. struct timespec p;
  95. uint8_t *buf;
  96. size_t nr_len;
  97. struct cgpu_info *avalon;
  98. struct avalon_info *info;
  99. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  100. uint32_t nonce_range;
  101. int i;
  102. if (at->nonce_elf)
  103. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  104. else
  105. nr_len = AVALON_WRITE_SIZE;
  106. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  107. if (!buf)
  108. return AVA_SEND_ERROR;
  109. memcpy(buf, at, AVALON_WRITE_SIZE);
  110. if (at->nonce_elf) {
  111. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  112. for (i = 0; i < at->asic_num; i++) {
  113. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  114. (i * nonce_range & 0xff000000) >> 24;
  115. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  116. (i * nonce_range & 0x00ff0000) >> 16;
  117. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  118. (i * nonce_range & 0x0000ff00) >> 8;
  119. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  120. (i * nonce_range & 0x000000ff) >> 0;
  121. }
  122. }
  123. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  124. uint8_t tt = 0;
  125. tt = (buf[0] & 0x0f) << 4;
  126. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  127. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  128. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  129. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  130. buf[0] = tt;
  131. buf[4] = rev8(buf[4]);
  132. #endif
  133. if (opt_debug) {
  134. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  135. hexdump((uint8_t *)buf, nr_len);
  136. }
  137. ret = write(fd, buf, nr_len);
  138. free(buf);
  139. if (unlikely(ret != nr_len))
  140. return AVA_SEND_ERROR;
  141. if (thr) {
  142. avalon = thr->cgpu;
  143. info = avalon_info[avalon->device_id];
  144. delay = nr_len * 10 * 1000000000ULL;
  145. delay = delay / info->baud;
  146. }
  147. p.tv_sec = 0;
  148. p.tv_nsec = (long)delay + 4000000;
  149. nanosleep(&p, NULL);
  150. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  151. full = avalon_buffer_full(fd);
  152. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  153. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  154. if (full == AVA_BUFFER_EMPTY)
  155. return AVA_SEND_BUFFER_EMPTY;
  156. return AVA_SEND_BUFFER_FULL;
  157. }
  158. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  159. struct thr_info *thr, struct timeval *tv_finish)
  160. {
  161. ssize_t ret = 0;
  162. int rc = 0;
  163. int read_amount = AVALON_READ_SIZE;
  164. bool first = true;
  165. /* Read reply 1 byte at a time to get earliest tv_finish */
  166. while (true) {
  167. ret = read(fd, buf, 1);
  168. if (ret < 0)
  169. return AVA_GETS_ERROR;
  170. if (first && tv_finish != NULL)
  171. gettimeofday(tv_finish, NULL);
  172. if (ret >= read_amount)
  173. return AVA_GETS_OK;
  174. if (ret > 0) {
  175. buf += ret;
  176. read_amount -= ret;
  177. first = false;
  178. continue;
  179. }
  180. rc++;
  181. if (rc >= read_count) {
  182. if (opt_debug) {
  183. applog(LOG_ERR,
  184. "Avalon: No data in %.2f seconds",
  185. (float)rc/(float)TIME_FACTOR);
  186. }
  187. return AVA_GETS_TIMEOUT;
  188. }
  189. if (thr && thr->work_restart) {
  190. if (opt_debug) {
  191. applog(LOG_ERR,
  192. "Avalon: Work restart at %.2f seconds",
  193. (float)(rc)/(float)TIME_FACTOR);
  194. }
  195. return AVA_GETS_RESTART;
  196. }
  197. }
  198. }
  199. static int avalon_get_result(int fd, struct avalon_result *ar,
  200. struct thr_info *thr, struct timeval *tv_finish)
  201. {
  202. struct cgpu_info *avalon;
  203. struct avalon_info *info;
  204. uint8_t result[AVALON_READ_SIZE];
  205. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  206. if (thr) {
  207. avalon = thr->cgpu;
  208. info = avalon_info[avalon->device_id];
  209. read_count = info->read_count;
  210. }
  211. memset(result, 0, AVALON_READ_SIZE);
  212. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  213. if (ret == AVA_GETS_OK) {
  214. if (opt_debug) {
  215. applog(LOG_DEBUG, "Avalon: get:");
  216. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  217. }
  218. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  219. }
  220. return ret;
  221. }
  222. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  223. struct avalon_result *ar, uint32_t *nonce)
  224. {
  225. struct cgpu_info *avalon;
  226. struct avalon_info *info;
  227. int avalon_get_work_count, i;
  228. if (!work)
  229. return -1;
  230. avalon = thr->cgpu;
  231. info = avalon_info[avalon->device_id];
  232. avalon_get_work_count = info->miner_count;
  233. for (i = 0; i < avalon_get_work_count; i++) {
  234. if (work[i] &&
  235. !memcmp(ar->data, work[i]->data + 64, 12) &&
  236. !memcmp(ar->midstate, work[i]->midstate, 32))
  237. break;
  238. }
  239. if (i == avalon_get_work_count)
  240. return -1;
  241. *nonce = ar->nonce;
  242. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  243. *nonce = swab32(*nonce);
  244. #endif
  245. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  246. return i;
  247. }
  248. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  249. uint8_t miner_num_p, struct avalon_result *ar)
  250. {
  251. struct avalon_task at;
  252. uint8_t *buf;
  253. int ret, i = 0;
  254. struct timespec p;
  255. avalon_init_task(NULL,
  256. &at, 1, 0,
  257. AVALON_DEFAULT_FAN_PWM,
  258. timeout_p, asic_num_p, miner_num_p);
  259. ret = avalon_send_task(fd, &at, NULL);
  260. if (ret == AVA_SEND_ERROR)
  261. return 1;
  262. avalon_get_result(fd, ar, NULL, NULL);
  263. buf = (uint8_t *)ar;
  264. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  265. buf[2] == 0xAA && buf[3] == 0x55) {
  266. for (i = 4; i < 11; i++)
  267. if (buf[i] != 0)
  268. break;
  269. }
  270. if (i != 11) {
  271. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  272. " (%d: %02x %02x %02x %02x)",
  273. i, buf[0], buf[1], buf[2], buf[3]);
  274. return 1;
  275. }
  276. p.tv_sec = 1;
  277. p.tv_nsec = AVALON_RESET_PITCH;
  278. nanosleep(&p, NULL);
  279. applog(LOG_ERR,
  280. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  281. "Temp1: %d, Temp2: %d, Temp3: %d",
  282. ar->fan0, ar->fan1, ar->fan2, ar->temp0, ar->temp1, ar->temp2);
  283. applog(LOG_ERR, "Avalon: Reset succeeded");
  284. return 0;
  285. }
  286. static void do_avalon_close(struct thr_info *thr)
  287. {
  288. struct cgpu_info *avalon = thr->cgpu;
  289. avalon_close(avalon->device_fd);
  290. avalon->device_fd = -1;
  291. no_matching_work = 0;
  292. /* FIXME: should I free the bulk1 and bulk2? */
  293. }
  294. static void set_timing_mode(struct cgpu_info *avalon, struct avalon_result *ar)
  295. {
  296. struct avalon_info *info = avalon_info[avalon->device_id];
  297. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  298. TIME_FACTOR) / (float)info->miner_count;
  299. info->fan0 = ar->fan0;
  300. info->fan1 = ar->fan1;
  301. info->fan2 = ar->fan2;
  302. info->temp0 = ar->temp0;
  303. info->temp1 = ar->temp1;
  304. info->temp2 = ar->temp2;
  305. if (info->temp0 > info->temp_max)
  306. info->temp_max = info->temp0;
  307. if (info->temp1 > info->temp_max)
  308. info->temp_max = info->temp1;
  309. if (info->temp2 > info->temp_max)
  310. info->temp_max = info->temp2;
  311. }
  312. static void get_options(int this_option_offset, int *baud, int *miner_count,
  313. int *asic_count, int *timeout)
  314. {
  315. char err_buf[BUFSIZ+1];
  316. char buf[BUFSIZ+1];
  317. char *ptr, *comma, *colon, *colon2, *colon3;
  318. size_t max;
  319. int i, tmp;
  320. if (opt_avalon_options == NULL)
  321. buf[0] = '\0';
  322. else {
  323. ptr = opt_avalon_options;
  324. for (i = 0; i < this_option_offset; i++) {
  325. comma = strchr(ptr, ',');
  326. if (comma == NULL)
  327. break;
  328. ptr = comma + 1;
  329. }
  330. comma = strchr(ptr, ',');
  331. if (comma == NULL)
  332. max = strlen(ptr);
  333. else
  334. max = comma - ptr;
  335. if (max > BUFSIZ)
  336. max = BUFSIZ;
  337. strncpy(buf, ptr, max);
  338. buf[max] = '\0';
  339. }
  340. *baud = AVALON_IO_SPEED;
  341. *miner_count = AVALON_DEFAULT_MINER_NUM;
  342. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  343. *timeout = AVALON_DEFAULT_TIMEOUT;
  344. if (!(*buf))
  345. return;
  346. colon = strchr(buf, ':');
  347. if (colon)
  348. *(colon++) = '\0';
  349. tmp = atoi(buf);
  350. switch (tmp) {
  351. case 115200:
  352. *baud = 115200;
  353. break;
  354. case 57600:
  355. *baud = 57600;
  356. break;
  357. case 38400:
  358. *baud = 38400;
  359. break;
  360. case 19200:
  361. *baud = 19200;
  362. break;
  363. default:
  364. sprintf(err_buf,
  365. "Invalid avalon-options for baud (%s) "
  366. "must be 115200, 57600, 38400 or 19200", buf);
  367. quit(1, err_buf);
  368. }
  369. if (colon && *colon) {
  370. colon2 = strchr(colon, ':');
  371. if (colon2)
  372. *(colon2++) = '\0';
  373. if (*colon) {
  374. tmp = atoi(colon);
  375. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  376. *miner_count = tmp;
  377. } else {
  378. sprintf(err_buf,
  379. "Invalid avalon-options for "
  380. "miner_count (%s) must be 1 ~ %d",
  381. colon, AVALON_DEFAULT_MINER_NUM);
  382. quit(1, err_buf);
  383. }
  384. }
  385. if (colon2 && *colon2) {
  386. colon3 = strchr(colon2, ':');
  387. if (colon3)
  388. *(colon3++) = '\0';
  389. tmp = atoi(colon2);
  390. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  391. *asic_count = tmp;
  392. else {
  393. sprintf(err_buf,
  394. "Invalid avalon-options for "
  395. "asic_count (%s) must be 1 ~ %d",
  396. colon2, AVALON_DEFAULT_ASIC_NUM);
  397. quit(1, err_buf);
  398. }
  399. if (colon3 && *colon3) {
  400. tmp = atoi(colon3);
  401. if (tmp > 0 && tmp <= 0xff)
  402. *timeout = tmp;
  403. else {
  404. sprintf(err_buf,
  405. "Invalid avalon-options for "
  406. "timeout (%s) must be 1 ~ %d",
  407. colon3, 0xff);
  408. quit(1, err_buf);
  409. }
  410. }
  411. }
  412. }
  413. }
  414. static bool avalon_detect_one(const char *devpath)
  415. {
  416. struct avalon_info *info;
  417. struct avalon_result ar;
  418. int fd, ret;
  419. int baud, miner_count, asic_count, timeout;
  420. int this_option_offset = ++option_offset;
  421. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  422. &timeout);
  423. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  424. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  425. devpath, baud, miner_count, asic_count, timeout);
  426. fd = avalon_open2(devpath, baud, true);
  427. if (unlikely(fd == -1)) {
  428. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  429. return false;
  430. }
  431. ret = avalon_reset(fd, timeout, asic_count, miner_count, &ar);
  432. avalon_close(fd);
  433. if (ret)
  434. return false;
  435. /* We have a real Avalon! */
  436. struct cgpu_info *avalon;
  437. avalon = calloc(1, sizeof(struct cgpu_info));
  438. avalon->api = &avalon_api;
  439. avalon->device_path = strdup(devpath);
  440. avalon->device_fd = -1;
  441. avalon->threads = AVALON_MINER_THREADS;
  442. add_cgpu(avalon);
  443. avalon_info = realloc(avalon_info,
  444. sizeof(struct avalon_info *) *
  445. (total_devices + 1));
  446. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  447. devpath, avalon->device_id);
  448. avalon_info[avalon->device_id] = (struct avalon_info *)
  449. malloc(sizeof(struct avalon_info));
  450. if (unlikely(!(avalon_info[avalon->device_id])))
  451. quit(1, "Failed to malloc avalon_info");
  452. info = avalon_info[avalon->device_id];
  453. memset(info, 0, sizeof(struct avalon_info));
  454. info->baud = baud;
  455. info->miner_count = miner_count;
  456. info->asic_count = asic_count;
  457. info->timeout = timeout;
  458. set_timing_mode(avalon, &ar);
  459. return true;
  460. }
  461. static inline void avalon_detect()
  462. {
  463. serial_detect(&avalon_api, avalon_detect_one);
  464. }
  465. static bool avalon_prepare(struct thr_info *thr)
  466. {
  467. struct avalon_result ar;
  468. struct cgpu_info *avalon = thr->cgpu;
  469. struct timeval now;
  470. int fd, ret;
  471. struct avalon_info *info = avalon_info[avalon->device_id];
  472. avalon->device_fd = -1;
  473. fd = avalon_open(avalon->device_path,
  474. avalon_info[avalon->device_id]->baud);
  475. if (unlikely(fd == -1)) {
  476. applog(LOG_ERR, "Avalon: Failed to open on %s",
  477. avalon->device_path);
  478. return false;
  479. }
  480. ret = avalon_reset(fd, info->timeout, info->asic_count,
  481. info->miner_count, &ar);
  482. if (ret)
  483. return false;
  484. avalon->device_fd = fd;
  485. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  486. gettimeofday(&now, NULL);
  487. get_datestamp(avalon->init, &now);
  488. return true;
  489. }
  490. static void avalon_free_work(struct thr_info *thr, struct work **work)
  491. {
  492. struct cgpu_info *avalon;
  493. struct avalon_info *info;
  494. int avalon_get_work_count, i;
  495. if (!work)
  496. return;
  497. avalon = thr->cgpu;
  498. info = avalon_info[avalon->device_id];
  499. avalon_get_work_count = info->miner_count;
  500. for (i = 0; i < avalon_get_work_count; i++)
  501. if (work[i]) {
  502. free_work(work[i]);
  503. work[i] = NULL;
  504. }
  505. }
  506. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  507. __maybe_unused int64_t max_nonce)
  508. {
  509. struct cgpu_info *avalon;
  510. int fd, ret, full;
  511. struct avalon_info *info;
  512. struct avalon_task at;
  513. struct avalon_result ar;
  514. static struct work *bulk0[AVALON_DEFAULT_MINER_NUM] = {
  515. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  516. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  517. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  518. static struct work *bulk1[AVALON_DEFAULT_MINER_NUM] = {
  519. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  520. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  521. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  522. static struct work *bulk2[AVALON_DEFAULT_MINER_NUM] = {
  523. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  524. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  525. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  526. struct work **work = NULL;
  527. int i, work_i0, work_i1, work_i2;
  528. int avalon_get_work_count;
  529. struct timeval tv_start, tv_finish, elapsed;
  530. uint32_t nonce;
  531. int64_t hash_count;
  532. avalon = thr->cgpu;
  533. info = avalon_info[avalon->device_id];
  534. avalon_get_work_count = info->miner_count;
  535. if (avalon->device_fd == -1)
  536. if (!avalon_prepare(thr)) {
  537. applog(LOG_ERR, "AVA%i: Comms error",
  538. avalon->device_id);
  539. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  540. /* fail the device if the reopen attempt fails */
  541. return -1;
  542. }
  543. fd = avalon->device_fd;
  544. #ifndef WIN32
  545. tcflush(fd, TCOFLUSH);
  546. #endif
  547. work = bulk_work;
  548. for (i = 0; i < avalon_get_work_count; i++) {
  549. bulk0[i] = bulk1[i];
  550. bulk1[i] = bulk2[i];
  551. bulk2[i] = work[i];
  552. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  553. i, bulk0[i], bulk1[i], bulk2[i]);
  554. }
  555. i = 0;
  556. while (true) {
  557. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  558. avalon_create_task(&at, work[i]);
  559. ret = avalon_send_task(fd, &at, thr);
  560. if (ret == AVA_SEND_ERROR ||
  561. (ret == AVA_SEND_BUFFER_EMPTY &&
  562. (i + 1 == avalon_get_work_count))) {
  563. avalon_free_work(thr, bulk0);
  564. avalon_free_work(thr, bulk1);
  565. avalon_free_work(thr, bulk2);
  566. do_avalon_close(thr);
  567. applog(LOG_ERR, "AVA%i: Comms error",
  568. avalon->device_id);
  569. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  570. sleep(1);
  571. return 0; /* This should never happen */
  572. }
  573. work[i]->blk.nonce = 0xffffffff;
  574. if (ret == AVA_SEND_BUFFER_FULL)
  575. break;
  576. i++;
  577. }
  578. elapsed.tv_sec = elapsed.tv_usec = 0;
  579. gettimeofday(&tv_start, NULL);
  580. hash_count = 0;
  581. while(true) {
  582. work_i0 = work_i1 = work_i2 = -1;
  583. full = avalon_buffer_full(fd);
  584. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  585. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  586. if (full == AVA_BUFFER_EMPTY)
  587. break;
  588. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  589. if (ret == AVA_GETS_ERROR) {
  590. avalon_free_work(thr, bulk0);
  591. avalon_free_work(thr, bulk1);
  592. avalon_free_work(thr, bulk2);
  593. do_avalon_close(thr);
  594. applog(LOG_ERR,
  595. "AVA%i: Comms error", avalon->device_id);
  596. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  597. return 0;
  598. }
  599. if (ret == AVA_GETS_TIMEOUT) {
  600. timersub(&tv_finish, &tv_start, &elapsed);
  601. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  602. elapsed.tv_sec, elapsed.tv_usec);
  603. continue;
  604. }
  605. if (ret == AVA_GETS_RESTART) {
  606. avalon_free_work(thr, bulk0);
  607. avalon_free_work(thr, bulk1);
  608. avalon_free_work(thr, bulk2);
  609. continue;
  610. }
  611. avalon->temp = (ar.temp0 + ar.temp1 + ar.temp2) / 3;
  612. info->fan0 = ar.fan0;
  613. info->fan1 = ar.fan1;
  614. info->fan2 = ar.fan2;
  615. info->temp0 = ar.temp0;
  616. info->temp1 = ar.temp1;
  617. info->temp2 = ar.temp2;
  618. if (info->temp0 > info->temp_max)
  619. info->temp_max = info->temp0;
  620. if (info->temp1 > info->temp_max)
  621. info->temp_max = info->temp1;
  622. if (info->temp2 > info->temp_max)
  623. info->temp_max = info->temp2;
  624. work_i0 = avalon_decode_nonce(thr, bulk0, &ar, &nonce);
  625. work_i1 = avalon_decode_nonce(thr, bulk1, &ar, &nonce);
  626. work_i2 = avalon_decode_nonce(thr, bulk2, &ar, &nonce);
  627. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0)) {
  628. if (opt_debug) {
  629. timersub(&tv_finish, &tv_start, &elapsed);
  630. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  631. " (%ld.%06lds)", ++no_matching_work,
  632. elapsed.tv_sec, elapsed.tv_usec);
  633. }
  634. continue;
  635. }
  636. if (work_i0 >= 0)
  637. submit_nonce(thr, bulk0[work_i0], nonce);
  638. if (work_i1 >= 0)
  639. submit_nonce(thr, bulk1[work_i1], nonce);
  640. if (work_i2 >= 0)
  641. submit_nonce(thr, bulk2[work_i2], nonce);
  642. /* TODO: should I take care about HW, no_matching_work? */
  643. hash_count += nonce;
  644. if (opt_debug) {
  645. timersub(&tv_finish, &tv_start, &elapsed);
  646. applog(LOG_DEBUG,
  647. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  648. "(%ld.%06lds)", nonce, hash_count,
  649. elapsed.tv_sec, elapsed.tv_usec);
  650. }
  651. }
  652. avalon_free_work(thr, bulk0);
  653. applog(LOG_ERR,
  654. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  655. "Temp1: %d, Temp2: %d, Temp3: %d, TempMAX: %d",
  656. info->fan0, info->fan1, info->fan2,
  657. info->temp0, info->temp1, info->temp2, info->temp_max);
  658. return (hash_count ? hash_count :
  659. ((int64_t)256*1024*1024)*info->miner_count*info->asic_count);
  660. }
  661. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  662. {
  663. struct api_data *root = NULL;
  664. struct avalon_info *info = avalon_info[cgpu->device_id];
  665. root = api_add_int(root, "read_count", &(info->read_count), false);
  666. root = api_add_int(root, "baud", &(info->baud), false);
  667. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  668. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  669. root = api_add_int(root, "fan1", &(info->fan0), false);
  670. root = api_add_int(root, "fan2", &(info->fan1), false);
  671. root = api_add_int(root, "fan3", &(info->fan2), false);
  672. root = api_add_int(root, "temp1", &(info->temp0), false);
  673. root = api_add_int(root, "temp2", &(info->temp1), false);
  674. root = api_add_int(root, "temp3", &(info->temp2), false);
  675. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  676. return root;
  677. }
  678. static void avalon_shutdown(struct thr_info *thr)
  679. {
  680. do_avalon_close(thr);
  681. }
  682. struct device_api avalon_api = {
  683. .dname = "avalon",
  684. .name = "AVA",
  685. .api_detect = avalon_detect,
  686. .thread_prepare = avalon_prepare,
  687. .scanhash_queue = avalon_scanhash,
  688. .get_api_stats = avalon_api_stats,
  689. .thread_shutdown = avalon_shutdown,
  690. };