driver-avalon.c 23 KB

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  1. /*
  2. * Copyright 2013 Avalon project
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int option_offset = -1;
  34. struct avalon_info **avalon_info;
  35. struct device_api avalon_api;
  36. static int avalon_init_task(struct avalon_task *at,
  37. uint8_t reset, uint8_t ff, uint8_t fan,
  38. uint8_t timeout, uint8_t asic_num,
  39. uint8_t miner_num, uint8_t nonce_elf)
  40. {
  41. static bool first = true;
  42. if (unlikely(!at))
  43. return -1;
  44. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  45. return -1;
  46. memset(at, 0, sizeof(struct avalon_task));
  47. if (unlikely(reset)) {
  48. at->reset = 1;
  49. at->fan_eft = 1;
  50. at->timer_eft = 1;
  51. first = true;
  52. }
  53. at->flush_fifo = (ff ? 1 : 0);
  54. at->fan_eft = (fan ? 1 : 0);
  55. if (unlikely(first && !at->reset)) {
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = false;
  59. }
  60. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  61. at->timeout_data = timeout;
  62. at->asic_num = asic_num;
  63. at->miner_num = miner_num;
  64. at->nonce_elf = nonce_elf;
  65. return 0;
  66. }
  67. static inline void avalon_create_task(struct avalon_task *at,
  68. struct work *work)
  69. {
  70. memcpy(at->midstate, work->midstate, 32);
  71. memcpy(at->data, work->data + 64, 12);
  72. }
  73. static int avalon_send_task(int fd, const struct avalon_task *at,
  74. struct thr_info *thr)
  75. {
  76. size_t ret;
  77. int full;
  78. struct timespec p;
  79. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  80. size_t nr_len;
  81. struct cgpu_info *avalon;
  82. struct avalon_info *info;
  83. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  84. uint32_t nonce_range;
  85. int i;
  86. if (at->nonce_elf)
  87. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  88. else
  89. nr_len = AVALON_WRITE_SIZE;
  90. memcpy(buf, at, AVALON_WRITE_SIZE);
  91. if (at->nonce_elf) {
  92. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  93. for (i = 0; i < at->asic_num; i++) {
  94. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  95. (i * nonce_range & 0xff000000) >> 24;
  96. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  97. (i * nonce_range & 0x00ff0000) >> 16;
  98. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  99. (i * nonce_range & 0x0000ff00) >> 8;
  100. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  101. (i * nonce_range & 0x000000ff) >> 0;
  102. }
  103. }
  104. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  105. uint8_t tt = 0;
  106. tt = (buf[0] & 0x0f) << 4;
  107. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  108. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  109. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  110. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  111. buf[0] = tt;
  112. buf[4] = rev8(buf[4]);
  113. #endif
  114. if (at->reset)
  115. nr_len = 1;
  116. if (opt_debug) {
  117. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  118. hexdump((uint8_t *)buf, nr_len);
  119. }
  120. ret = write(fd, buf, nr_len);
  121. if (unlikely(ret != nr_len))
  122. return AVA_SEND_ERROR;
  123. if (likely(thr)) {
  124. avalon = thr->cgpu;
  125. info = avalon_info[avalon->device_id];
  126. delay = nr_len * 10 * 1000000000ULL;
  127. delay = delay / info->baud;
  128. }
  129. p.tv_sec = 0;
  130. p.tv_nsec = (long)delay + 4000000;
  131. nanosleep(&p, NULL);
  132. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  133. full = avalon_buffer_full(fd);
  134. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  135. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  136. if (unlikely(full == AVA_BUFFER_FULL))
  137. return AVA_SEND_BUFFER_FULL;
  138. return AVA_SEND_BUFFER_EMPTY;
  139. }
  140. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  141. struct thr_info *thr, struct timeval *tv_finish)
  142. {
  143. ssize_t ret = 0;
  144. int rc = 0;
  145. int read_amount = AVALON_READ_SIZE;
  146. bool first = true;
  147. /* Read reply 1 byte at a time to get earliest tv_finish */
  148. while (true) {
  149. ret = read(fd, buf, 1);
  150. if (ret < 0)
  151. return AVA_GETS_ERROR;
  152. if (first && tv_finish != NULL)
  153. gettimeofday(tv_finish, NULL);
  154. if (ret >= read_amount)
  155. return AVA_GETS_OK;
  156. if (ret > 0) {
  157. buf += ret;
  158. read_amount -= ret;
  159. first = false;
  160. continue;
  161. }
  162. rc++;
  163. if (rc >= read_count) {
  164. if (opt_debug) {
  165. applog(LOG_WARNING,
  166. "Avalon: No data in %.2f seconds",
  167. (float)rc/(float)AVALON_TIME_FACTOR);
  168. }
  169. return AVA_GETS_TIMEOUT;
  170. }
  171. if (thr && thr->work_restart) {
  172. if (opt_debug) {
  173. applog(LOG_WARNING,
  174. "Avalon: Work restart at %.2f seconds",
  175. (float)(rc)/(float)AVALON_TIME_FACTOR);
  176. }
  177. return AVA_GETS_RESTART;
  178. }
  179. }
  180. }
  181. static int avalon_get_result(int fd, struct avalon_result *ar,
  182. struct thr_info *thr, struct timeval *tv_finish)
  183. {
  184. struct cgpu_info *avalon;
  185. struct avalon_info *info;
  186. uint8_t result[AVALON_READ_SIZE];
  187. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  188. if (likely(thr)) {
  189. avalon = thr->cgpu;
  190. info = avalon_info[avalon->device_id];
  191. read_count = info->read_count;
  192. }
  193. memset(result, 0, AVALON_READ_SIZE);
  194. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  195. if (ret == AVA_GETS_OK) {
  196. if (opt_debug) {
  197. applog(LOG_DEBUG, "Avalon: get:");
  198. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  199. }
  200. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  201. }
  202. return ret;
  203. }
  204. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  205. struct avalon_result *ar, uint32_t *nonce)
  206. {
  207. struct cgpu_info *avalon;
  208. struct avalon_info *info;
  209. int avalon_get_work_count, i;
  210. if (unlikely(!work))
  211. return -1;
  212. avalon = thr->cgpu;
  213. info = avalon_info[avalon->device_id];
  214. avalon_get_work_count = info->miner_count;
  215. for (i = 0; i < avalon_get_work_count; i++) {
  216. if (work[i] &&
  217. !memcmp(ar->data, work[i]->data + 64, 12) &&
  218. !memcmp(ar->midstate, work[i]->midstate, 32))
  219. break;
  220. }
  221. if (i == avalon_get_work_count)
  222. return -1;
  223. ++info->matching_work[i];
  224. *nonce = ar->nonce;
  225. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  226. *nonce = swab32(*nonce);
  227. #endif
  228. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  229. info->matching_work[i]);
  230. return i;
  231. }
  232. static int avalon_reset(int fd, struct avalon_result *ar)
  233. {
  234. struct avalon_task at;
  235. uint8_t *buf;
  236. int ret, i = 0;
  237. struct timespec p;
  238. avalon_init_task(&at, 1, 0,
  239. AVALON_DEFAULT_FAN_PWM,
  240. AVALON_DEFAULT_TIMEOUT,
  241. AVALON_DEFAULT_ASIC_NUM,
  242. AVALON_DEFAULT_MINER_NUM,
  243. 0);
  244. ret = avalon_send_task(fd, &at, NULL);
  245. if (ret == AVA_SEND_ERROR)
  246. return 1;
  247. avalon_get_result(fd, ar, NULL, NULL);
  248. buf = (uint8_t *)ar;
  249. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  250. buf[2] == 0xAA && buf[3] == 0x55) {
  251. for (i = 4; i < 11; i++)
  252. if (buf[i] != 0)
  253. break;
  254. }
  255. if (i != 11) {
  256. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  257. " (%d: %02x %02x %02x %02x)",
  258. i, buf[0], buf[1], buf[2], buf[3]);
  259. /* FIXME: return 1; */
  260. }
  261. p.tv_sec = 1;
  262. p.tv_nsec = AVALON_RESET_PITCH;
  263. nanosleep(&p, NULL);
  264. applog(LOG_WARNING, "Avalon: Reset succeeded");
  265. return 0;
  266. }
  267. static void get_options(int this_option_offset, int *baud, int *miner_count,
  268. int *asic_count, int *timeout)
  269. {
  270. char err_buf[BUFSIZ+1];
  271. char buf[BUFSIZ+1];
  272. char *ptr, *comma, *colon, *colon2, *colon3;
  273. size_t max;
  274. int i, tmp;
  275. if (opt_avalon_options == NULL)
  276. buf[0] = '\0';
  277. else {
  278. ptr = opt_avalon_options;
  279. for (i = 0; i < this_option_offset; i++) {
  280. comma = strchr(ptr, ',');
  281. if (comma == NULL)
  282. break;
  283. ptr = comma + 1;
  284. }
  285. comma = strchr(ptr, ',');
  286. if (comma == NULL)
  287. max = strlen(ptr);
  288. else
  289. max = comma - ptr;
  290. if (max > BUFSIZ)
  291. max = BUFSIZ;
  292. strncpy(buf, ptr, max);
  293. buf[max] = '\0';
  294. }
  295. *baud = AVALON_IO_SPEED;
  296. *miner_count = AVALON_DEFAULT_MINER_NUM;
  297. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  298. *timeout = AVALON_DEFAULT_TIMEOUT;
  299. if (!(*buf))
  300. return;
  301. colon = strchr(buf, ':');
  302. if (colon)
  303. *(colon++) = '\0';
  304. tmp = atoi(buf);
  305. switch (tmp) {
  306. case 115200:
  307. *baud = 115200;
  308. break;
  309. case 57600:
  310. *baud = 57600;
  311. break;
  312. case 38400:
  313. *baud = 38400;
  314. break;
  315. case 19200:
  316. *baud = 19200;
  317. break;
  318. default:
  319. sprintf(err_buf,
  320. "Invalid avalon-options for baud (%s) "
  321. "must be 115200, 57600, 38400 or 19200", buf);
  322. quit(1, err_buf);
  323. }
  324. if (colon && *colon) {
  325. colon2 = strchr(colon, ':');
  326. if (colon2)
  327. *(colon2++) = '\0';
  328. if (*colon) {
  329. tmp = atoi(colon);
  330. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  331. *miner_count = tmp;
  332. } else {
  333. sprintf(err_buf,
  334. "Invalid avalon-options for "
  335. "miner_count (%s) must be 1 ~ %d",
  336. colon, AVALON_DEFAULT_MINER_NUM);
  337. quit(1, err_buf);
  338. }
  339. }
  340. if (colon2 && *colon2) {
  341. colon3 = strchr(colon2, ':');
  342. if (colon3)
  343. *(colon3++) = '\0';
  344. tmp = atoi(colon2);
  345. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  346. *asic_count = tmp;
  347. else {
  348. sprintf(err_buf,
  349. "Invalid avalon-options for "
  350. "asic_count (%s) must be 1 ~ %d",
  351. colon2, AVALON_DEFAULT_ASIC_NUM);
  352. quit(1, err_buf);
  353. }
  354. if (colon3 && *colon3) {
  355. tmp = atoi(colon3);
  356. if (tmp > 0 && tmp <= 0xff)
  357. *timeout = tmp;
  358. else {
  359. sprintf(err_buf,
  360. "Invalid avalon-options for "
  361. "timeout (%s) must be 1 ~ %d",
  362. colon3, 0xff);
  363. quit(1, err_buf);
  364. }
  365. }
  366. }
  367. }
  368. }
  369. static bool avalon_detect_one(const char *devpath)
  370. {
  371. struct avalon_info *info;
  372. struct avalon_result ar;
  373. int fd, ret;
  374. int baud, miner_count, asic_count, timeout;
  375. int this_option_offset = ++option_offset;
  376. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  377. &timeout);
  378. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  379. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  380. devpath, baud, miner_count, asic_count, timeout);
  381. fd = avalon_open2(devpath, baud, true);
  382. if (unlikely(fd == -1)) {
  383. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  384. return false;
  385. }
  386. ret = avalon_reset(fd, &ar);
  387. avalon_close(fd);
  388. if (ret) {
  389. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  390. }
  391. /* We have a real Avalon! */
  392. struct cgpu_info *avalon;
  393. avalon = calloc(1, sizeof(struct cgpu_info));
  394. avalon->api = &avalon_api;
  395. avalon->device_path = strdup(devpath);
  396. avalon->device_fd = -1;
  397. avalon->threads = AVALON_MINER_THREADS;
  398. add_cgpu(avalon);
  399. avalon_info = realloc(avalon_info,
  400. sizeof(struct avalon_info *) *
  401. (total_devices + 1));
  402. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  403. devpath, avalon->device_id);
  404. avalon_info[avalon->device_id] = (struct avalon_info *)
  405. malloc(sizeof(struct avalon_info));
  406. if (unlikely(!(avalon_info[avalon->device_id])))
  407. quit(1, "Failed to malloc avalon_info");
  408. info = avalon_info[avalon->device_id];
  409. memset(info, 0, sizeof(struct avalon_info));
  410. info->baud = baud;
  411. info->miner_count = miner_count;
  412. info->asic_count = asic_count;
  413. info->timeout = timeout;
  414. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  415. AVALON_TIME_FACTOR) / (float)info->miner_count;
  416. info->fan_pwm = AVALON_DEFAULT_FAN_PWM;
  417. info->temp_max = 0;
  418. info->temp_history_count = (4 / (float)(0x3c * ((float)1.67/0x32))) + 1;
  419. if (info->temp_history_count <= 0)
  420. info->temp_history_count = 1;
  421. info->temp_history_index = 0;
  422. info->temp_sum = 0;
  423. info->temp_old = 0;
  424. return true;
  425. }
  426. static inline void avalon_detect()
  427. {
  428. serial_detect(&avalon_api, avalon_detect_one);
  429. }
  430. static bool avalon_prepare(struct thr_info *thr)
  431. {
  432. struct avalon_result ar;
  433. struct cgpu_info *avalon = thr->cgpu;
  434. struct timeval now;
  435. int fd, ret;
  436. avalon->device_fd = -1;
  437. fd = avalon_open(avalon->device_path,
  438. avalon_info[avalon->device_id]->baud);
  439. if (unlikely(fd == -1)) {
  440. applog(LOG_ERR, "Avalon: Failed to open on %s",
  441. avalon->device_path);
  442. return false;
  443. }
  444. ret = avalon_reset(fd, &ar);
  445. if (ret)
  446. return false;
  447. avalon->device_fd = fd;
  448. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  449. gettimeofday(&now, NULL);
  450. get_datestamp(avalon->init, &now);
  451. return true;
  452. }
  453. static void avalon_free_work(struct thr_info *thr, struct work **work)
  454. {
  455. struct cgpu_info *avalon;
  456. struct avalon_info *info;
  457. int i;
  458. if (unlikely(!work))
  459. return;
  460. avalon = thr->cgpu;
  461. info = avalon_info[avalon->device_id];
  462. for (i = 0; i < info->miner_count; i++)
  463. if (likely(work[i])) {
  464. free_work(work[i]);
  465. work[i] = NULL;
  466. }
  467. }
  468. static void do_avalon_close(struct thr_info *thr)
  469. {
  470. struct cgpu_info *avalon = thr->cgpu;
  471. struct avalon_info *info = avalon_info[avalon->device_id];
  472. avalon_close(avalon->device_fd);
  473. avalon->device_fd = -1;
  474. info->no_matching_work = 0;
  475. avalon_free_work(thr, info->bulk0);
  476. avalon_free_work(thr, info->bulk1);
  477. avalon_free_work(thr, info->bulk2);
  478. avalon_free_work(thr, info->bulk3);
  479. }
  480. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  481. {
  482. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  483. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  484. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  485. info->temp0 = ar->temp0;
  486. info->temp1 = ar->temp1;
  487. info->temp2 = ar->temp2;
  488. if (ar->temp0 & 0x80) {
  489. ar->temp0 &= 0x7f;
  490. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  491. }
  492. if (ar->temp1 & 0x80) {
  493. ar->temp1 &= 0x7f;
  494. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  495. }
  496. if (ar->temp2 & 0x80) {
  497. ar->temp2 &= 0x7f;
  498. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  499. }
  500. if (info->temp0 > info->temp_max)
  501. info->temp_max = info->temp0;
  502. if (info->temp1 > info->temp_max)
  503. info->temp_max = info->temp1;
  504. if (info->temp2 > info->temp_max)
  505. info->temp_max = info->temp2;
  506. *temp_avg = info->temp2;
  507. }
  508. static void adjust_temp(struct avalon_info *info)
  509. {
  510. int temp_new;
  511. temp_new = info->temp_sum / info->temp_history_count;
  512. if (temp_new < 40)
  513. info->fan_pwm = 0xA;
  514. else if (temp_new > 60)
  515. info->fan_pwm = AVALON_DEFAULT_FAN_PWM;
  516. else if (abs(temp_new - info->temp_old) >= 2) {
  517. info->fan_pwm = (temp_new - 40) * 9 + 10;
  518. info->temp_old = temp_new;
  519. }
  520. }
  521. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  522. __maybe_unused int64_t max_nonce)
  523. {
  524. struct cgpu_info *avalon;
  525. int fd, ret, full;
  526. struct avalon_info *info;
  527. struct avalon_task at;
  528. struct avalon_result ar;
  529. int i, work_i0, work_i1, work_i2, work_i3;
  530. int avalon_get_work_count;
  531. struct timeval tv_start, tv_finish, elapsed;
  532. uint32_t nonce;
  533. int64_t hash_count;
  534. static int first_try = 0;
  535. avalon = thr->cgpu;
  536. info = avalon_info[avalon->device_id];
  537. avalon_get_work_count = info->miner_count;
  538. if (unlikely(avalon->device_fd == -1))
  539. if (!avalon_prepare(thr)) {
  540. applog(LOG_ERR, "AVA%i: Comms error(open)",
  541. avalon->device_id);
  542. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  543. /* fail the device if the reopen attempt fails */
  544. return -1;
  545. }
  546. fd = avalon->device_fd;
  547. #ifndef WIN32
  548. tcflush(fd, TCOFLUSH);
  549. #endif
  550. for (i = 0; i < avalon_get_work_count; i++) {
  551. info->bulk0[i] = info->bulk1[i];
  552. info->bulk1[i] = info->bulk2[i];
  553. info->bulk2[i] = info->bulk3[i];
  554. info->bulk3[i] = work[i];
  555. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  556. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  557. }
  558. i = 0;
  559. while (true) {
  560. avalon_init_task(&at, 0, 0, info->fan_pwm,
  561. info->timeout, info->asic_count,
  562. info->miner_count, 1);
  563. avalon_create_task(&at, work[i]);
  564. ret = avalon_send_task(fd, &at, thr);
  565. if (unlikely(ret == AVA_SEND_ERROR ||
  566. (ret == AVA_SEND_BUFFER_EMPTY &&
  567. (i + 1 == avalon_get_work_count) &&
  568. first_try))) {
  569. avalon_free_work(thr, info->bulk0);
  570. avalon_free_work(thr, info->bulk1);
  571. avalon_free_work(thr, info->bulk2);
  572. avalon_free_work(thr, info->bulk3);
  573. do_avalon_close(thr);
  574. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  575. avalon->device_id);
  576. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  577. first_try = 0;
  578. sleep(1);
  579. return 0; /* This should never happen */
  580. }
  581. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  582. first_try = 1;
  583. return 0xffffffff;
  584. }
  585. work[i]->blk.nonce = 0xffffffff;
  586. if (ret == AVA_SEND_BUFFER_FULL)
  587. break;
  588. i++;
  589. }
  590. if (unlikely(first_try))
  591. first_try = 0;
  592. elapsed.tv_sec = elapsed.tv_usec = 0;
  593. gettimeofday(&tv_start, NULL);
  594. hash_count = 0;
  595. while (true) {
  596. work_i0 = work_i1 = work_i2 = -1;
  597. full = avalon_buffer_full(fd);
  598. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  599. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  600. if (unlikely(full == AVA_BUFFER_EMPTY))
  601. break;
  602. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  603. if (unlikely(ret == AVA_GETS_ERROR)) {
  604. avalon_free_work(thr, info->bulk0);
  605. avalon_free_work(thr, info->bulk1);
  606. avalon_free_work(thr, info->bulk2);
  607. avalon_free_work(thr, info->bulk3);
  608. do_avalon_close(thr);
  609. applog(LOG_ERR,
  610. "AVA%i: Comms error(read)", avalon->device_id);
  611. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  612. return 0;
  613. }
  614. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  615. timersub(&tv_finish, &tv_start, &elapsed);
  616. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  617. elapsed.tv_sec, elapsed.tv_usec);
  618. continue;
  619. }
  620. if (unlikely(ret == AVA_GETS_RESTART)) {
  621. avalon_free_work(thr, info->bulk0);
  622. avalon_free_work(thr, info->bulk1);
  623. avalon_free_work(thr, info->bulk2);
  624. avalon_free_work(thr, info->bulk3);
  625. continue;
  626. }
  627. record_temp_fan(info, &ar, &(avalon->temp));
  628. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  629. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  630. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  631. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  632. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  633. if (opt_debug) {
  634. timersub(&tv_finish, &tv_start, &elapsed);
  635. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  636. " (%ld.%06lds)", ++info->no_matching_work,
  637. elapsed.tv_sec, elapsed.tv_usec);
  638. }
  639. continue;
  640. }
  641. if (work_i0 >= 0)
  642. submit_nonce(thr, info->bulk0[work_i0], nonce);
  643. if (work_i1 >= 0)
  644. submit_nonce(thr, info->bulk1[work_i1], nonce);
  645. if (work_i2 >= 0)
  646. submit_nonce(thr, info->bulk2[work_i2], nonce);
  647. if (work_i3 >= 0)
  648. submit_nonce(thr, info->bulk3[work_i3], nonce);
  649. hash_count += nonce;
  650. if (opt_debug) {
  651. timersub(&tv_finish, &tv_start, &elapsed);
  652. applog(LOG_DEBUG,
  653. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  654. "(%ld.%06lds)", nonce, hash_count,
  655. elapsed.tv_sec, elapsed.tv_usec);
  656. }
  657. }
  658. avalon_free_work(thr, info->bulk0);
  659. applog(LOG_WARNING,
  660. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  661. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  662. info->fan0, info->fan1, info->fan2,
  663. info->temp0, info->temp1, info->temp2, info->temp_max);
  664. info->temp_history_index++;
  665. info->temp_sum += info->temp2;
  666. applog(LOG_DEBUG, "Avalon: temp_hist: %d, temp_count: %d, temp_old: %d",
  667. info->temp_history_index, info->temp_history_count, info->temp_old);
  668. if (info->temp_history_index == info->temp_history_count) {
  669. adjust_temp(info);
  670. info->temp_history_index = 0;
  671. info->temp_sum = 0;
  672. }
  673. /*
  674. * FIXME: Each work split to 10 pieces, each piece send to a
  675. * asic(256MHs). one work can be mulit-nonce back. it is not
  676. * easy calculate correct hash on such situation. so I simplely
  677. * add each nonce to hash_count. base on Utility/m hash_count*2
  678. * give a very good result.
  679. *
  680. * Any patch will be great.
  681. */
  682. return (hash_count * 2);
  683. }
  684. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  685. {
  686. struct api_data *root = NULL;
  687. struct avalon_info *info = avalon_info[cgpu->device_id];
  688. root = api_add_int(root, "read_count", &(info->read_count), false);
  689. root = api_add_int(root, "baud", &(info->baud), false);
  690. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  691. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  692. root = api_add_int(root, "fan1", &(info->fan0), false);
  693. root = api_add_int(root, "fan2", &(info->fan1), false);
  694. root = api_add_int(root, "fan3", &(info->fan2), false);
  695. root = api_add_int(root, "temp1", &(info->temp0), false);
  696. root = api_add_int(root, "temp2", &(info->temp1), false);
  697. root = api_add_int(root, "temp3", &(info->temp2), false);
  698. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  699. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  700. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  701. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  702. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  703. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  704. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  705. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  706. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  707. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  708. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  709. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  710. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  711. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  712. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  713. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  714. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  715. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  716. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  717. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  718. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  719. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  720. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  721. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  722. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  723. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  724. return root;
  725. }
  726. static void avalon_shutdown(struct thr_info *thr)
  727. {
  728. do_avalon_close(thr);
  729. }
  730. struct device_api avalon_api = {
  731. .dname = "avalon",
  732. .name = "AVA",
  733. .api_detect = avalon_detect,
  734. .thread_prepare = avalon_prepare,
  735. .scanhash_queue = avalon_scanhash,
  736. .get_api_stats = avalon_api_stats,
  737. .thread_shutdown = avalon_shutdown,
  738. };