driver-avalon.c 36 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  41. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  42. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  43. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  44. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  45. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  46. bool opt_avalon_auto;
  47. static int option_offset = -1;
  48. struct device_drv avalon_drv;
  49. static int avalon_is_bitburner(struct cgpu_info *avalon)
  50. {
  51. return strcmp(avalon->drv->name, "BTB") == 0;
  52. }
  53. static int avalon_init_task(struct avalon_task *at,
  54. uint8_t reset, uint8_t ff, uint8_t fan,
  55. uint8_t timeout, uint8_t asic_num,
  56. uint8_t miner_num, uint8_t nonce_elf,
  57. uint8_t gate_miner, int frequency)
  58. {
  59. uint16_t *lefreq16;
  60. uint8_t *buf;
  61. static bool first = true;
  62. if (unlikely(!at))
  63. return -1;
  64. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  65. return -1;
  66. memset(at, 0, sizeof(struct avalon_task));
  67. if (unlikely(reset)) {
  68. at->reset = 1;
  69. at->fan_eft = 1;
  70. at->timer_eft = 1;
  71. first = true;
  72. }
  73. at->flush_fifo = (ff ? 1 : 0);
  74. at->fan_eft = (fan ? 1 : 0);
  75. if (unlikely(first && !at->reset)) {
  76. at->fan_eft = 1;
  77. at->timer_eft = 1;
  78. first = false;
  79. }
  80. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  81. at->timeout_data = timeout;
  82. at->asic_num = asic_num;
  83. at->miner_num = miner_num;
  84. at->nonce_elf = nonce_elf;
  85. at->gate_miner_elf = 1;
  86. at->asic_pll = 1;
  87. if (unlikely(gate_miner)) {
  88. at-> gate_miner = 1;
  89. at->asic_pll = 0;
  90. }
  91. buf = (uint8_t *)at;
  92. buf[5] = 0x00;
  93. buf[8] = 0x74;
  94. buf[9] = 0x01;
  95. buf[10] = 0x00;
  96. buf[11] = 0x00;
  97. lefreq16 = (uint16_t *)&buf[6];
  98. *lefreq16 = htole16(frequency * 8);
  99. return 0;
  100. }
  101. static inline void avalon_create_task(struct avalon_task *at,
  102. struct work *work)
  103. {
  104. memcpy(at->midstate, work->midstate, 32);
  105. memcpy(at->data, work->data + 64, 12);
  106. }
  107. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  108. {
  109. int err, amount;
  110. err = usb_write(avalon, buf, len, &amount, ep);
  111. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  112. avalon->device_id, err);
  113. if (unlikely(err != 0)) {
  114. applog(LOG_WARNING, "usb_write error on avalon_write");
  115. return AVA_SEND_ERROR;
  116. }
  117. if (amount != len) {
  118. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  119. return AVA_SEND_ERROR;
  120. }
  121. return AVA_SEND_OK;
  122. }
  123. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  124. {
  125. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  126. int delay, ret, i, ep = C_AVALON_TASK;
  127. struct avalon_info *info;
  128. uint32_t nonce_range;
  129. size_t nr_len;
  130. if (at->nonce_elf)
  131. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  132. else
  133. nr_len = AVALON_WRITE_SIZE;
  134. memcpy(buf, at, AVALON_WRITE_SIZE);
  135. if (at->nonce_elf) {
  136. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  137. for (i = 0; i < at->asic_num; i++) {
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  139. (i * nonce_range & 0xff000000) >> 24;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  141. (i * nonce_range & 0x00ff0000) >> 16;
  142. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  143. (i * nonce_range & 0x0000ff00) >> 8;
  144. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  145. (i * nonce_range & 0x000000ff) >> 0;
  146. }
  147. }
  148. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  149. uint8_t tt = 0;
  150. tt = (buf[0] & 0x0f) << 4;
  151. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  152. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  153. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  154. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  155. buf[0] = tt;
  156. tt = (buf[4] & 0x0f) << 4;
  157. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  158. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  159. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  160. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  161. buf[4] = tt;
  162. #endif
  163. info = avalon->device_data;
  164. delay = nr_len * 10 * 1000000;
  165. delay = delay / info->baud;
  166. if (at->reset) {
  167. ep = C_AVALON_RESET;
  168. nr_len = 1;
  169. }
  170. if (opt_debug) {
  171. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  172. hexdump(buf, nr_len);
  173. }
  174. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  175. delay += 4000;
  176. nusleep(delay);
  177. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  178. return ret;
  179. }
  180. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  181. struct avalon_info *info, struct avalon_result *ar,
  182. struct work *work)
  183. {
  184. uint32_t nonce;
  185. info = avalon->device_data;
  186. info->matching_work[work->subid]++;
  187. nonce = htole32(ar->nonce);
  188. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  189. return submit_nonce(thr, work, nonce);
  190. }
  191. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  192. static void wait_avalon_ready(struct cgpu_info *avalon)
  193. {
  194. while (avalon_buffer_full(avalon)) {
  195. nmsleep(40);
  196. }
  197. }
  198. #define AVALON_CTS (1 << 4)
  199. static inline bool avalon_cts(char c)
  200. {
  201. return (c & AVALON_CTS);
  202. }
  203. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  204. size_t bufsize, int timeout, int ep)
  205. {
  206. struct avalon_info *info = avalon->device_data;
  207. size_t total = 0, readsize = bufsize + 2;
  208. char readbuf[AVALON_READBUF_SIZE];
  209. int err, amount, ofs = 2, cp;
  210. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  211. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  212. avalon->drv->name, avalon->device_id, err);
  213. if (amount < 2)
  214. goto out;
  215. /* Use the fact that we're reading the status with the buffer to tell
  216. * the write thread it should send more work without needing to call
  217. * avalon_buffer_full directly. */
  218. if (avalon_cts(buf[0]))
  219. cgsem_post(&info->write_sem);
  220. /* The first 2 of every 64 bytes are status on FTDIRL */
  221. while (amount > 2) {
  222. cp = amount - 2;
  223. if (cp > 62)
  224. cp = 62;
  225. memcpy(&buf[total], &readbuf[ofs], cp);
  226. total += cp;
  227. amount -= cp + 2;
  228. ofs += 64;
  229. }
  230. out:
  231. return total;
  232. }
  233. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  234. {
  235. struct avalon_result ar;
  236. int ret, i, spare;
  237. struct avalon_task at;
  238. uint8_t *buf, *tmp;
  239. struct timespec p;
  240. /* Send reset, then check for result */
  241. avalon_init_task(&at, 1, 0,
  242. AVALON_DEFAULT_FAN_MAX_PWM,
  243. AVALON_DEFAULT_TIMEOUT,
  244. AVALON_DEFAULT_ASIC_NUM,
  245. AVALON_DEFAULT_MINER_NUM,
  246. 0, 0,
  247. AVALON_DEFAULT_FREQUENCY);
  248. wait_avalon_ready(avalon);
  249. ret = avalon_send_task(&at, avalon);
  250. if (unlikely(ret == AVA_SEND_ERROR))
  251. return -1;
  252. if (!initial) {
  253. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  254. return 0;
  255. }
  256. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  257. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  258. /* What do these sleeps do?? */
  259. p.tv_sec = 0;
  260. p.tv_nsec = AVALON_RESET_PITCH;
  261. nanosleep(&p, NULL);
  262. /* Look for the first occurrence of 0xAA, the reset response should be:
  263. * AA 55 AA 55 00 00 00 00 00 00 */
  264. spare = ret - 10;
  265. buf = tmp = (uint8_t *)&ar;
  266. if (opt_debug) {
  267. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  268. hexdump(tmp, AVALON_READ_SIZE);
  269. }
  270. for (i = 0; i <= spare; i++) {
  271. buf = &tmp[i];
  272. if (buf[0] == 0xAA)
  273. break;
  274. }
  275. i = 0;
  276. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  277. buf[2] == 0xAA && buf[3] == 0x55) {
  278. for (i = 4; i < 11; i++)
  279. if (buf[i] != 0)
  280. break;
  281. }
  282. if (i != 11) {
  283. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  284. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  285. i, buf[0], buf[1], buf[2], buf[3]);
  286. /* FIXME: return 1; */
  287. } else
  288. applog(LOG_WARNING, "%s%d: Reset succeeded",
  289. avalon->drv->name, avalon->device_id);
  290. return 0;
  291. }
  292. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  293. int *asic_count, int *timeout, int *frequency)
  294. {
  295. char buf[BUFSIZ+1];
  296. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  297. size_t max;
  298. int i, tmp;
  299. if (opt_avalon_options == NULL)
  300. buf[0] = '\0';
  301. else {
  302. ptr = opt_avalon_options;
  303. for (i = 0; i < this_option_offset; i++) {
  304. comma = strchr(ptr, ',');
  305. if (comma == NULL)
  306. break;
  307. ptr = comma + 1;
  308. }
  309. comma = strchr(ptr, ',');
  310. if (comma == NULL)
  311. max = strlen(ptr);
  312. else
  313. max = comma - ptr;
  314. if (max > BUFSIZ)
  315. max = BUFSIZ;
  316. strncpy(buf, ptr, max);
  317. buf[max] = '\0';
  318. }
  319. if (!(*buf))
  320. return false;
  321. colon = strchr(buf, ':');
  322. if (colon)
  323. *(colon++) = '\0';
  324. tmp = atoi(buf);
  325. switch (tmp) {
  326. case 115200:
  327. *baud = 115200;
  328. break;
  329. case 57600:
  330. *baud = 57600;
  331. break;
  332. case 38400:
  333. *baud = 38400;
  334. break;
  335. case 19200:
  336. *baud = 19200;
  337. break;
  338. default:
  339. quit(1, "Invalid avalon-options for baud (%s) "
  340. "must be 115200, 57600, 38400 or 19200", buf);
  341. }
  342. if (colon && *colon) {
  343. colon2 = strchr(colon, ':');
  344. if (colon2)
  345. *(colon2++) = '\0';
  346. if (*colon) {
  347. tmp = atoi(colon);
  348. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  349. *miner_count = tmp;
  350. } else {
  351. quit(1, "Invalid avalon-options for "
  352. "miner_count (%s) must be 1 ~ %d",
  353. colon, AVALON_DEFAULT_MINER_NUM);
  354. }
  355. }
  356. if (colon2 && *colon2) {
  357. colon3 = strchr(colon2, ':');
  358. if (colon3)
  359. *(colon3++) = '\0';
  360. tmp = atoi(colon2);
  361. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  362. *asic_count = tmp;
  363. else {
  364. quit(1, "Invalid avalon-options for "
  365. "asic_count (%s) must be 1 ~ %d",
  366. colon2, AVALON_DEFAULT_ASIC_NUM);
  367. }
  368. if (colon3 && *colon3) {
  369. colon4 = strchr(colon3, ':');
  370. if (colon4)
  371. *(colon4++) = '\0';
  372. tmp = atoi(colon3);
  373. if (tmp > 0 && tmp <= 0xff)
  374. *timeout = tmp;
  375. else {
  376. quit(1, "Invalid avalon-options for "
  377. "timeout (%s) must be 1 ~ %d",
  378. colon3, 0xff);
  379. }
  380. if (colon4 && *colon4) {
  381. tmp = atoi(colon4);
  382. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  383. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  384. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  385. }
  386. *frequency = tmp;
  387. }
  388. }
  389. }
  390. }
  391. return true;
  392. }
  393. char *set_avalon_fan(char *arg)
  394. {
  395. int val1, val2, ret;
  396. ret = sscanf(arg, "%d-%d", &val1, &val2);
  397. if (ret < 1)
  398. return "No values passed to avalon-fan";
  399. if (ret == 1)
  400. val2 = val1;
  401. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  402. return "Invalid value passed to avalon-fan";
  403. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  404. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  405. return NULL;
  406. }
  407. char *set_avalon_freq(char *arg)
  408. {
  409. int val1, val2, ret;
  410. ret = sscanf(arg, "%d-%d", &val1, &val2);
  411. if (ret < 1)
  412. return "No values passed to avalon-freq";
  413. if (ret == 1)
  414. val2 = val1;
  415. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  416. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  417. val2 < val1)
  418. return "Invalid value passed to avalon-freq";
  419. opt_avalon_freq_min = val1;
  420. opt_avalon_freq_max = val2;
  421. return NULL;
  422. }
  423. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  424. {
  425. int i;
  426. wait_avalon_ready(avalon);
  427. /* Send idle to all miners */
  428. for (i = 0; i < info->miner_count; i++) {
  429. struct avalon_task at;
  430. if (unlikely(avalon_buffer_full(avalon)))
  431. break;
  432. info->idle++;
  433. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  434. info->asic_count, info->miner_count, 1, 1,
  435. info->frequency);
  436. avalon_send_task(&at, avalon);
  437. }
  438. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  439. wait_avalon_ready(avalon);
  440. }
  441. static void avalon_initialise(struct cgpu_info *avalon)
  442. {
  443. int err, interface;
  444. if (avalon->usbinfo.nodev)
  445. return;
  446. interface = avalon->usbdev->found->interface;
  447. // Reset
  448. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  449. FTDI_VALUE_RESET, interface, C_RESET);
  450. applog(LOG_DEBUG, "%s%i: reset got err %d",
  451. avalon->drv->name, avalon->device_id, err);
  452. if (avalon->usbinfo.nodev)
  453. return;
  454. // Set latency
  455. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  456. AVALON_LATENCY, interface, C_LATENCY);
  457. applog(LOG_DEBUG, "%s%i: latency got err %d",
  458. avalon->drv->name, avalon->device_id, err);
  459. if (avalon->usbinfo.nodev)
  460. return;
  461. // Set data
  462. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  463. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  464. applog(LOG_DEBUG, "%s%i: data got err %d",
  465. avalon->drv->name, avalon->device_id, err);
  466. if (avalon->usbinfo.nodev)
  467. return;
  468. // Set the baud
  469. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  470. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  471. C_SETBAUD);
  472. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  473. avalon->drv->name, avalon->device_id, err);
  474. if (avalon->usbinfo.nodev)
  475. return;
  476. // Set Modem Control
  477. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  478. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  479. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  480. avalon->drv->name, avalon->device_id, err);
  481. if (avalon->usbinfo.nodev)
  482. return;
  483. // Set Flow Control
  484. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  485. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  486. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  487. avalon->drv->name, avalon->device_id, err);
  488. if (avalon->usbinfo.nodev)
  489. return;
  490. /* Avalon repeats the following */
  491. // Set Modem Control
  492. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  493. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  494. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  495. avalon->drv->name, avalon->device_id, err);
  496. if (avalon->usbinfo.nodev)
  497. return;
  498. // Set Flow Control
  499. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  500. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  501. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  502. avalon->drv->name, avalon->device_id, err);
  503. }
  504. static void bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  505. {
  506. uint8_t buf[2];
  507. int err;
  508. if (avalon_is_bitburner(avalon)) {
  509. buf[0] = (uint8_t)core_voltage;
  510. buf[1] = (uint8_t)(core_voltage >> 8);
  511. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  512. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  513. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  514. if (unlikely(err < 0)) {
  515. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  516. avalon->drv->name, avalon->device_id, err);
  517. } else {
  518. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  519. avalon->drv->name, avalon->device_id,
  520. core_voltage);
  521. }
  522. }
  523. }
  524. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  525. {
  526. uint8_t buf[2];
  527. int err;
  528. int amount;
  529. if (avalon_is_bitburner(avalon)) {
  530. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  531. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  532. (char *)buf, sizeof(buf), &amount,
  533. C_BB_GET_VOLTAGE);
  534. if (unlikely(err != 0 || amount != 2)) {
  535. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  536. avalon->drv->name, avalon->device_id, err, amount);
  537. return 0;
  538. } else {
  539. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  540. }
  541. } else {
  542. return 0;
  543. }
  544. }
  545. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  546. {
  547. int baud, miner_count, asic_count, timeout, frequency = 0;
  548. int this_option_offset = ++option_offset;
  549. struct avalon_info *info;
  550. struct cgpu_info *avalon;
  551. bool configured;
  552. int ret;
  553. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  554. configured = get_options(this_option_offset, &baud, &miner_count,
  555. &asic_count, &timeout, &frequency);
  556. if (!usb_init(avalon, dev, found))
  557. goto shin;
  558. /* Even though this is an FTDI type chip, we want to do the parsing
  559. * all ourselves so set it to std usb type */
  560. avalon->usbdev->usb_type = USB_TYPE_STD;
  561. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  562. /* We have a real Avalon! */
  563. avalon_initialise(avalon);
  564. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  565. if (unlikely(!(avalon->device_data)))
  566. quit(1, "Failed to calloc avalon_info data");
  567. info = avalon->device_data;
  568. if (configured) {
  569. info->baud = baud;
  570. info->miner_count = miner_count;
  571. info->asic_count = asic_count;
  572. info->timeout = timeout;
  573. info->frequency = frequency;
  574. } else {
  575. info->baud = AVALON_IO_SPEED;
  576. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  577. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  578. info->timeout = AVALON_DEFAULT_TIMEOUT;
  579. info->frequency = AVALON_DEFAULT_FREQUENCY;
  580. }
  581. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  582. info->temp_max = 0;
  583. /* This is for check the temp/fan every 3~4s */
  584. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  585. if (info->temp_history_count <= 0)
  586. info->temp_history_count = 1;
  587. info->temp_history_index = 0;
  588. info->temp_sum = 0;
  589. info->temp_old = 0;
  590. if (!add_cgpu(avalon))
  591. goto unshin;
  592. ret = avalon_reset(avalon, true);
  593. if (ret && !configured)
  594. goto unshin;
  595. update_usb_stats(avalon);
  596. avalon_idle(avalon, info);
  597. applog(LOG_DEBUG, "Avalon Detected: %s "
  598. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  599. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  600. info->frequency);
  601. if (avalon_is_bitburner(avalon) &&
  602. opt_bitburner_core_voltage != BITBURNER_DEFAULT_CORE_VOLTAGE)
  603. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  604. return true;
  605. unshin:
  606. usb_uninit(avalon);
  607. shin:
  608. free(avalon->device_data);
  609. avalon->device_data = NULL;
  610. avalon = usb_free_cgpu(avalon);
  611. return false;
  612. }
  613. static void avalon_detect(void)
  614. {
  615. usb_detect(&avalon_drv, avalon_detect_one);
  616. }
  617. static void avalon_init(struct cgpu_info *avalon)
  618. {
  619. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  620. }
  621. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  622. {
  623. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  624. (char *)ar->data, 64, 12);
  625. }
  626. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  627. struct avalon_result *ar);
  628. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  629. {
  630. applog(LOG_INFO, "%s%d: No matching work - HW error",
  631. thr->cgpu->drv->name, thr->cgpu->device_id);
  632. inc_hw_errors(thr);
  633. info->no_matching_work++;
  634. }
  635. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  636. struct thr_info *thr, char *buf, int *offset)
  637. {
  638. int i, spare = *offset - AVALON_READ_SIZE;
  639. bool found = false;
  640. for (i = 0; i <= spare; i++) {
  641. struct avalon_result *ar;
  642. struct work *work;
  643. ar = (struct avalon_result *)&buf[i];
  644. work = avalon_valid_result(avalon, ar);
  645. if (work) {
  646. bool gettemp = false;
  647. found = true;
  648. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  649. mutex_lock(&info->lock);
  650. if (!info->nonces++)
  651. gettemp = true;
  652. info->auto_nonces++;
  653. mutex_unlock(&info->lock);
  654. } else if (opt_avalon_auto) {
  655. mutex_lock(&info->lock);
  656. info->auto_hw++;
  657. mutex_unlock(&info->lock);
  658. }
  659. if (gettemp)
  660. avalon_update_temps(avalon, info, ar);
  661. break;
  662. }
  663. }
  664. if (!found) {
  665. spare = *offset - AVALON_READ_SIZE;
  666. /* We are buffering and haven't accumulated one more corrupt
  667. * work result. */
  668. if (spare < (int)AVALON_READ_SIZE)
  669. return;
  670. avalon_inc_nvw(info, thr);
  671. } else {
  672. spare = AVALON_READ_SIZE + i;
  673. if (i) {
  674. if (i >= (int)AVALON_READ_SIZE)
  675. avalon_inc_nvw(info, thr);
  676. else
  677. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  678. }
  679. }
  680. *offset -= spare;
  681. memmove(buf, buf + spare, *offset);
  682. }
  683. static void avalon_running_reset(struct cgpu_info *avalon,
  684. struct avalon_info *info)
  685. {
  686. avalon_reset(avalon, false);
  687. avalon_idle(avalon, info);
  688. avalon->results = 0;
  689. info->reset = false;
  690. }
  691. static void *avalon_get_results(void *userdata)
  692. {
  693. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  694. struct avalon_info *info = avalon->device_data;
  695. int offset = 0, read_delay = 0, ret = 0;
  696. const int rsize = AVALON_FTDI_READSIZE;
  697. char readbuf[AVALON_READBUF_SIZE];
  698. struct thr_info *thr = info->thr;
  699. struct timeval tv_start, tv_end;
  700. char threadname[24];
  701. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  702. RenameThread(threadname);
  703. while (likely(!avalon->shutdown)) {
  704. unsigned char buf[rsize];
  705. struct timeval tv_diff;
  706. int us_diff;
  707. if (offset >= (int)AVALON_READ_SIZE)
  708. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  709. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  710. /* This should never happen */
  711. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  712. offset = 0;
  713. }
  714. if (unlikely(info->reset)) {
  715. avalon_running_reset(avalon, info);
  716. /* Discard anything in the buffer */
  717. offset = 0;
  718. }
  719. /* As the usb read returns after just 1ms, sleep long enough
  720. * to leave the interface idle for writes to occur, but do not
  721. * sleep if we have been receiving data as more may be coming. */
  722. if (ret < 1) {
  723. cgtime(&tv_end);
  724. timersub(&tv_end, &tv_start, &tv_diff);
  725. /* Assume it has not been > 1 second so ignore tv_sec */
  726. us_diff = tv_diff.tv_usec;
  727. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  728. if (likely(read_delay >= 1000))
  729. nusleep(read_delay);
  730. }
  731. cgtime(&tv_start);
  732. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  733. C_AVALON_READ);
  734. if (ret < 1)
  735. continue;
  736. if (opt_debug) {
  737. applog(LOG_DEBUG, "Avalon: get:");
  738. hexdump((uint8_t *)buf, ret);
  739. }
  740. memcpy(&readbuf[offset], &buf, ret);
  741. offset += ret;
  742. }
  743. return NULL;
  744. }
  745. static void avalon_rotate_array(struct cgpu_info *avalon)
  746. {
  747. avalon->queued = 0;
  748. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  749. avalon->work_array = 0;
  750. }
  751. static void avalon_set_timeout(struct avalon_info *info)
  752. {
  753. info->timeout = AVALON_TIMEOUT_FACTOR / info->frequency;
  754. }
  755. static void avalon_inc_freq(struct avalon_info *info)
  756. {
  757. info->frequency += 2;
  758. if (info->frequency > opt_avalon_freq_max)
  759. info->frequency = opt_avalon_freq_max;
  760. avalon_set_timeout(info);
  761. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  762. info->frequency, info->timeout);
  763. }
  764. static void avalon_dec_freq(struct avalon_info *info)
  765. {
  766. info->frequency -= 1;
  767. if (info->frequency < opt_avalon_freq_min)
  768. info->frequency = opt_avalon_freq_min;
  769. avalon_set_timeout(info);
  770. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  771. info->frequency, info->timeout);
  772. }
  773. static void avalon_reset_auto(struct avalon_info *info)
  774. {
  775. info->auto_queued =
  776. info->auto_nonces =
  777. info->auto_hw = 0;
  778. }
  779. static void *avalon_send_tasks(void *userdata)
  780. {
  781. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  782. struct avalon_info *info = avalon->device_data;
  783. const int avalon_get_work_count = info->miner_count;
  784. char threadname[24];
  785. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  786. RenameThread(threadname);
  787. while (likely(!avalon->shutdown)) {
  788. int start_count, end_count, i, j, ret;
  789. struct avalon_task at;
  790. bool idled = false;
  791. while (avalon_buffer_full(avalon))
  792. cgsem_wait(&info->write_sem);
  793. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  794. mutex_lock(&info->lock);
  795. if (!info->optimal) {
  796. if (info->fan_pwm >= opt_avalon_fan_max) {
  797. applog(LOG_WARNING,
  798. "%s%i: Above optimal temperature, throttling",
  799. avalon->drv->name, avalon->device_id);
  800. avalon_dec_freq(info);
  801. }
  802. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  803. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  804. int total = info->auto_nonces + info->auto_hw;
  805. /* Try to keep hw errors < 2% */
  806. if (info->auto_hw * 100 < total)
  807. avalon_inc_freq(info);
  808. else if (info->auto_hw * 66 > total)
  809. avalon_dec_freq(info);
  810. }
  811. avalon_reset_auto(info);
  812. mutex_unlock(&info->lock);
  813. }
  814. mutex_lock(&info->qlock);
  815. start_count = avalon->work_array * avalon_get_work_count;
  816. end_count = start_count + avalon_get_work_count;
  817. for (i = start_count, j = 0; i < end_count; i++, j++) {
  818. if (avalon_buffer_full(avalon)) {
  819. applog(LOG_INFO,
  820. "%s%i: Buffer full after only %d of %d work queued",
  821. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  822. break;
  823. }
  824. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  825. avalon_init_task(&at, 0, 0, info->fan_pwm,
  826. info->timeout, info->asic_count,
  827. info->miner_count, 1, 0, info->frequency);
  828. avalon_create_task(&at, avalon->works[i]);
  829. info->auto_queued++;
  830. } else {
  831. int idle_freq = info->frequency;
  832. if (!info->idle++)
  833. idled = true;
  834. if (unlikely(info->overheat && opt_avalon_auto))
  835. idle_freq = AVALON_MIN_FREQUENCY;
  836. avalon_init_task(&at, 0, 0, info->fan_pwm,
  837. info->timeout, info->asic_count,
  838. info->miner_count, 1, 1, idle_freq);
  839. /* Reset the auto_queued count if we end up
  840. * idling any miners. */
  841. avalon_reset_auto(info);
  842. }
  843. ret = avalon_send_task(&at, avalon);
  844. if (unlikely(ret == AVA_SEND_ERROR)) {
  845. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  846. avalon->drv->name, avalon->device_id);
  847. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  848. info->reset = true;
  849. break;
  850. }
  851. }
  852. avalon_rotate_array(avalon);
  853. pthread_cond_signal(&info->qcond);
  854. mutex_unlock(&info->qlock);
  855. if (unlikely(idled)) {
  856. applog(LOG_WARNING, "%s%i: Idled %d miners",
  857. avalon->drv->name, avalon->device_id, idled);
  858. }
  859. }
  860. return NULL;
  861. }
  862. static bool avalon_prepare(struct thr_info *thr)
  863. {
  864. struct cgpu_info *avalon = thr->cgpu;
  865. struct avalon_info *info = avalon->device_data;
  866. free(avalon->works);
  867. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  868. AVALON_ARRAY_SIZE);
  869. if (!avalon->works)
  870. quit(1, "Failed to calloc avalon works in avalon_prepare");
  871. info->thr = thr;
  872. mutex_init(&info->lock);
  873. mutex_init(&info->qlock);
  874. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  875. quit(1, "Failed to pthread_cond_init avalon qcond");
  876. cgsem_init(&info->write_sem);
  877. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  878. quit(1, "Failed to create avalon read_thr");
  879. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  880. quit(1, "Failed to create avalon write_thr");
  881. avalon_init(avalon);
  882. return true;
  883. }
  884. static void do_avalon_close(struct thr_info *thr)
  885. {
  886. struct cgpu_info *avalon = thr->cgpu;
  887. struct avalon_info *info = avalon->device_data;
  888. pthread_join(info->read_thr, NULL);
  889. pthread_join(info->write_thr, NULL);
  890. avalon_running_reset(avalon, info);
  891. info->no_matching_work = 0;
  892. cgsem_destroy(&info->write_sem);
  893. }
  894. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  895. {
  896. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  897. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  898. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  899. info->temp0 = ar->temp0;
  900. info->temp1 = ar->temp1;
  901. info->temp2 = ar->temp2;
  902. if (ar->temp0 & 0x80) {
  903. ar->temp0 &= 0x7f;
  904. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  905. }
  906. if (ar->temp1 & 0x80) {
  907. ar->temp1 &= 0x7f;
  908. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  909. }
  910. if (ar->temp2 & 0x80) {
  911. ar->temp2 &= 0x7f;
  912. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  913. }
  914. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  915. if (info->temp0 > info->temp_max)
  916. info->temp_max = info->temp0;
  917. if (info->temp1 > info->temp_max)
  918. info->temp_max = info->temp1;
  919. if (info->temp2 > info->temp_max)
  920. info->temp_max = info->temp2;
  921. }
  922. static void temp_rise(struct avalon_info *info, int temp)
  923. {
  924. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  925. info->fan_pwm = AVALON_PWM_MAX;
  926. return;
  927. }
  928. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  929. info->fan_pwm += 10;
  930. else if (temp > opt_avalon_temp)
  931. info->fan_pwm += 5;
  932. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  933. info->fan_pwm += 1;
  934. else
  935. return;
  936. if (info->fan_pwm > opt_avalon_fan_max)
  937. info->fan_pwm = opt_avalon_fan_max;
  938. }
  939. static void temp_drop(struct avalon_info *info, int temp)
  940. {
  941. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  942. info->fan_pwm = opt_avalon_fan_min;
  943. return;
  944. }
  945. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  946. info->fan_pwm -= 10;
  947. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  948. info->fan_pwm -= 5;
  949. else if (temp < opt_avalon_temp)
  950. info->fan_pwm -= 1;
  951. if (info->fan_pwm < opt_avalon_fan_min)
  952. info->fan_pwm = opt_avalon_fan_min;
  953. }
  954. static inline void adjust_fan(struct avalon_info *info)
  955. {
  956. int temp_new;
  957. temp_new = info->temp_sum / info->temp_history_count;
  958. if (temp_new > info->temp_old)
  959. temp_rise(info, temp_new);
  960. else if (temp_new < info->temp_old)
  961. temp_drop(info, temp_new);
  962. else {
  963. /* temp_new == info->temp_old */
  964. if (temp_new > opt_avalon_temp)
  965. temp_rise(info, temp_new);
  966. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  967. temp_drop(info, temp_new);
  968. }
  969. info->temp_old = temp_new;
  970. if (info->temp_old <= opt_avalon_temp)
  971. info->optimal = true;
  972. else
  973. info->optimal = false;
  974. }
  975. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  976. struct avalon_result *ar)
  977. {
  978. record_temp_fan(info, ar, &(avalon->temp));
  979. applog(LOG_INFO,
  980. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  981. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  982. info->fan0, info->fan1, info->fan2,
  983. info->temp0, info->temp1, info->temp2, info->temp_max);
  984. info->temp_history_index++;
  985. info->temp_sum += avalon->temp;
  986. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  987. info->temp_history_index, info->temp_history_count, info->temp_old);
  988. if (avalon_is_bitburner(avalon)) {
  989. info->core_voltage = bitburner_get_core_voltage(avalon);
  990. }
  991. if (info->temp_history_index == info->temp_history_count) {
  992. adjust_fan(info);
  993. info->temp_history_index = 0;
  994. info->temp_sum = 0;
  995. }
  996. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  997. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  998. info->overheat = true;
  999. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1000. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1001. info->overheat = false;
  1002. }
  1003. }
  1004. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1005. {
  1006. struct avalon_info *info = avalon->device_data;
  1007. int lowfan = 10000;
  1008. if (avalon_is_bitburner(avalon)) {
  1009. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1010. } else {
  1011. /* Find the lowest fan speed of the ASIC cooling fans. */
  1012. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1013. lowfan = info->fan1;
  1014. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1015. lowfan = info->fan2;
  1016. tailsprintf(buf, bufsiz, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1017. }
  1018. }
  1019. /* We use a replacement algorithm to only remove references to work done from
  1020. * the buffer when we need the extra space for new work. */
  1021. static bool avalon_fill(struct cgpu_info *avalon)
  1022. {
  1023. struct avalon_info *info = avalon->device_data;
  1024. int subid, slot, mc;
  1025. struct work *work;
  1026. bool ret = true;
  1027. mc = info->miner_count;
  1028. mutex_lock(&info->qlock);
  1029. if (avalon->queued >= mc)
  1030. goto out_unlock;
  1031. work = get_queued(avalon);
  1032. if (unlikely(!work)) {
  1033. ret = false;
  1034. goto out_unlock;
  1035. }
  1036. subid = avalon->queued++;
  1037. work->subid = subid;
  1038. slot = avalon->work_array * mc + subid;
  1039. if (likely(avalon->works[slot]))
  1040. work_completed(avalon, avalon->works[slot]);
  1041. avalon->works[slot] = work;
  1042. if (avalon->queued < mc)
  1043. ret = false;
  1044. out_unlock:
  1045. mutex_unlock(&info->qlock);
  1046. return ret;
  1047. }
  1048. static int64_t avalon_scanhash(struct thr_info *thr)
  1049. {
  1050. struct cgpu_info *avalon = thr->cgpu;
  1051. struct avalon_info *info = avalon->device_data;
  1052. const int miner_count = info->miner_count;
  1053. struct timeval now, then, tdiff;
  1054. int64_t hash_count, us_timeout;
  1055. struct timespec abstime;
  1056. int ret;
  1057. /* Half nonce range */
  1058. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1059. tdiff.tv_sec = us_timeout / 1000000;
  1060. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  1061. cgtime(&now);
  1062. timeradd(&now, &tdiff, &then);
  1063. abstime.tv_sec = then.tv_sec;
  1064. abstime.tv_nsec = then.tv_usec * 1000;
  1065. /* Wait until avalon_send_tasks signals us that it has completed
  1066. * sending its work or a full nonce range timeout has occurred */
  1067. mutex_lock(&info->qlock);
  1068. ret = pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1069. mutex_unlock(&info->qlock);
  1070. /* If we timed out, avalon_send_tasks may be stuck waiting on the
  1071. * write_sem, so force it to check for avalon_buffer_full itself. */
  1072. if (ret)
  1073. cgsem_post(&info->write_sem);
  1074. mutex_lock(&info->lock);
  1075. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1076. avalon->results += info->nonces + info->idle;
  1077. if (avalon->results > miner_count)
  1078. avalon->results = miner_count;
  1079. if (!info->reset)
  1080. avalon->results--;
  1081. info->nonces = info->idle = 0;
  1082. mutex_unlock(&info->lock);
  1083. /* Check for nothing but consecutive bad results or consistently less
  1084. * results than we should be getting and reset the FPGA if necessary */
  1085. if (!avalon_is_bitburner(avalon)) {
  1086. if (avalon->results < -miner_count && !info->reset) {
  1087. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1088. avalon->drv->name, avalon->device_id);
  1089. info->reset = true;
  1090. }
  1091. }
  1092. if (unlikely(avalon->usbinfo.nodev)) {
  1093. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1094. avalon->drv->name, avalon->device_id);
  1095. avalon->shutdown = true;
  1096. }
  1097. /* This hashmeter is just a utility counter based on returned shares */
  1098. return hash_count;
  1099. }
  1100. static void avalon_flush_work(struct cgpu_info *avalon)
  1101. {
  1102. struct avalon_info *info = avalon->device_data;
  1103. mutex_lock(&info->qlock);
  1104. /* Will overwrite any work queued */
  1105. avalon->queued = 0;
  1106. pthread_cond_signal(&info->qcond);
  1107. mutex_unlock(&info->qlock);
  1108. }
  1109. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1110. {
  1111. struct api_data *root = NULL;
  1112. struct avalon_info *info = cgpu->device_data;
  1113. int i;
  1114. root = api_add_int(root, "baud", &(info->baud), false);
  1115. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1116. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1117. root = api_add_int(root, "timeout", &(info->timeout), false);
  1118. root = api_add_int(root, "frequency", &(info->frequency), false);
  1119. root = api_add_int(root, "fan1", &(info->fan0), false);
  1120. root = api_add_int(root, "fan2", &(info->fan1), false);
  1121. root = api_add_int(root, "fan3", &(info->fan2), false);
  1122. root = api_add_int(root, "temp1", &(info->temp0), false);
  1123. root = api_add_int(root, "temp2", &(info->temp1), false);
  1124. root = api_add_int(root, "temp3", &(info->temp2), false);
  1125. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1126. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1127. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1128. for (i = 0; i < info->miner_count; i++) {
  1129. char mcw[24];
  1130. sprintf(mcw, "match_work_count%d", i + 1);
  1131. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1132. }
  1133. return root;
  1134. }
  1135. static void avalon_shutdown(struct thr_info *thr)
  1136. {
  1137. do_avalon_close(thr);
  1138. }
  1139. struct device_drv avalon_drv = {
  1140. .drv_id = DRIVER_AVALON,
  1141. .dname = "avalon",
  1142. .name = "AVA",
  1143. .drv_detect = avalon_detect,
  1144. .thread_prepare = avalon_prepare,
  1145. .hash_work = hash_queued_work,
  1146. .queue_full = avalon_fill,
  1147. .scanwork = avalon_scanhash,
  1148. .flush_work = avalon_flush_work,
  1149. .get_api_stats = avalon_api_stats,
  1150. .get_statline_before = get_avalon_statline_before,
  1151. .reinit_device = avalon_init,
  1152. .thread_shutdown = avalon_shutdown,
  1153. };