driver-bitmain.c 67 KB

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  1. /*
  2. * Copyright 2012-2014 Lingchao Xu
  3. * Copyright 2015 Luke Dashjr
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <ctype.h>
  12. #include <limits.h>
  13. #include <math.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include <curl/curl.h>
  34. #include <uthash.h>
  35. #include "deviceapi.h"
  36. #include "miner.h"
  37. #include "driver-bitmain.h"
  38. #include "lowl-vcom.h"
  39. #include "util.h"
  40. const bool opt_bitmain_hwerror = true;
  41. const unsigned bitmain_poll_interval_us = 10000;
  42. const unsigned bitmain_work_poll_prio = 1024;
  43. BFG_REGISTER_DRIVER(bitmain_drv)
  44. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[];
  45. #define htole8(x) (x)
  46. #define BITMAIN_USING_CURL -2
  47. static
  48. struct cgpu_info *btm_alloc_cgpu(struct device_drv *drv, int threads)
  49. {
  50. struct cgpu_info *cgpu = calloc(1, sizeof(*cgpu));
  51. if (unlikely(!cgpu))
  52. quit(1, "Failed to calloc cgpu for %s in usb_alloc_cgpu", drv->dname);
  53. cgpu->drv = drv;
  54. cgpu->deven = DEV_ENABLED;
  55. cgpu->threads = threads;
  56. cgpu->device_fd = -1;
  57. struct bitmain_info *info = malloc(sizeof(*info));
  58. if (unlikely(!info))
  59. quit(1, "Failed to calloc bitmain_info data");
  60. cgpu->device_data = info;
  61. *info = (struct bitmain_info){
  62. .chain_num = BITMAIN_DEFAULT_CHAIN_NUM,
  63. .asic_num = BITMAIN_DEFAULT_ASIC_NUM,
  64. .timeout = BITMAIN_DEFAULT_TIMEOUT,
  65. .frequency = BITMAIN_DEFAULT_FREQUENCY,
  66. .voltage[0] = BITMAIN_DEFAULT_VOLTAGE0,
  67. .voltage[1] = BITMAIN_DEFAULT_VOLTAGE1,
  68. .diff = 255,
  69. .lowest_goal_diff = 255,
  70. .work_restart = true,
  71. };
  72. sprintf(info->frequency_t, "%d", BITMAIN_DEFAULT_FREQUENCY),
  73. strcpy(info->voltage_t, BITMAIN_DEFAULT_VOLTAGE_T);
  74. return cgpu;
  75. }
  76. static curl_socket_t bitmain_grab_socket_opensocket_cb(void *clientp, __maybe_unused curlsocktype purpose, struct curl_sockaddr *addr)
  77. {
  78. struct bitmain_info * const info = clientp;
  79. curl_socket_t sck = bfg_socket(addr->family, addr->socktype, addr->protocol);
  80. info->curl_sock = sck;
  81. return sck;
  82. }
  83. static
  84. bool btm_init(struct cgpu_info *cgpu, const char * devpath)
  85. {
  86. applog(LOG_DEBUG, "btm_init cgpu->device_fd=%d", cgpu->device_fd);
  87. int fd = -1;
  88. if(cgpu->device_fd >= 0) {
  89. return false;
  90. }
  91. struct bitmain_info *info = cgpu->device_data;
  92. if (!strncmp(devpath, "ip:", 3)) {
  93. CURL *curl = curl_easy_init();
  94. if (!curl)
  95. applogr(false, LOG_ERR, "%s: curl_easy_init failed", cgpu->drv->dname);
  96. // CURLINFO_LASTSOCKET is broken on Win64 (which has a wider SOCKET type than curl_easy_getinfo returns), so we use this hack for now
  97. info->curl_sock = -1;
  98. curl_easy_setopt(curl, CURLOPT_OPENSOCKETFUNCTION, bitmain_grab_socket_opensocket_cb);
  99. curl_easy_setopt(curl, CURLOPT_OPENSOCKETDATA, info);
  100. curl_easy_setopt(curl, CURLOPT_FRESH_CONNECT, 1);
  101. curl_easy_setopt(curl, CURLOPT_CONNECTTIMEOUT, 5);
  102. curl_easy_setopt(curl, CURLOPT_NOSIGNAL, 1);
  103. curl_easy_setopt(curl, CURLOPT_TCP_NODELAY, 1);
  104. curl_easy_setopt(curl, CURLOPT_CONNECT_ONLY, 1);
  105. curl_easy_setopt(curl, CURLOPT_URL, &devpath[3]);
  106. if (curl_easy_perform(curl)) {
  107. curl_easy_cleanup(curl);
  108. applogr(false, LOG_ERR, "%s: curl_easy_perform failed for %s", cgpu->drv->dname, &devpath[3]);
  109. }
  110. cgpu->device_path = strdup(devpath);
  111. cgpu->device_fd = BITMAIN_USING_CURL;
  112. info->device_curl = curl;
  113. return true;
  114. }
  115. fd = serial_open(devpath, 0, 1, false);
  116. if(fd == -1) {
  117. applog(LOG_DEBUG, "%s open %s error %d",
  118. cgpu->drv->dname, devpath, errno);
  119. return false;
  120. }
  121. cgpu->device_path = strdup(devpath);
  122. cgpu->device_fd = fd;
  123. applog(LOG_DEBUG, "btm_init open device fd = %d", cgpu->device_fd);
  124. return true;
  125. }
  126. static
  127. void btm_uninit(struct cgpu_info *cgpu)
  128. {
  129. struct bitmain_info * const info = cgpu->device_data;
  130. applog(LOG_DEBUG, "BTM uninit %s%i", cgpu->drv->name, cgpu->device_fd);
  131. // May have happened already during a failed initialisation
  132. // if release_cgpu() was called due to a USB NODEV(err)
  133. if (cgpu->device_fd >= 0) {
  134. serial_close(cgpu->device_fd);
  135. cgpu->device_fd = -1;
  136. }
  137. if (info->device_curl) {
  138. curl_easy_cleanup(info->device_curl);
  139. info->device_curl = NULL;
  140. }
  141. if(cgpu->device_path) {
  142. free((char*)cgpu->device_path);
  143. cgpu->device_path = NULL;
  144. }
  145. }
  146. bool bitmain_curl_all(const bool is_recv, const int fd, CURL * const curl, void *p, size_t remsz)
  147. {
  148. CURLcode (* const func)(CURL *, void *, size_t, size_t *) = is_recv ? (void*)curl_easy_recv : (void*)curl_easy_send;
  149. CURLcode r;
  150. size_t sz;
  151. while (remsz) {
  152. fd_set otherfds, thisfds;
  153. FD_ZERO(&otherfds);
  154. FD_ZERO(&thisfds);
  155. FD_SET(fd, &thisfds);
  156. select(fd + 1, is_recv ? &thisfds : &otherfds, is_recv ? &otherfds : &thisfds, &thisfds, NULL);
  157. r = func(curl, p, remsz, &sz);
  158. switch (r) {
  159. case CURLE_OK:
  160. remsz -= sz;
  161. p += sz;
  162. break;
  163. case CURLE_AGAIN:
  164. break;
  165. default:
  166. return false;
  167. }
  168. }
  169. return true;
  170. }
  171. static
  172. int btm_read(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  173. {
  174. int err = 0;
  175. //applog(LOG_DEBUG, "btm_read ----- %d -----", bufsize);
  176. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  177. struct bitmain_info * const info = cgpu->device_data;
  178. uint8_t headbuf[5];
  179. headbuf[0] = 0;
  180. pk_u32be(headbuf, 1, bufsize);
  181. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, headbuf, sizeof(headbuf)))
  182. return -1;
  183. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, headbuf, 4))
  184. return -1;
  185. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  186. return -1;
  187. size_t sz = upk_u32be(headbuf, 0);
  188. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, buf, sz))
  189. return -1;
  190. return sz;
  191. }
  192. err = read(cgpu->device_fd, buf, bufsize);
  193. return err;
  194. }
  195. static
  196. int btm_write(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  197. {
  198. int err = 0;
  199. //applog(LOG_DEBUG, "btm_write ----- %d -----", bufsize);
  200. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  201. struct bitmain_info * const info = cgpu->device_data;
  202. uint8_t headbuf[5];
  203. headbuf[0] = 1;
  204. pk_u32be(headbuf, 1, bufsize);
  205. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, headbuf, sizeof(headbuf)))
  206. return -1;
  207. if (!bitmain_curl_all(false, info->curl_sock, info->device_curl, buf, bufsize))
  208. return -1;
  209. if (!bitmain_curl_all( true, info->curl_sock, info->device_curl, headbuf, 4))
  210. return -1;
  211. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  212. return -1;
  213. return upk_u32be(headbuf, 0);
  214. }
  215. err = write(cgpu->device_fd, buf, bufsize);
  216. return err;
  217. }
  218. #ifdef WIN32
  219. #define BITMAIN_TEST
  220. #endif
  221. #define BITMAIN_TEST_PRINT_WORK 0
  222. #ifdef BITMAIN_TEST
  223. #define BITMAIN_TEST_NUM 19
  224. #define BITMAIN_TEST_USENUM 1
  225. int g_test_index = 0;
  226. const char btm_work_test_data[BITMAIN_TEST_NUM][256] = {
  227. "00000002ddc1ce5579dbec17f17fbb8f31ae218a814b2a0c1900f0d90000000100000000b58aa6ca86546b07a5a46698f736c7ca9c0eedc756d8f28ac33c20cc24d792675276f879190afc85b6888022000000800000000000000000000000000000000000000000000000000000000000000000",
  228. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000eb2d45233c5b02de50ddcb9049ba16040e0ba00e9750a474eec75891571d925b52dfda4a190266667145b02f000000800000000000000000000000000000000000000000000000000000000000000000",
  229. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000090c7d3743e0b0562e4f56d3dd35cece3c5e8275d0abb21bf7e503cb72bd7ed3b52dfda4a190266667bbb58d7000000800000000000000000000000000000000000000000000000000000000000000000",
  230. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000006e0561da06022bfbb42c5ecd74a46bfd91934f201b777e9155cc6c3674724ec652dfda4a19026666a0cd827b000000800000000000000000000000000000000000000000000000000000000000000000",
  231. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000000312f42ce4964cc23f2d8c039f106f25ddd58e10a1faed21b3bba4b0e621807b52dfda4a1902666629c9497d000000800000000000000000000000000000000000000000000000000000000000000000",
  232. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000033093a6540dbe8f7f3d19e3d2af05585ac58dafad890fa9a942e977334a23d6e52dfda4a190266665ae95079000000800000000000000000000000000000000000000000000000000000000000000000",
  233. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000bd7893057d06e69705bddf9a89c7bac6b40c5b32f15e2295fc8c5edf491ea24952dfda4a190266664b89b4d3000000800000000000000000000000000000000000000000000000000000000000000000",
  234. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000075e66f533e53837d14236a793ee4e493985642bc39e016b9e63adf14a584a2aa52dfda4a19026666ab5d638d000000800000000000000000000000000000000000000000000000000000000000000000",
  235. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d936f90c5db5f0fe1d017344443854fbf9e40a07a9b7e74fedc8661c23162bff52dfda4a19026666338e79cb000000800000000000000000000000000000000000000000000000000000000000000000",
  236. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d2c1a7d279a4355b017bc0a4b0a9425707786729f21ee18add3fda4252a31a4152dfda4a190266669bc90806000000800000000000000000000000000000000000000000000000000000000000000000",
  237. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000ad36d19f33d04ca779942843890bc3b083cec83a4b60b6c45cf7d21fc187746552dfda4a1902666675d81ab7000000800000000000000000000000000000000000000000000000000000000000000000",
  238. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000093b809cf82b76082eacb55bc35b79f31882ed0976fd102ef54783cd24341319b52dfda4a1902666642ab4e42000000800000000000000000000000000000000000000000000000000000000000000000",
  239. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000007411ff315430a7bbf41de8a685d457e82d5177c05640d6a4436a40f39e99667852dfda4a190266662affa4b5000000800000000000000000000000000000000000000000000000000000000000000000",
  240. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000001ad0db5b9e1e2b57c8d3654c160f5a51067521eab7e340a270639d97f00a3fa252dfda4a1902666601a47bb6000000800000000000000000000000000000000000000000000000000000000000000000",
  241. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000022e055c442c46bbe16df68603a26891f6e4cf85b90102b39fd7cadb602b4e34552dfda4a1902666695d33cea000000800000000000000000000000000000000000000000000000000000000000000000",
  242. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000009c8baf5a8a1e16de2d6ae949d5fec3ed751f10dcd4c99810f2ce08040fb9e31d52dfda4a19026666fe78849d000000800000000000000000000000000000000000000000000000000000000000000000",
  243. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000e5655532b414887f35eb4652bc7b11ebac12891f65bc08cbe0ce5b277b9e795152dfda4a19026666fcc0d1d1000000800000000000000000000000000000000000000000000000000000000000000000",
  244. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000f272c5508704e2b62dd1c30ea970372c40bf00f9203f9bf69d456b4a7fbfffe352dfda4a19026666c03d4399000000800000000000000000000000000000000000000000000000000000000000000000",
  245. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000fca3b4531ba627ad9b0e23cdd84c888952c23810df196e9c6db0bcecba6a830952dfda4a19026666c14009cb000000800000000000000000000000000000000000000000000000000000000000000000"
  246. };
  247. const char btm_work_test_midstate[BITMAIN_TEST_NUM][256] = {
  248. "2d8738e7f5bcf76dcb8316fec772e20e240cd58c88d47f2d3f5a6a9547ed0a35",
  249. "d31b6ce09c0bfc2af6f3fe3a03475ebefa5aa191fa70a327a354b2c22f9692f1",
  250. "84a8c8224b80d36caeb42eff2a100f634e1ff873e83fd02ef1306a34abef9dbe",
  251. "059882159439b9b32968c79a93c5521e769dbea9d840f56c2a17b9ad87e530b8",
  252. "17fa435d05012574f8f1da26994cc87b6cb9660b5e82072dc6a0881cec150a0d",
  253. "92a28cc5ec4ba6a2688471dfe2032b5fe97c805ca286c503e447d6749796c6af",
  254. "1677a03516d6e9509ac37e273d2482da9af6e077abe8392cdca6a30e916a7ae9",
  255. "50bbe09f1b8ac18c97aeb745d5d2c3b5d669b6ac7803e646f65ac7b763a392d1",
  256. "e46a0022ebdc303a7fb1a0ebfa82b523946c312e745e5b8a116b17ae6b4ce981",
  257. "8f2f61e7f5b4d76d854e6d266acfff4d40347548216838ccc4ef3b9e43d3c9ea",
  258. "0a450588ae99f75d676a08d0326e1ea874a3497f696722c78a80c7b6ee961ea6",
  259. "3c4c0fc2cf040b806c51b46de9ec0dcc678a7cc5cf3eff11c6c03de3bc7818cc",
  260. "f6c7c785ab5daddb8f98e5f854f2cb41879fcaf47289eb2b4196fefc1b28316f",
  261. "005312351ccb0d0794779f5023e4335b5cad221accf0dfa3da7b881266fa9f5a",
  262. "7b26d189c6bba7add54143179aadbba7ccaeff6887bd8d5bec9597d5716126e6",
  263. "a4718f4c801e7ddf913a9474eb71774993525684ffea1915f767ab16e05e6889",
  264. "6b6226a8c18919d0e55684638d33a6892a00d22492cc2f5906ca7a4ac21c74a7",
  265. "383114dccd1cb824b869158aa2984d157fcb02f46234ceca65943e919329e697",
  266. "d4d478df3016852b27cb1ae9e1e98d98617f8d0943bf9dc1217f47f817236222"
  267. };
  268. #endif
  269. bool opt_bitmain_checkall = false;
  270. bool opt_bitmain_nobeeper = false;
  271. bool opt_bitmain_notempoverctrl = false;
  272. bool opt_bitmain_homemode = false;
  273. bool opt_bitmain_auto;
  274. // --------------------------------------------------------------
  275. // CRC16 check table
  276. // --------------------------------------------------------------
  277. static
  278. const uint8_t chCRCHTalbe[] = // CRC high byte table
  279. {
  280. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  281. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  282. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  283. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  284. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  285. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  286. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  287. 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  288. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  289. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  290. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  291. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  292. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  293. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  294. 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  295. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  296. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  297. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  298. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  299. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  300. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  301. 0x00, 0xC1, 0x81, 0x40
  302. };
  303. static
  304. const uint8_t chCRCLTalbe[] = // CRC low byte table
  305. {
  306. 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
  307. 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
  308. 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
  309. 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
  310. 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
  311. 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
  312. 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
  313. 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
  314. 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
  315. 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
  316. 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
  317. 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
  318. 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
  319. 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
  320. 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
  321. 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
  322. 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
  323. 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
  324. 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
  325. 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
  326. 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
  327. 0x41, 0x81, 0x80, 0x40
  328. };
  329. static uint16_t CRC16(const uint8_t* p_data, uint16_t w_len)
  330. {
  331. uint8_t chCRCHi = 0xFF; // CRC high byte initialize
  332. uint8_t chCRCLo = 0xFF; // CRC low byte initialize
  333. uint16_t wIndex = 0; // CRC cycling index
  334. while (w_len--) {
  335. wIndex = chCRCLo ^ *p_data++;
  336. chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
  337. chCRCHi = chCRCLTalbe[wIndex];
  338. }
  339. return ((chCRCHi << 8) | chCRCLo);
  340. }
  341. static uint32_t num2bit(int num) {
  342. return 1L << (31 - num);
  343. }
  344. static int bitmain_set_txconfig(struct bitmain_txconfig_token *bm,
  345. uint8_t reset, uint8_t fan_eft, uint8_t timeout_eft, uint8_t frequency_eft,
  346. uint8_t voltage_eft, uint8_t chain_check_time_eft, uint8_t chip_config_eft, uint8_t hw_error_eft,
  347. uint8_t beeper_ctrl, uint8_t temp_over_ctrl,uint8_t fan_home_mode,
  348. uint8_t chain_num, uint8_t asic_num, uint8_t fan_pwm_data, uint8_t timeout_data,
  349. uint16_t frequency, uint8_t * voltage, uint8_t chain_check_time,
  350. uint8_t chip_address, uint8_t reg_address, uint8_t * reg_data)
  351. {
  352. uint16_t crc = 0;
  353. int datalen = 0;
  354. uint8_t version = 0;
  355. uint8_t * sendbuf = (uint8_t *)bm;
  356. if (unlikely(!bm)) {
  357. applog(LOG_WARNING, "bitmain_set_txconfig bitmain_txconfig_token is null");
  358. return -1;
  359. }
  360. if (unlikely(timeout_data <= 0 || asic_num <= 0 || chain_num <= 0)) {
  361. applog(LOG_WARNING, "bitmain_set_txconfig parameter invalid timeout_data(%d) asic_num(%d) chain_num(%d)",
  362. timeout_data, asic_num, chain_num);
  363. return -1;
  364. }
  365. datalen = sizeof(struct bitmain_txconfig_token);
  366. memset(bm, 0, datalen);
  367. bm->token_type = BITMAIN_TOKEN_TYPE_TXCONFIG;
  368. bm->version = version;
  369. bm->length = datalen-4;
  370. bm->length = htole16(bm->length);
  371. bm->reset = reset;
  372. bm->fan_eft = fan_eft;
  373. bm->timeout_eft = timeout_eft;
  374. bm->frequency_eft = frequency_eft;
  375. bm->voltage_eft = voltage_eft;
  376. bm->chain_check_time_eft = chain_check_time_eft;
  377. bm->chip_config_eft = chip_config_eft;
  378. bm->hw_error_eft = hw_error_eft;
  379. bm->beeper_ctrl = beeper_ctrl;
  380. bm->temp_over_ctrl = temp_over_ctrl;
  381. bm->fan_home_mode = fan_home_mode;
  382. sendbuf[4] = htole8(sendbuf[4]);
  383. sendbuf[5] = htole8(sendbuf[5]);
  384. bm->chain_num = chain_num;
  385. bm->asic_num = asic_num;
  386. bm->fan_pwm_data = fan_pwm_data;
  387. bm->timeout_data = timeout_data;
  388. bm->frequency = htole16(frequency);
  389. memcpy(bm->voltage, voltage, 2);
  390. bm->chain_check_time = chain_check_time;
  391. memcpy(bm->reg_data, reg_data, 4);
  392. bm->chip_address = chip_address;
  393. bm->reg_address = reg_address;
  394. crc = CRC16((uint8_t *)bm, datalen-2);
  395. bm->crc = htole16(crc);
  396. applog(LOG_ERR, "BTM TxConfigToken:v(%d) reset(%d) fan_e(%d) tout_e(%d) fq_e(%d) vt_e(%d) chainc_e(%d) chipc_e(%d) hw_e(%d) b_c(%d) t_c(%d) f_m(%d) mnum(%d) anum(%d) fanpwmdata(%d) toutdata(%d) freq(%d) volt(%02x%02x) chainctime(%d) regdata(%02x%02x%02x%02x) chipaddr(%02x) regaddr(%02x) crc(%04x)",
  397. version, reset, fan_eft, timeout_eft, frequency_eft, voltage_eft,
  398. chain_check_time_eft, chip_config_eft, hw_error_eft, beeper_ctrl, temp_over_ctrl,fan_home_mode,chain_num, asic_num,
  399. fan_pwm_data, timeout_data, frequency, voltage[0], voltage[1],
  400. chain_check_time, reg_data[0], reg_data[1], reg_data[2], reg_data[3], chip_address, reg_address, crc);
  401. return datalen;
  402. }
  403. static int bitmain_set_rxstatus(struct bitmain_rxstatus_token *bm,
  404. uint8_t chip_status_eft, uint8_t detect_get, uint8_t chip_address, uint8_t reg_address)
  405. {
  406. uint16_t crc = 0;
  407. uint8_t version = 0;
  408. int datalen = 0;
  409. uint8_t * sendbuf = (uint8_t *)bm;
  410. if (unlikely(!bm)) {
  411. applog(LOG_WARNING, "bitmain_set_rxstatus bitmain_rxstatus_token is null");
  412. return -1;
  413. }
  414. datalen = sizeof(struct bitmain_rxstatus_token);
  415. memset(bm, 0, datalen);
  416. bm->token_type = BITMAIN_TOKEN_TYPE_RXSTATUS;
  417. bm->version = version;
  418. bm->length = datalen-4;
  419. bm->length = htole16(bm->length);
  420. bm->chip_status_eft = chip_status_eft;
  421. bm->detect_get = detect_get;
  422. sendbuf[4] = htole8(sendbuf[4]);
  423. bm->chip_address = chip_address;
  424. bm->reg_address = reg_address;
  425. crc = CRC16((uint8_t *)bm, datalen-2);
  426. bm->crc = htole16(crc);
  427. applog(LOG_ERR, "BitMain RxStatus Token: v(%d) chip_status_eft(%d) detect_get(%d) chip_address(%02x) reg_address(%02x) crc(%04x)",
  428. version, chip_status_eft, detect_get, chip_address, reg_address, crc);
  429. return datalen;
  430. }
  431. static int bitmain_parse_rxstatus(const uint8_t * data, int datalen, struct bitmain_rxstatus_data *bm)
  432. {
  433. uint16_t crc = 0;
  434. uint8_t version = 0;
  435. int i = 0, j = 0;
  436. int asic_num = 0;
  437. int dataindex = 0;
  438. uint8_t tmp = 0x01;
  439. if (unlikely(!bm)) {
  440. applog(LOG_WARNING, "bitmain_parse_rxstatus bitmain_rxstatus_data is null");
  441. return -1;
  442. }
  443. if (unlikely(!data || datalen <= 0)) {
  444. applog(LOG_WARNING, "bitmain_parse_rxstatus parameter invalid data is null or datalen(%d) error", datalen);
  445. return -1;
  446. }
  447. memset(bm, 0, sizeof(struct bitmain_rxstatus_data));
  448. memcpy(bm, data, 28);
  449. if (bm->data_type != BITMAIN_DATA_TYPE_RXSTATUS) {
  450. applog(LOG_ERR, "bitmain_parse_rxstatus datatype(%02x) error", bm->data_type);
  451. return -1;
  452. }
  453. if (bm->version != version) {
  454. applog(LOG_ERR, "bitmain_parse_rxstatus version(%02x) error", bm->version);
  455. return -1;
  456. }
  457. bm->length = htole16(bm->length);
  458. if (bm->length+4 != datalen) {
  459. applog(LOG_ERR, "bitmain_parse_rxstatus length(%d) datalen(%d) error", bm->length, datalen);
  460. return -1;
  461. }
  462. crc = CRC16(data, datalen-2);
  463. memcpy(&(bm->crc), data+datalen-2, 2);
  464. bm->crc = htole16(bm->crc);
  465. if(crc != bm->crc) {
  466. applog(LOG_ERR, "bitmain_parse_rxstatus check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  467. return -1;
  468. }
  469. bm->fifo_space = htole16(bm->fifo_space);
  470. bm->fan_exist = htole16(bm->fan_exist);
  471. bm->temp_exist = htole32(bm->temp_exist);
  472. bm->nonce_error = htole32(bm->nonce_error);
  473. if(bm->chain_num > BITMAIN_MAX_CHAIN_NUM) {
  474. applog(LOG_ERR, "bitmain_parse_rxstatus chain_num=%d error", bm->chain_num);
  475. return -1;
  476. }
  477. dataindex = 28;
  478. if(bm->chain_num > 0) {
  479. memcpy(bm->chain_asic_num, data+datalen-2-bm->chain_num-bm->temp_num-bm->fan_num, bm->chain_num);
  480. }
  481. for(i = 0; i < bm->chain_num; i++) {
  482. asic_num = bm->chain_asic_num[i];
  483. if(asic_num <= 0) {
  484. asic_num = 1;
  485. } else {
  486. if(asic_num % 32 == 0) {
  487. asic_num = asic_num / 32;
  488. } else {
  489. asic_num = asic_num / 32 + 1;
  490. }
  491. }
  492. memcpy((uint8_t *)bm->chain_asic_exist+i*32, data+dataindex, asic_num*4);
  493. dataindex += asic_num*4;
  494. }
  495. for(i = 0; i < bm->chain_num; i++) {
  496. asic_num = bm->chain_asic_num[i];
  497. if(asic_num <= 0) {
  498. asic_num = 1;
  499. } else {
  500. if(asic_num % 32 == 0) {
  501. asic_num = asic_num / 32;
  502. } else {
  503. asic_num = asic_num / 32 + 1;
  504. }
  505. }
  506. memcpy((uint8_t *)bm->chain_asic_status+i*32, data+dataindex, asic_num*4);
  507. dataindex += asic_num*4;
  508. }
  509. dataindex += bm->chain_num;
  510. if(dataindex + bm->temp_num + bm->fan_num + 2 != datalen) {
  511. applog(LOG_ERR, "bitmain_parse_rxstatus dataindex(%d) chain_num(%d) temp_num(%d) fan_num(%d) not match datalen(%d)",
  512. dataindex, bm->chain_num, bm->temp_num, bm->fan_num, datalen);
  513. return -1;
  514. }
  515. for(i = 0; i < bm->chain_num; i++) {
  516. //bm->chain_asic_status[i] = swab32(bm->chain_asic_status[i]);
  517. for(j = 0; j < 8; j++) {
  518. bm->chain_asic_exist[i*8+j] = htole32(bm->chain_asic_exist[i*8+j]);
  519. bm->chain_asic_status[i*8+j] = htole32(bm->chain_asic_status[i*8+j]);
  520. }
  521. }
  522. if(bm->temp_num > 0) {
  523. memcpy(bm->temp, data+dataindex, bm->temp_num);
  524. dataindex += bm->temp_num;
  525. }
  526. if(bm->fan_num > 0) {
  527. memcpy(bm->fan, data+dataindex, bm->fan_num);
  528. dataindex += bm->fan_num;
  529. }
  530. if(!opt_bitmain_checkall){
  531. if(tmp != htole8(tmp)){
  532. applog(LOG_ERR, "BitMain RxStatus byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  533. memcpy(&tmp,data+4,1);
  534. bm->chip_value_eft = tmp >>7;
  535. bm->get_blk_num = tmp >> 4;
  536. bm->reserved1 = ((tmp << 4) & 0xff) >> 5;
  537. }
  538. found_blocks = bm->get_blk_num;
  539. applog(LOG_ERR, "BitMain RxStatus tmp :0x%02x byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",tmp,*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  540. }
  541. applog(LOG_DEBUG, "BitMain RxStatusData: chipv_e(%d) chainnum(%d) fifos(%d) v1(%d) v2(%d) v3(%d) v4(%d) fann(%d) tempn(%d) fanet(%04x) tempet(%08x) ne(%d) regvalue(%d) crc(%04x)",
  542. bm->chip_value_eft, bm->chain_num, bm->fifo_space, bm->hw_version[0], bm->hw_version[1], bm->hw_version[2], bm->hw_version[3], bm->fan_num, bm->temp_num, bm->fan_exist, bm->temp_exist, bm->nonce_error, bm->reg_value, bm->crc);
  543. applog(LOG_DEBUG, "BitMain RxStatus Data chain info:");
  544. for(i = 0; i < bm->chain_num; i++) {
  545. applog(LOG_DEBUG, "BitMain RxStatus Data chain(%d) asic num=%d asic_exist=%08x asic_status=%08x", i+1, bm->chain_asic_num[i], bm->chain_asic_exist[i*8], bm->chain_asic_status[i*8]);
  546. }
  547. applog(LOG_DEBUG, "BitMain RxStatus Data temp info:");
  548. for(i = 0; i < bm->temp_num; i++) {
  549. applog(LOG_DEBUG, "BitMain RxStatus Data temp(%d) temp=%d", i+1, bm->temp[i]);
  550. }
  551. applog(LOG_DEBUG, "BitMain RxStatus Data fan info:");
  552. for(i = 0; i < bm->fan_num; i++) {
  553. applog(LOG_DEBUG, "BitMain RxStatus Data fan(%d) fan=%d", i+1, bm->fan[i]);
  554. }
  555. return 0;
  556. }
  557. static int bitmain_parse_rxnonce(const uint8_t * data, int datalen, struct bitmain_rxnonce_data *bm, int * nonce_num)
  558. {
  559. int i = 0;
  560. uint16_t crc = 0;
  561. uint8_t version = 0;
  562. int curnoncenum = 0;
  563. if (unlikely(!bm)) {
  564. applog(LOG_ERR, "bitmain_parse_rxnonce bitmain_rxstatus_data null");
  565. return -1;
  566. }
  567. if (unlikely(!data || datalen <= 0)) {
  568. applog(LOG_ERR, "bitmain_parse_rxnonce data null or datalen(%d) error", datalen);
  569. return -1;
  570. }
  571. memcpy(bm, data, sizeof(struct bitmain_rxnonce_data));
  572. if (bm->data_type != BITMAIN_DATA_TYPE_RXNONCE) {
  573. applog(LOG_ERR, "bitmain_parse_rxnonce datatype(%02x) error", bm->data_type);
  574. return -1;
  575. }
  576. if (bm->version != version) {
  577. applog(LOG_ERR, "bitmain_parse_rxnonce version(%02x) error", bm->version);
  578. return -1;
  579. }
  580. bm->length = htole16(bm->length);
  581. if (bm->length+4 != datalen) {
  582. applog(LOG_ERR, "bitmain_parse_rxnonce length(%d) error", bm->length);
  583. return -1;
  584. }
  585. crc = CRC16(data, datalen-2);
  586. memcpy(&(bm->crc), data+datalen-2, 2);
  587. bm->crc = htole16(bm->crc);
  588. if(crc != bm->crc) {
  589. applog(LOG_ERR, "bitmain_parse_rxnonce check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  590. return -1;
  591. }
  592. bm->fifo_space = htole16(bm->fifo_space);
  593. bm->diff = htole16(bm->diff);
  594. bm->total_nonce_num = htole64(bm->total_nonce_num);
  595. curnoncenum = (datalen-14)/8;
  596. applog(LOG_DEBUG, "BitMain RxNonce Data: nonce_num(%d) fifo_space(%d) diff(%d) tnn(%"PRIu64")", curnoncenum, bm->fifo_space, bm->diff, bm->total_nonce_num);
  597. for(i = 0; i < curnoncenum; i++) {
  598. bm->nonces[i].work_id = htole32(bm->nonces[i].work_id);
  599. bm->nonces[i].nonce = htole32(bm->nonces[i].nonce);
  600. applog(LOG_DEBUG, "BitMain RxNonce Data %d: work_id(%d) nonce(%08x)(%d)",
  601. i, bm->nonces[i].work_id, bm->nonces[i].nonce, bm->nonces[i].nonce);
  602. }
  603. *nonce_num = curnoncenum;
  604. return 0;
  605. }
  606. static int bitmain_read(struct cgpu_info *bitmain, unsigned char *buf,
  607. size_t bufsize, int timeout)
  608. {
  609. int err = 0;
  610. size_t total = 0;
  611. if(bitmain == NULL || buf == NULL || bufsize <= 0) {
  612. applog(LOG_WARNING, "bitmain_read parameter error bufsize(%llu)", (unsigned long long)bufsize);
  613. return -1;
  614. }
  615. {
  616. err = btm_read(bitmain, buf, bufsize);
  617. total = err;
  618. }
  619. return total;
  620. }
  621. static int bitmain_write(struct cgpu_info *bitmain, char *buf, ssize_t len)
  622. {
  623. int err;
  624. {
  625. int havelen = 0;
  626. while(havelen < len) {
  627. err = btm_write(bitmain, buf+havelen, len-havelen);
  628. if(err < 0) {
  629. applog(LOG_DEBUG, "%s%i: btm_write got err %d", bitmain->drv->name,
  630. bitmain->device_id, err);
  631. applog(LOG_WARNING, "usb_write error on bitmain_write");
  632. return BTM_SEND_ERROR;
  633. } else {
  634. havelen += err;
  635. }
  636. }
  637. }
  638. return BTM_SEND_OK;
  639. }
  640. static int bitmain_send_data(const uint8_t * data, int datalen, struct cgpu_info *bitmain)
  641. {
  642. int ret;
  643. if(datalen <= 0) {
  644. return 0;
  645. }
  646. //struct bitmain_info *info = bitmain->device_data;
  647. //int delay;
  648. //delay = datalen * 10 * 1000000;
  649. //delay = delay / info->baud;
  650. //delay += 4000;
  651. if(opt_debug) {
  652. char hex[(datalen * 2) + 1];
  653. bin2hex(hex, data, datalen);
  654. applog(LOG_DEBUG, "BitMain: Sent(%d): %s", datalen, hex);
  655. }
  656. //cgtimer_t ts_start;
  657. //cgsleep_prepare_r(&ts_start);
  658. //applog(LOG_DEBUG, "----bitmain_send_data start");
  659. ret = bitmain_write(bitmain, (char *)data, datalen);
  660. applog(LOG_DEBUG, "----bitmain_send_data stop ret=%d datalen=%d", ret, datalen);
  661. //cgsleep_us_r(&ts_start, delay);
  662. //applog(LOG_DEBUG, "BitMain: Sent: Buffer delay: %dus", delay);
  663. return ret;
  664. }
  665. static void bitmain_inc_nvw(struct bitmain_info *info, struct thr_info *thr)
  666. {
  667. applog(LOG_INFO, "%s%d: No matching work - HW error",
  668. thr->cgpu->drv->name, thr->cgpu->device_id);
  669. inc_hw_errors_only(thr);
  670. info->no_matching_work++;
  671. }
  672. static inline void record_temp_fan(struct bitmain_info *info, struct bitmain_rxstatus_data *bm, float *temp)
  673. {
  674. int i = 0;
  675. int maxfan = 0, maxtemp = 0;
  676. int temp_avg = 0;
  677. info->fan_num = bm->fan_num;
  678. for(i = 0; i < bm->fan_num; i++) {
  679. info->fan[i] = bm->fan[i] * BITMAIN_FAN_FACTOR;
  680. if(info->fan[i] > maxfan)
  681. maxfan = info->fan[i];
  682. }
  683. info->temp_num = bm->temp_num;
  684. for(i = 0; i < bm->temp_num; i++) {
  685. info->temp[i] = bm->temp[i];
  686. /*
  687. if(bm->temp[i] & 0x80) {
  688. bm->temp[i] &= 0x7f;
  689. info->temp[i] = 0 - ((~bm->temp[i] & 0x7f) + 1);
  690. }*/
  691. temp_avg += info->temp[i];
  692. if(info->temp[i] > info->temp_max) {
  693. info->temp_max = info->temp[i];
  694. }
  695. if(info->temp[i] > maxtemp)
  696. maxtemp = info->temp[i];
  697. }
  698. if(bm->temp_num > 0) {
  699. temp_avg /= bm->temp_num;
  700. info->temp_avg = temp_avg;
  701. }
  702. *temp = maxtemp;
  703. }
  704. static void bitmain_update_temps(struct cgpu_info *bitmain, struct bitmain_info *info,
  705. struct bitmain_rxstatus_data *bm)
  706. {
  707. char tmp[64] = {0};
  708. char msg[10240] = {0};
  709. int i = 0;
  710. record_temp_fan(info, bm, &(bitmain->temp));
  711. strcpy(msg, "BitMain: ");
  712. for(i = 0; i < bm->fan_num; i++) {
  713. if(i != 0) {
  714. strcat(msg, ", ");
  715. }
  716. sprintf(tmp, "Fan%d: %d/m", i+1, info->fan[i]);
  717. strcat(msg, tmp);
  718. }
  719. strcat(msg, "\t");
  720. for(i = 0; i < bm->temp_num; i++) {
  721. if(i != 0) {
  722. strcat(msg, ", ");
  723. }
  724. sprintf(tmp, "Temp%d: %dC", i+1, info->temp[i]);
  725. strcat(msg, tmp);
  726. }
  727. sprintf(tmp, ", TempMAX: %dC", info->temp_max);
  728. strcat(msg, tmp);
  729. applog(LOG_INFO, "%s", msg);
  730. info->temp_history_index++;
  731. info->temp_sum += bitmain->temp;
  732. applog(LOG_DEBUG, "BitMain: temp_index: %d, temp_count: %d, temp_old: %d",
  733. info->temp_history_index, info->temp_history_count, info->temp_old);
  734. if (info->temp_history_index == info->temp_history_count) {
  735. info->temp_history_index = 0;
  736. info->temp_sum = 0;
  737. }
  738. }
  739. static void bitmain_set_fifo_space(struct cgpu_info * const dev, const int fifo_space)
  740. {
  741. struct thr_info * const master_thr = dev->thr[0];
  742. struct bitmain_info * const info = dev->device_data;
  743. if (unlikely(fifo_space > info->max_fifo_space))
  744. info->max_fifo_space = fifo_space;
  745. info->fifo_space = fifo_space;
  746. master_thr->queue_full = !fifo_space;
  747. }
  748. static void bitmain_parse_results(struct cgpu_info *bitmain, struct bitmain_info *info,
  749. struct thr_info *thr, uint8_t *buf, int *offset)
  750. {
  751. int i, j, n, m, r, errordiff, spare = BITMAIN_READ_SIZE;
  752. uint32_t checkbit = 0x00000000;
  753. bool found = false;
  754. struct work *work = NULL;
  755. struct bitmain_packet_head packethead;
  756. int asicnum = 0;
  757. int mod = 0,tmp = 0;
  758. for (i = 0; i <= spare; i++) {
  759. if(buf[i] == 0xa1) {
  760. struct bitmain_rxstatus_data rxstatusdata;
  761. applog(LOG_DEBUG, "bitmain_parse_results RxStatus Data");
  762. if(*offset < 4) {
  763. return;
  764. }
  765. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  766. packethead.length = htole16(packethead.length);
  767. if(packethead.length > 1130) {
  768. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus datalen=%d error", packethead.length+4);
  769. continue;
  770. }
  771. if(*offset < packethead.length + 4) {
  772. return;
  773. }
  774. if(bitmain_parse_rxstatus(buf+i, packethead.length+4, &rxstatusdata) != 0) {
  775. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus error len=%d", packethead.length+4);
  776. } else {
  777. mutex_lock(&info->qlock);
  778. info->chain_num = rxstatusdata.chain_num;
  779. bitmain_set_fifo_space(bitmain, rxstatusdata.fifo_space);
  780. info->hw_version[0] = rxstatusdata.hw_version[0];
  781. info->hw_version[1] = rxstatusdata.hw_version[1];
  782. info->hw_version[2] = rxstatusdata.hw_version[2];
  783. info->hw_version[3] = rxstatusdata.hw_version[3];
  784. info->nonce_error = rxstatusdata.nonce_error;
  785. errordiff = info->nonce_error-info->last_nonce_error;
  786. //sprintf(g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  787. applog(LOG_ERR, "bitmain_parse_results v=%d chain=%d fifo=%d hwv1=%d hwv2=%d hwv3=%d hwv4=%d nerr=%d-%d freq=%d chain info:",
  788. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  789. info->last_nonce_error, info->nonce_error, info->frequency);
  790. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  791. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  792. for(n = 0; n < rxstatusdata.chain_num; n++) {
  793. info->chain_asic_num[n] = rxstatusdata.chain_asic_num[n];
  794. memset(info->chain_asic_status_t[n], 0, 320);
  795. j = 0;
  796. mod = 0;
  797. if(info->chain_asic_num[n] <= 0) {
  798. asicnum = 0;
  799. } else {
  800. mod = info->chain_asic_num[n] % 32;
  801. if(mod == 0) {
  802. asicnum = info->chain_asic_num[n] / 32;
  803. } else {
  804. asicnum = info->chain_asic_num[n] / 32 + 1;
  805. }
  806. }
  807. if(asicnum > 0) {
  808. for(m = asicnum-1; m >= 0; m--) {
  809. tmp = mod ? (32-mod): 0;
  810. for(r = tmp;r < 32;r++){
  811. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  812. info->chain_asic_status_t[n][j] = ' ';
  813. j++;
  814. }
  815. checkbit = num2bit(r);
  816. if(rxstatusdata.chain_asic_exist[n*8+m] & checkbit) {
  817. if(rxstatusdata.chain_asic_status[n*8+m] & checkbit) {
  818. info->chain_asic_status_t[n][j] = 'o';
  819. } else {
  820. info->chain_asic_status_t[n][j] = 'x';
  821. }
  822. } else {
  823. info->chain_asic_status_t[n][j] = '-';
  824. }
  825. j++;
  826. }
  827. info->chain_asic_status_t[n][j] = ' ';
  828. j++;
  829. mod = 0;
  830. }
  831. }
  832. applog(LOG_DEBUG, "bitmain_parse_results chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  833. n, info->chain_asic_num[n],
  834. info->chain_asic_exist[n*8+0], info->chain_asic_exist[n*8+1], info->chain_asic_exist[n*8+2], info->chain_asic_exist[n*8+3], info->chain_asic_exist[n*8+4], info->chain_asic_exist[n*8+5], info->chain_asic_exist[n*8+6], info->chain_asic_exist[n*8+7],
  835. info->chain_asic_status[n*8+0], info->chain_asic_status[n*8+1], info->chain_asic_status[n*8+2], info->chain_asic_status[n*8+3], info->chain_asic_status[n*8+4], info->chain_asic_status[n*8+5], info->chain_asic_status[n*8+6], info->chain_asic_status[n*8+7]);
  836. applog(LOG_ERR, "bitmain_parse_results chain(%d) asic_num=%d asic_status=%s", n, info->chain_asic_num[n], info->chain_asic_status_t[n]);
  837. }
  838. mutex_unlock(&info->qlock);
  839. if(errordiff > 0) {
  840. for(j = 0; j < errordiff; j++) {
  841. bitmain_inc_nvw(info, thr);
  842. }
  843. mutex_lock(&info->qlock);
  844. info->last_nonce_error += errordiff;
  845. mutex_unlock(&info->qlock);
  846. }
  847. bitmain_update_temps(bitmain, info, &rxstatusdata);
  848. }
  849. found = true;
  850. spare = packethead.length + 4 + i;
  851. if(spare > *offset) {
  852. applog(LOG_ERR, "bitmain_parse_rxresults space(%d) > offset(%d)", spare, *offset);
  853. spare = *offset;
  854. }
  855. break;
  856. } else if(buf[i] == 0xa2) {
  857. struct bitmain_rxnonce_data rxnoncedata;
  858. int nonce_num = 0;
  859. applog(LOG_DEBUG, "bitmain_parse_results RxNonce Data");
  860. if(*offset < 4) {
  861. return;
  862. }
  863. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  864. packethead.length = htole16(packethead.length);
  865. if(packethead.length > 1038) {
  866. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce datalen=%d error", packethead.length+4);
  867. continue;
  868. }
  869. if(*offset < packethead.length + 4) {
  870. return;
  871. }
  872. if(bitmain_parse_rxnonce(buf+i, packethead.length+4, &rxnoncedata, &nonce_num) != 0) {
  873. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce error len=%d", packethead.length+4);
  874. } else {
  875. const float nonce_diff = 1 << rxnoncedata.diff;
  876. for(j = 0; j < nonce_num; j++) {
  877. const work_device_id_t work_id = rxnoncedata.nonces[j].work_id;
  878. HASH_FIND(hh, thr->work_list, &work_id, sizeof(work_id), work);
  879. if(work) {
  880. if(BITMAIN_TEST_PRINT_WORK) {
  881. applog(LOG_ERR, "bitmain_parse_results nonce find work(%d-%d)(%08x)", work->id, rxnoncedata.nonces[j].work_id, rxnoncedata.nonces[j].nonce);
  882. char ob_hex[(32 * 2) + 1];
  883. bin2hex(ob_hex, work->midstate, 32);
  884. applog(LOG_ERR, "work %d midstate: %s", work->id, ob_hex);
  885. bin2hex(ob_hex, &work->data[64], 12);
  886. applog(LOG_ERR, "work %d data2: %s", work->id, ob_hex);
  887. }
  888. {
  889. const uint32_t nonce = rxnoncedata.nonces[j].nonce;
  890. applog(LOG_DEBUG, "BitMain: submit nonce = %08lx", (unsigned long)nonce);
  891. work->nonce_diff = nonce_diff;
  892. if (submit_nonce(thr, work, nonce)) {
  893. mutex_lock(&info->qlock);
  894. hashes_done2(thr, 0x100000000 * work->nonce_diff, NULL);
  895. mutex_unlock(&info->qlock);
  896. } else {
  897. applog(LOG_ERR, "BitMain: bitmain_decode_nonce error work(%d)", rxnoncedata.nonces[j].work_id);
  898. }
  899. }
  900. } else {
  901. bitmain_inc_nvw(info, thr);
  902. applog(LOG_ERR, "BitMain: Nonce not find work(%d)", rxnoncedata.nonces[j].work_id);
  903. }
  904. }
  905. mutex_lock(&info->qlock);
  906. bitmain_set_fifo_space(bitmain, rxnoncedata.fifo_space);
  907. mutex_unlock(&info->qlock);
  908. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  909. #ifndef WIN32
  910. if(nonce_num < BITMAIN_MAX_NONCE_NUM)
  911. cgsleep_ms(5);
  912. #endif
  913. }
  914. found = true;
  915. spare = packethead.length + 4 + i;
  916. if(spare > *offset) {
  917. applog(LOG_ERR, "bitmain_parse_rxnonce space(%d) > offset(%d)", spare, *offset);
  918. spare = *offset;
  919. }
  920. break;
  921. } else {
  922. applog(LOG_ERR, "bitmain_parse_results data type error=%02x", buf[i]);
  923. }
  924. }
  925. if (!found) {
  926. spare = *offset - BITMAIN_READ_SIZE;
  927. /* We are buffering and haven't accumulated one more corrupt
  928. * work result. */
  929. if (spare < (int)BITMAIN_READ_SIZE)
  930. return;
  931. bitmain_inc_nvw(info, thr);
  932. }
  933. *offset -= spare;
  934. memmove(buf, buf + spare, *offset);
  935. }
  936. static void bitmain_running_reset(struct cgpu_info *bitmain, struct bitmain_info *info)
  937. {
  938. info->reset = false;
  939. }
  940. static void bitmain_prune_old_work(struct cgpu_info * const dev)
  941. {
  942. struct thr_info * const master_thr = dev->thr[0];
  943. struct bitmain_info * const info = dev->device_data;
  944. const size_t retain_work_items = info->max_fifo_space * 2;
  945. const size_t queued_work_items = HASH_COUNT(master_thr->work_list);
  946. if (queued_work_items > retain_work_items) {
  947. size_t remove_work_items = queued_work_items - retain_work_items;
  948. while (remove_work_items--) {
  949. // Deletes the first item insertion-order
  950. struct work * const work = master_thr->work_list;
  951. HASH_DEL(master_thr->work_list, work);
  952. free_work(work);
  953. }
  954. }
  955. }
  956. static void bitmain_poll(struct thr_info * const thr)
  957. {
  958. struct cgpu_info *bitmain = thr->cgpu;
  959. struct bitmain_info *info = bitmain->device_data;
  960. int offset = info->readbuf_offset, ret = 0;
  961. const int rsize = BITMAIN_FTDI_READSIZE;
  962. uint8_t * const readbuf = info->readbuf;
  963. {
  964. unsigned char buf[rsize];
  965. if (unlikely(info->reset)) {
  966. bitmain_running_reset(bitmain, info);
  967. /* Discard anything in the buffer */
  968. offset = 0;
  969. }
  970. //cgsleep_prepare_r(&ts_start);
  971. //applog(LOG_DEBUG, "======start bitmain_get_results bitmain_read");
  972. ret = bitmain_read(bitmain, buf, rsize, BITMAIN_READ_TIMEOUT);
  973. //applog(LOG_DEBUG, "======stop bitmain_get_results bitmain_read=%d", ret);
  974. if ((ret < 1) || (ret == 18)) {
  975. ++info->errorcount2;
  976. #ifdef WIN32
  977. if(info->errorcount2 > 200) {
  978. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  979. cgsleep_ms(20);
  980. info->errorcount2 = 0;
  981. }
  982. #else
  983. if(info->errorcount2 > 3) {
  984. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  985. cgsleep_ms(20);
  986. info->errorcount2 = 0;
  987. }
  988. #endif
  989. if(ret < 1)
  990. return;
  991. }
  992. if (opt_debug) {
  993. char hex[(ret * 2) + 1];
  994. bin2hex(hex, buf, ret);
  995. applog(LOG_DEBUG, "BitMain: get: %s", hex);
  996. }
  997. memcpy(readbuf+offset, buf, ret);
  998. offset += ret;
  999. //applog(LOG_DEBUG, "+++++++bitmain_get_results offset=%d", offset);
  1000. if (offset >= (int)BITMAIN_READ_SIZE) {
  1001. //applog(LOG_DEBUG, "======start bitmain_get_results ");
  1002. bitmain_parse_results(bitmain, info, thr, readbuf, &offset);
  1003. //applog(LOG_DEBUG, "======stop bitmain_get_results ");
  1004. }
  1005. if (unlikely(offset + rsize >= BITMAIN_READBUF_SIZE)) {
  1006. /* This should never happen */
  1007. applog(LOG_DEBUG, "BitMain readbuf overflow, resetting buffer");
  1008. offset = 0;
  1009. }
  1010. /* As the usb read returns after just 1ms, sleep long enough
  1011. * to leave the interface idle for writes to occur, but do not
  1012. * sleep if we have been receiving data as more may be coming. */
  1013. //if (offset == 0) {
  1014. // cgsleep_ms_r(&ts_start, BITMAIN_READ_TIMEOUT);
  1015. //}
  1016. }
  1017. info->readbuf_offset = offset;
  1018. bitmain_prune_old_work(bitmain);
  1019. timer_set_delay_from_now(&thr->tv_poll, bitmain_poll_interval_us);
  1020. }
  1021. static void bitmain_init(struct cgpu_info *bitmain)
  1022. {
  1023. applog(LOG_INFO, "BitMain: Opened on %s", bitmain->device_path);
  1024. }
  1025. static bool bitmain_prepare(struct thr_info *thr)
  1026. {
  1027. struct cgpu_info *bitmain = thr->cgpu;
  1028. struct bitmain_info *info = bitmain->device_data;
  1029. mutex_init(&info->qlock);
  1030. // To initialise queue_full
  1031. bitmain_set_fifo_space(bitmain, info->fifo_space);
  1032. bitmain_init(bitmain);
  1033. timer_set_now(&thr->tv_poll);
  1034. return true;
  1035. }
  1036. static int bitmain_initialize(struct cgpu_info *bitmain)
  1037. {
  1038. uint8_t data[BITMAIN_READBUF_SIZE];
  1039. struct bitmain_info *info = NULL;
  1040. int ret = 0;
  1041. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1042. int readlen = 0;
  1043. int sendlen = 0;
  1044. int trycount = 3;
  1045. struct timespec p;
  1046. struct bitmain_rxstatus_data rxstatusdata;
  1047. int i = 0, j = 0, m = 0, r = 0, statusok = 0;
  1048. uint32_t checkbit = 0x00000000;
  1049. int hwerror_eft = 0;
  1050. int beeper_ctrl = 1;
  1051. int tempover_ctrl = 1;
  1052. int home_mode = 0;
  1053. struct bitmain_packet_head packethead;
  1054. int asicnum = 0;
  1055. int mod = 0,tmp = 0;
  1056. /* Send reset, then check for result */
  1057. if(!bitmain) {
  1058. applog(LOG_WARNING, "bitmain_initialize cgpu_info is null");
  1059. return -1;
  1060. }
  1061. info = bitmain->device_data;
  1062. /* clear read buf */
  1063. ret = bitmain_read(bitmain, data, BITMAIN_READBUF_SIZE,
  1064. BITMAIN_RESET_TIMEOUT);
  1065. if(ret > 0) {
  1066. if (opt_debug) {
  1067. char hex[(ret * 2) + 1];
  1068. bin2hex(hex, data, ret);
  1069. applog(LOG_DEBUG, "BTM%d Clear Read(%d): %s", bitmain->device_id, ret, hex);
  1070. }
  1071. }
  1072. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *)sendbuf, 0, 1, 0, 0);
  1073. if(sendlen <= 0) {
  1074. applog(LOG_ERR, "bitmain_initialize bitmain_set_rxstatus error(%d)", sendlen);
  1075. return -1;
  1076. }
  1077. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1078. if (unlikely(ret == BTM_SEND_ERROR)) {
  1079. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1080. return -1;
  1081. }
  1082. while(trycount >= 0) {
  1083. ret = bitmain_read(bitmain, data+readlen, BITMAIN_READBUF_SIZE, BITMAIN_RESET_TIMEOUT);
  1084. if(ret > 0) {
  1085. readlen += ret;
  1086. if(readlen > BITMAIN_READ_SIZE) {
  1087. for(i = 0; i < readlen; i++) {
  1088. if(data[i] == 0xa1) {
  1089. if (opt_debug) {
  1090. char hex[(readlen * 2) + 1];
  1091. bin2hex(hex, data, readlen);
  1092. applog(LOG_DEBUG, "%s%d initset: get: %s", bitmain->drv->name, bitmain->device_id, hex);
  1093. }
  1094. memcpy(&packethead, data+i, sizeof(struct bitmain_packet_head));
  1095. packethead.length = htole16(packethead.length);
  1096. if(packethead.length > 1130) {
  1097. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d error", packethead.length+4);
  1098. continue;
  1099. }
  1100. if(readlen-i < packethead.length+4) {
  1101. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d<%d low", readlen-i, packethead.length+4);
  1102. continue;
  1103. }
  1104. if (bitmain_parse_rxstatus(data+i, packethead.length+4, &rxstatusdata) != 0) {
  1105. applog(LOG_ERR, "bitmain_initialize bitmain_parse_rxstatus error");
  1106. continue;
  1107. }
  1108. info->chain_num = rxstatusdata.chain_num;
  1109. // NOTE: This is before thr_info is allocated, so we cannot use bitmain_set_fifo_space (bitmain_prepare will re-set it for us)
  1110. info->fifo_space = rxstatusdata.fifo_space;
  1111. info->hw_version[0] = rxstatusdata.hw_version[0];
  1112. info->hw_version[1] = rxstatusdata.hw_version[1];
  1113. info->hw_version[2] = rxstatusdata.hw_version[2];
  1114. info->hw_version[3] = rxstatusdata.hw_version[3];
  1115. info->nonce_error = 0;
  1116. info->last_nonce_error = 0;
  1117. sprintf(info->g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  1118. applog(LOG_ERR, "bitmain_initialize rxstatus v(%d) chain(%d) fifo(%d) hwv1(%d) hwv2(%d) hwv3(%d) hwv4(%d) nerr(%d) freq=%d",
  1119. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  1120. rxstatusdata.nonce_error, info->frequency);
  1121. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  1122. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  1123. for(i = 0; i < rxstatusdata.chain_num; i++) {
  1124. info->chain_asic_num[i] = rxstatusdata.chain_asic_num[i];
  1125. memset(info->chain_asic_status_t[i], 0, 320);
  1126. j = 0;
  1127. mod = 0;
  1128. if(info->chain_asic_num[i] <= 0) {
  1129. asicnum = 0;
  1130. } else {
  1131. mod = info->chain_asic_num[i] % 32;
  1132. if(mod == 0) {
  1133. asicnum = info->chain_asic_num[i] / 32;
  1134. } else {
  1135. asicnum = info->chain_asic_num[i] / 32 + 1;
  1136. }
  1137. }
  1138. if(asicnum > 0) {
  1139. for(m = asicnum-1; m >= 0; m--) {
  1140. tmp = mod ? (32-mod):0;
  1141. for(r = tmp;r < 32;r++){
  1142. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  1143. info->chain_asic_status_t[i][j] = ' ';
  1144. j++;
  1145. }
  1146. checkbit = num2bit(r);
  1147. if(rxstatusdata.chain_asic_exist[i*8+m] & checkbit) {
  1148. if(rxstatusdata.chain_asic_status[i*8+m] & checkbit) {
  1149. info->chain_asic_status_t[i][j] = 'o';
  1150. } else {
  1151. info->chain_asic_status_t[i][j] = 'x';
  1152. }
  1153. } else {
  1154. info->chain_asic_status_t[i][j] = '-';
  1155. }
  1156. j++;
  1157. }
  1158. info->chain_asic_status_t[i][j] = ' ';
  1159. j++;
  1160. mod = 0;
  1161. }
  1162. }
  1163. applog(LOG_DEBUG, "bitmain_initialize chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  1164. i, info->chain_asic_num[i],
  1165. info->chain_asic_exist[i*8+0], info->chain_asic_exist[i*8+1], info->chain_asic_exist[i*8+2], info->chain_asic_exist[i*8+3], info->chain_asic_exist[i*8+4], info->chain_asic_exist[i*8+5], info->chain_asic_exist[i*8+6], info->chain_asic_exist[i*8+7],
  1166. info->chain_asic_status[i*8+0], info->chain_asic_status[i*8+1], info->chain_asic_status[i*8+2], info->chain_asic_status[i*8+3], info->chain_asic_status[i*8+4], info->chain_asic_status[i*8+5], info->chain_asic_status[i*8+6], info->chain_asic_status[i*8+7]);
  1167. applog(LOG_ERR, "bitmain_initialize chain(%d) asic_num=%d asic_status=%s", i, info->chain_asic_num[i], info->chain_asic_status_t[i]);
  1168. }
  1169. bitmain_update_temps(bitmain, info, &rxstatusdata);
  1170. statusok = 1;
  1171. break;
  1172. }
  1173. }
  1174. if(statusok) {
  1175. break;
  1176. }
  1177. }
  1178. }
  1179. trycount--;
  1180. p.tv_sec = 0;
  1181. p.tv_nsec = BITMAIN_RESET_PITCH;
  1182. nanosleep(&p, NULL);
  1183. }
  1184. p.tv_sec = 0;
  1185. p.tv_nsec = BITMAIN_RESET_PITCH;
  1186. nanosleep(&p, NULL);
  1187. if(statusok) {
  1188. applog(LOG_ERR, "bitmain_initialize start send txconfig");
  1189. if(opt_bitmain_hwerror)
  1190. hwerror_eft = 1;
  1191. else
  1192. hwerror_eft = 0;
  1193. if(opt_bitmain_nobeeper)
  1194. beeper_ctrl = 0;
  1195. else
  1196. beeper_ctrl = 1;
  1197. if(opt_bitmain_notempoverctrl)
  1198. tempover_ctrl = 0;
  1199. else
  1200. tempover_ctrl = 1;
  1201. if(opt_bitmain_homemode)
  1202. home_mode= 1;
  1203. else
  1204. home_mode= 0;
  1205. sendlen = bitmain_set_txconfig((struct bitmain_txconfig_token *)sendbuf, 1, 1, 1, 1, 1, 0, 1, hwerror_eft, beeper_ctrl, tempover_ctrl,home_mode,
  1206. info->chain_num, info->asic_num, BITMAIN_DEFAULT_FAN_MAX_PWM, info->timeout,
  1207. info->frequency, info->voltage, 0, 0, 0x04, info->reg_data);
  1208. if(sendlen <= 0) {
  1209. applog(LOG_ERR, "bitmain_initialize bitmain_set_txconfig error(%d)", sendlen);
  1210. return -1;
  1211. }
  1212. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1213. if (unlikely(ret == BTM_SEND_ERROR)) {
  1214. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1215. return -1;
  1216. }
  1217. applog(LOG_WARNING, "BMM%d: InitSet succeeded", bitmain->device_id);
  1218. } else {
  1219. applog(LOG_WARNING, "BMS%d: InitSet error", bitmain->device_id);
  1220. return -1;
  1221. }
  1222. return 0;
  1223. }
  1224. static bool bitmain_detect_one(const char * devpath)
  1225. {
  1226. struct bitmain_info *info;
  1227. struct cgpu_info *bitmain;
  1228. int ret;
  1229. bitmain = btm_alloc_cgpu(&bitmain_drv, BITMAIN_MINER_THREADS);
  1230. info = bitmain->device_data;
  1231. drv_set_defaults(&bitmain_drv, bitmain_set_device_funcs_init, info, devpath, NULL, 1);
  1232. if (!info->packet_max_work)
  1233. return_via_applog(shin, , LOG_ERR, "%s: Device not configured (did you forget --set bitmain:model=S5 ?)", bitmain_drv.dname);
  1234. if (!btm_init(bitmain, devpath))
  1235. goto shin;
  1236. applog(LOG_ERR, "bitmain_detect_one btm init ok");
  1237. info->fan_pwm = BITMAIN_DEFAULT_FAN_MIN_PWM;
  1238. info->temp_max = 0;
  1239. /* This is for check the temp/fan every 3~4s */
  1240. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  1241. if (info->temp_history_count <= 0)
  1242. info->temp_history_count = 1;
  1243. info->temp_history_index = 0;
  1244. info->temp_sum = 0;
  1245. info->temp_old = 0;
  1246. if (!add_cgpu(bitmain))
  1247. goto unshin;
  1248. ret = bitmain_initialize(bitmain);
  1249. applog(LOG_ERR, "bitmain_detect_one stop bitmain_initialize %d", ret);
  1250. if (ret)
  1251. goto unshin;
  1252. info->errorcount = 0;
  1253. applog(LOG_ERR, "BitMain Detected: %s "
  1254. "(chain_num=%d asic_num=%d timeout=%d freq=%d-%s volt=%02x%02x-%s)",
  1255. bitmain->device_path, info->chain_num, info->asic_num, info->timeout,
  1256. info->frequency, info->frequency_t, info->voltage[0], info->voltage[1], info->voltage_t);
  1257. return true;
  1258. unshin:
  1259. btm_uninit(bitmain);
  1260. shin:
  1261. free(bitmain->device_data);
  1262. bitmain->device_data = NULL;
  1263. free(bitmain);
  1264. return false;
  1265. }
  1266. static int bitmain_detect_auto(void)
  1267. {
  1268. const char * const auto_bitmain_dev = "/dev/bitmain-asic";
  1269. applog(LOG_DEBUG, "BTM detect dev: %s", auto_bitmain_dev);
  1270. return bitmain_detect_one(auto_bitmain_dev) ? 1 : 0;
  1271. }
  1272. static void bitmain_detect()
  1273. {
  1274. generic_detect(&bitmain_drv, bitmain_detect_one, bitmain_detect_auto, GDF_REQUIRE_DNAME | GDF_DEFAULT_NOAUTO);
  1275. }
  1276. static void do_bitmain_close(struct thr_info *thr)
  1277. {
  1278. struct cgpu_info *bitmain = thr->cgpu;
  1279. struct bitmain_info *info = bitmain->device_data;
  1280. bitmain_running_reset(bitmain, info);
  1281. info->no_matching_work = 0;
  1282. }
  1283. static uint8_t diff_to_bitmain(float diff)
  1284. {
  1285. uint8_t res = 0;
  1286. if (diff > UINT64_MAX)
  1287. diff = UINT64_MAX;
  1288. for (uint64_t tmp = diff; tmp >>= 1; ) {
  1289. if (++res == UINT8_MAX)
  1290. break;
  1291. }
  1292. return res;
  1293. }
  1294. static bool bitmain_queue_append(struct thr_info * const thr, struct work * const work)
  1295. {
  1296. struct cgpu_info * const proc = thr->cgpu;
  1297. struct cgpu_info * const dev = proc->device;
  1298. struct thr_info * const master_thr = dev->thr[0];
  1299. struct bitmain_info * const info = dev->device_data;
  1300. const struct pool * const pool = work->pool;
  1301. const struct mining_goal_info * const goal = pool->goal;
  1302. applog(LOG_DEBUG, "%s: %s with fifo_space=%d (max=%d) work_restart=%d", dev->dev_repr, __func__, info->fifo_space, info->max_fifo_space, (int)info->work_restart);
  1303. if (info->work_restart) {
  1304. info->work_restart = false;
  1305. info->ready_to_queue = 0;
  1306. bitmain_set_fifo_space(dev, info->max_fifo_space);
  1307. info->queuebuf[4] = 1; // clear work queues
  1308. }
  1309. if (!info->fifo_space) {
  1310. thr->queue_full = true;
  1311. return false;
  1312. }
  1313. uint8_t * const wbuf = &info->queuebuf[BITMAIN_TASK_HEADER_SIZE + (BITMAIN_WORK_SIZE * info->ready_to_queue)];
  1314. const int work_nonce_bmdiff = diff_to_bitmain(work->nonce_diff);
  1315. if (work_nonce_bmdiff < info->diff)
  1316. info->diff = work_nonce_bmdiff;
  1317. if (goal->current_diff < info->lowest_goal_diff)
  1318. info->lowest_goal_diff = goal->current_diff;
  1319. work->device_id = info->next_work_id++;
  1320. pk_u32le(wbuf, 0, work->device_id);
  1321. memcpy(&wbuf[4], work->midstate, 0x20);
  1322. memcpy(&wbuf[0x24], &work->data[0x40], 0xc);
  1323. HASH_ADD(hh, master_thr->work_list, device_id, sizeof(work->device_id), work);
  1324. ++info->ready_to_queue;
  1325. if (!(info->ready_to_queue >= info->packet_max_work || info->fifo_space == info->ready_to_queue || info->fifo_space == info->max_fifo_space)) {
  1326. applog(LOG_DEBUG, "%s: %s now has ready_to_queue=%d; deferring send", dev->dev_repr, __func__, info->ready_to_queue);
  1327. return true;
  1328. }
  1329. applog(LOG_DEBUG, "%s: %s now has ready_to_queue=%d; sending to device", dev->dev_repr, __func__, info->ready_to_queue);
  1330. uint8_t * const buf = info->queuebuf;
  1331. const size_t buflen = BITMAIN_TASK_HEADER_SIZE + (info->ready_to_queue * BITMAIN_WORK_SIZE) + BITMAIN_TASK_FOOTER_SIZE;
  1332. buf[0] = BITMAIN_TOKEN_TYPE_TXTASK;
  1333. buf[1] = 0; // packet version
  1334. pk_u16le(buf, 2, buflen - 4); // length of data after this field (including CRC)
  1335. // buf[4] is set to 1 to clear work queues, when the first work item is added, and reset to 0 after we send
  1336. buf[5] = info->diff;
  1337. pk_u16le(buf, 6, diff_to_bitmain(info->lowest_goal_diff));
  1338. pk_u16le(buf, buflen - 2, CRC16(buf, buflen - 2));
  1339. int sendret = bitmain_send_data(buf, buflen, proc);
  1340. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1341. applog(LOG_ERR, "%s: Comms error(buffer)", dev->dev_repr);
  1342. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1343. info->reset = true;
  1344. info->errorcount++;
  1345. if (info->errorcount > 1000) {
  1346. info->errorcount = 0;
  1347. applog(LOG_ERR, "%s: Device disappeared, shutting down thread", dev->dev_repr);
  1348. dev->shutdown = true;
  1349. }
  1350. // The work is in the queuebuf already, so we're okay-ish for that...
  1351. return true;
  1352. } else {
  1353. applog(LOG_DEBUG, "bitmain_send_data send ret=%d", sendret);
  1354. info->errorcount = 0;
  1355. }
  1356. buf[4] = 0;
  1357. info->fifo_space -= info->ready_to_queue;
  1358. info->ready_to_queue = 0;
  1359. if (info->max_fifo_space - info->fifo_space > bitmain_work_poll_prio) {
  1360. bitmain_poll(master_thr);
  1361. }
  1362. return true;
  1363. }
  1364. static void bitmain_queue_flush(struct thr_info * const thr)
  1365. {
  1366. struct cgpu_info * const proc = thr->cgpu;
  1367. struct cgpu_info * const dev = proc->device;
  1368. struct bitmain_info * const info = dev->device_data;
  1369. // Can't use thr->work_restart as that merely triggers this function in minerloop_queue
  1370. info->work_restart = true;
  1371. thr->queue_full = false;
  1372. }
  1373. static struct api_data *bitmain_api_stats(struct cgpu_info *cgpu)
  1374. {
  1375. struct api_data *root = NULL;
  1376. struct bitmain_info *info = cgpu->device_data;
  1377. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1378. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1379. root = api_add_int(root, "miner_count", &(info->chain_num), false);
  1380. root = api_add_int(root, "asic_count", &(info->asic_num), false);
  1381. root = api_add_int(root, "timeout", &(info->timeout), false);
  1382. root = api_add_string(root, "frequency", info->frequency_t, false);
  1383. root = api_add_string(root, "voltage", info->voltage_t, false);
  1384. root = api_add_int(root, "hwv1", &(info->hw_version[0]), false);
  1385. root = api_add_int(root, "hwv2", &(info->hw_version[1]), false);
  1386. root = api_add_int(root, "hwv3", &(info->hw_version[2]), false);
  1387. root = api_add_int(root, "hwv4", &(info->hw_version[3]), false);
  1388. root = api_add_int(root, "fan_num", &(info->fan_num), false);
  1389. root = api_add_int(root, "fan1", &(info->fan[0]), false);
  1390. root = api_add_int(root, "fan2", &(info->fan[1]), false);
  1391. root = api_add_int(root, "fan3", &(info->fan[2]), false);
  1392. root = api_add_int(root, "fan4", &(info->fan[3]), false);
  1393. root = api_add_int(root, "fan5", &(info->fan[4]), false);
  1394. root = api_add_int(root, "fan6", &(info->fan[5]), false);
  1395. root = api_add_int(root, "fan7", &(info->fan[6]), false);
  1396. root = api_add_int(root, "fan8", &(info->fan[7]), false);
  1397. root = api_add_int(root, "fan9", &(info->fan[8]), false);
  1398. root = api_add_int(root, "fan10", &(info->fan[9]), false);
  1399. root = api_add_int(root, "fan11", &(info->fan[10]), false);
  1400. root = api_add_int(root, "fan12", &(info->fan[11]), false);
  1401. root = api_add_int(root, "fan13", &(info->fan[12]), false);
  1402. root = api_add_int(root, "fan14", &(info->fan[13]), false);
  1403. root = api_add_int(root, "fan15", &(info->fan[14]), false);
  1404. root = api_add_int(root, "fan16", &(info->fan[15]), false);
  1405. root = api_add_int(root, "temp_num", &(info->temp_num), false);
  1406. root = api_add_int(root, "temp1", &(info->temp[0]), false);
  1407. root = api_add_int(root, "temp2", &(info->temp[1]), false);
  1408. root = api_add_int(root, "temp3", &(info->temp[2]), false);
  1409. root = api_add_int(root, "temp4", &(info->temp[3]), false);
  1410. root = api_add_int(root, "temp5", &(info->temp[4]), false);
  1411. root = api_add_int(root, "temp6", &(info->temp[5]), false);
  1412. root = api_add_int(root, "temp7", &(info->temp[6]), false);
  1413. root = api_add_int(root, "temp8", &(info->temp[7]), false);
  1414. root = api_add_int(root, "temp9", &(info->temp[8]), false);
  1415. root = api_add_int(root, "temp10", &(info->temp[9]), false);
  1416. root = api_add_int(root, "temp11", &(info->temp[10]), false);
  1417. root = api_add_int(root, "temp12", &(info->temp[11]), false);
  1418. root = api_add_int(root, "temp13", &(info->temp[12]), false);
  1419. root = api_add_int(root, "temp14", &(info->temp[13]), false);
  1420. root = api_add_int(root, "temp15", &(info->temp[14]), false);
  1421. root = api_add_int(root, "temp16", &(info->temp[15]), false);
  1422. root = api_add_int(root, "temp_avg", &(info->temp_avg), false);
  1423. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1424. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1425. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1426. /*
  1427. for (int i = 0; i < info->chain_num; ++i) {
  1428. char mcw[24];
  1429. sprintf(mcw, "match_work_count%d", i + 1);
  1430. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1431. }*/
  1432. root = api_add_int(root, "chain_acn1", &(info->chain_asic_num[0]), false);
  1433. root = api_add_int(root, "chain_acn2", &(info->chain_asic_num[1]), false);
  1434. root = api_add_int(root, "chain_acn3", &(info->chain_asic_num[2]), false);
  1435. root = api_add_int(root, "chain_acn4", &(info->chain_asic_num[3]), false);
  1436. root = api_add_int(root, "chain_acn5", &(info->chain_asic_num[4]), false);
  1437. root = api_add_int(root, "chain_acn6", &(info->chain_asic_num[5]), false);
  1438. root = api_add_int(root, "chain_acn7", &(info->chain_asic_num[6]), false);
  1439. root = api_add_int(root, "chain_acn8", &(info->chain_asic_num[7]), false);
  1440. root = api_add_int(root, "chain_acn9", &(info->chain_asic_num[8]), false);
  1441. root = api_add_int(root, "chain_acn10", &(info->chain_asic_num[9]), false);
  1442. root = api_add_int(root, "chain_acn11", &(info->chain_asic_num[10]), false);
  1443. root = api_add_int(root, "chain_acn12", &(info->chain_asic_num[11]), false);
  1444. root = api_add_int(root, "chain_acn13", &(info->chain_asic_num[12]), false);
  1445. root = api_add_int(root, "chain_acn14", &(info->chain_asic_num[13]), false);
  1446. root = api_add_int(root, "chain_acn15", &(info->chain_asic_num[14]), false);
  1447. root = api_add_int(root, "chain_acn16", &(info->chain_asic_num[15]), false);
  1448. //applog(LOG_ERR, "chain asic status:%s", info->chain_asic_status_t[0]);
  1449. root = api_add_string(root, "chain_acs1", info->chain_asic_status_t[0], false);
  1450. root = api_add_string(root, "chain_acs2", info->chain_asic_status_t[1], false);
  1451. root = api_add_string(root, "chain_acs3", info->chain_asic_status_t[2], false);
  1452. root = api_add_string(root, "chain_acs4", info->chain_asic_status_t[3], false);
  1453. root = api_add_string(root, "chain_acs5", info->chain_asic_status_t[4], false);
  1454. root = api_add_string(root, "chain_acs6", info->chain_asic_status_t[5], false);
  1455. root = api_add_string(root, "chain_acs7", info->chain_asic_status_t[6], false);
  1456. root = api_add_string(root, "chain_acs8", info->chain_asic_status_t[7], false);
  1457. root = api_add_string(root, "chain_acs9", info->chain_asic_status_t[8], false);
  1458. root = api_add_string(root, "chain_acs10", info->chain_asic_status_t[9], false);
  1459. root = api_add_string(root, "chain_acs11", info->chain_asic_status_t[10], false);
  1460. root = api_add_string(root, "chain_acs12", info->chain_asic_status_t[11], false);
  1461. root = api_add_string(root, "chain_acs13", info->chain_asic_status_t[12], false);
  1462. root = api_add_string(root, "chain_acs14", info->chain_asic_status_t[13], false);
  1463. root = api_add_string(root, "chain_acs15", info->chain_asic_status_t[14], false);
  1464. root = api_add_string(root, "chain_acs16", info->chain_asic_status_t[15], false);
  1465. //root = api_add_int(root, "chain_acs1", &(info->chain_asic_status[0]), false);
  1466. //root = api_add_int(root, "chain_acs2", &(info->chain_asic_status[1]), false);
  1467. //root = api_add_int(root, "chain_acs3", &(info->chain_asic_status[2]), false);
  1468. //root = api_add_int(root, "chain_acs4", &(info->chain_asic_status[3]), false);
  1469. return root;
  1470. }
  1471. static void bitmain_shutdown(struct thr_info *thr)
  1472. {
  1473. do_bitmain_close(thr);
  1474. }
  1475. static
  1476. const char *bitmain_set_layout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1477. {
  1478. struct bitmain_info *info = proc->device_data;
  1479. char *endptr, *next_field;
  1480. const long int n_chains = strtol(newvalue, &endptr, 0);
  1481. if (endptr == newvalue || n_chains < 1)
  1482. return "Missing chain count";
  1483. long int n_asics = 0;
  1484. if (endptr[0] == ':' || endptr[1] == ',')
  1485. {
  1486. next_field = &endptr[1];
  1487. n_asics = strtol(next_field, &endptr, 0);
  1488. }
  1489. if (n_asics < 1)
  1490. return "Missing ASIC count";
  1491. if (n_asics > BITMAIN_DEFAULT_ASIC_NUM)
  1492. return "ASIC count too high";
  1493. info->chain_num = n_chains;
  1494. info->asic_num = n_asics;
  1495. return NULL;
  1496. }
  1497. static
  1498. const char *bitmain_set_timeout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1499. {
  1500. struct bitmain_info *info = proc->device_data;
  1501. const int timeout = atoi(newvalue);
  1502. if (timeout < 0 || timeout > 0xff)
  1503. return "Invalid timeout setting";
  1504. info->timeout = timeout;
  1505. return NULL;
  1506. }
  1507. static
  1508. const char *bitmain_set_clock(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1509. {
  1510. struct bitmain_info *info = proc->device_data;
  1511. const int freq = atoi(newvalue);
  1512. if (freq < BITMAIN_MIN_FREQUENCY || freq > BITMAIN_MAX_FREQUENCY)
  1513. return "Invalid clock frequency";
  1514. info->frequency = freq;
  1515. sprintf(info->frequency_t, "%d", freq);
  1516. return NULL;
  1517. }
  1518. static
  1519. const char *bitmain_set_reg_data(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1520. {
  1521. struct bitmain_info *info = proc->device_data;
  1522. uint8_t reg_data[4] = {0};
  1523. if (newvalue[0] == 'x')
  1524. ++newvalue;
  1525. size_t nvlen = strlen(newvalue);
  1526. if (nvlen > (sizeof(reg_data) * 2) || !nvlen || nvlen % 2)
  1527. return "reg_data must be a hex string of 2-8 digits (1-4 bytes)";
  1528. if (!hex2bin(reg_data, newvalue, nvlen / 2))
  1529. return "Invalid reg data hex";
  1530. memcpy(info->reg_data, reg_data, sizeof(reg_data));
  1531. return NULL;
  1532. }
  1533. static
  1534. const char *bitmain_set_voltage(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1535. {
  1536. struct bitmain_info *info = proc->device_data;
  1537. uint8_t voltage_data[2] = {0};
  1538. if (newvalue[0] == 'x')
  1539. ++newvalue;
  1540. else
  1541. voltage_usage:
  1542. return "voltage must be 'x' followed by a hex string of 1-4 digits (1-2 bytes)";
  1543. size_t nvlen = strlen(newvalue);
  1544. if (nvlen > (sizeof(voltage_data) * 2) || !nvlen || nvlen % 2)
  1545. goto voltage_usage;
  1546. if (!hex2bin(voltage_data, newvalue, nvlen / 2))
  1547. return "Invalid voltage data hex";
  1548. memcpy(info->voltage, voltage_data, sizeof(voltage_data));
  1549. bin2hex(info->voltage_t, voltage_data, 2);
  1550. info->voltage_t[5] = 0;
  1551. info->voltage_t[4] = info->voltage_t[3];
  1552. info->voltage_t[3] = info->voltage_t[2];
  1553. info->voltage_t[2] = info->voltage_t[1];
  1554. info->voltage_t[1] = '.';
  1555. return NULL;
  1556. }
  1557. static bool bitmain_set_packet_max_work(struct cgpu_info * const dev, const unsigned i)
  1558. {
  1559. struct bitmain_info * const info = dev->device_data;
  1560. uint8_t * const new_queuebuf = realloc(info->queuebuf, BITMAIN_TASK_HEADER_SIZE + (i * BITMAIN_WORK_SIZE) + BITMAIN_TASK_FOOTER_SIZE);
  1561. if (!new_queuebuf)
  1562. return false;
  1563. info->packet_max_work = i;
  1564. info->queuebuf = new_queuebuf;
  1565. return true;
  1566. }
  1567. static const char *bitmain_set_packet_max_work_opt(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1568. {
  1569. const int i = atoi(newvalue);
  1570. if (i < 1)
  1571. return "Invalid setting";
  1572. if (!bitmain_set_packet_max_work(proc->device, i))
  1573. return "realloc failure";
  1574. return NULL;
  1575. }
  1576. static const char *bitmain_set_model(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1577. {
  1578. struct cgpu_info * const dev = proc->device;
  1579. if (toupper(newvalue[0]) != 'S') {
  1580. unknown_model:
  1581. return "Unknown model";
  1582. }
  1583. char *endptr;
  1584. long Sn = strtol(&newvalue[1], &endptr, 10);
  1585. if (Sn < 1 || Sn > 5)
  1586. goto unknown_model;
  1587. if (Sn == 5 && endptr[0] == '+')
  1588. ++endptr;
  1589. if (endptr[0] && !isspace(endptr[0]))
  1590. goto unknown_model;
  1591. switch (Sn) {
  1592. case 1:
  1593. bitmain_set_packet_max_work(dev, 8);
  1594. break;
  1595. case 2:
  1596. bitmain_set_packet_max_work(dev, 0x40);
  1597. break;
  1598. case 3:
  1599. bitmain_set_packet_max_work(dev, 8);
  1600. break;
  1601. case 4:
  1602. case 5:
  1603. bitmain_set_packet_max_work(dev, 0x40);
  1604. break;
  1605. }
  1606. return NULL;
  1607. }
  1608. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[] = {
  1609. {"model", bitmain_set_model, "model of unit (S1-S5)"},
  1610. {"layout", bitmain_set_layout, "number of chains ':' number of ASICs per chain (eg: 32:8)"},
  1611. {"timeout", bitmain_set_timeout, "timeout"},
  1612. {"clock", bitmain_set_clock, "clock frequency"},
  1613. {"reg_data", bitmain_set_reg_data, "reg_data (eg: x0d82)"},
  1614. {"voltage", bitmain_set_voltage, "voltage (must be specified as 'x' and hex data; eg: x0725)"},
  1615. {"packet_max_work", bitmain_set_packet_max_work_opt, NULL},
  1616. {NULL},
  1617. };
  1618. struct device_drv bitmain_drv = {
  1619. .dname = "bitmain",
  1620. .name = "BTM",
  1621. .drv_detect = bitmain_detect,
  1622. .thread_prepare = bitmain_prepare,
  1623. .minerloop = minerloop_queue,
  1624. .queue_append = bitmain_queue_append,
  1625. .queue_flush = bitmain_queue_flush,
  1626. .poll = bitmain_poll,
  1627. .get_api_stats = bitmain_api_stats,
  1628. .reinit_device = bitmain_init,
  1629. .thread_shutdown = bitmain_shutdown,
  1630. };