driver-avalon.c 22 KB

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  1. /*
  2. * Copyright 2013 Xiangfu
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int option_offset = -1;
  34. struct avalon_info **avalon_info;
  35. struct device_api avalon_api;
  36. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  37. uint8_t reset, uint8_t ff, uint8_t fan,
  38. uint8_t timeout_p, uint8_t asic_num_p,
  39. uint8_t miner_num_p, uint8_t nonce_elf_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (unlikely(!at))
  48. return -1;
  49. if (unlikely(!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0)))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (likely(thr)) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (unlikely(reset)) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (unlikely(first && !at->reset)) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = nonce_elf_p;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at,
  89. struct thr_info *thr)
  90. {
  91. size_t ret;
  92. int full;
  93. struct timespec p;
  94. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  95. size_t nr_len;
  96. struct cgpu_info *avalon;
  97. struct avalon_info *info;
  98. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  99. uint32_t nonce_range;
  100. int i;
  101. if (at->nonce_elf)
  102. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  103. else
  104. nr_len = AVALON_WRITE_SIZE;
  105. memcpy(buf, at, AVALON_WRITE_SIZE);
  106. if (at->nonce_elf) {
  107. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  108. for (i = 0; i < at->asic_num; i++) {
  109. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  110. (i * nonce_range & 0xff000000) >> 24;
  111. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  112. (i * nonce_range & 0x00ff0000) >> 16;
  113. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  114. (i * nonce_range & 0x0000ff00) >> 8;
  115. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  116. (i * nonce_range & 0x000000ff) >> 0;
  117. }
  118. }
  119. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  120. uint8_t tt = 0;
  121. tt = (buf[0] & 0x0f) << 4;
  122. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  123. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  124. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  125. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  126. buf[0] = tt;
  127. buf[4] = rev8(buf[4]);
  128. #endif
  129. if (at->reset)
  130. nr_len = 1;
  131. if (opt_debug) {
  132. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  133. hexdump((uint8_t *)buf, nr_len);
  134. }
  135. ret = write(fd, buf, nr_len);
  136. if (unlikely(ret != nr_len))
  137. return AVA_SEND_ERROR;
  138. if (likely(thr)) {
  139. avalon = thr->cgpu;
  140. info = avalon_info[avalon->device_id];
  141. delay = nr_len * 10 * 1000000000ULL;
  142. delay = delay / info->baud;
  143. }
  144. p.tv_sec = 0;
  145. p.tv_nsec = (long)delay + 4000000;
  146. nanosleep(&p, NULL);
  147. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  148. full = avalon_buffer_full(fd);
  149. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  150. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  151. if (unlikely(full == AVA_BUFFER_FULL))
  152. return AVA_SEND_BUFFER_FULL;
  153. return AVA_SEND_BUFFER_EMPTY;
  154. }
  155. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  156. struct thr_info *thr, struct timeval *tv_finish)
  157. {
  158. ssize_t ret = 0;
  159. int rc = 0;
  160. int read_amount = AVALON_READ_SIZE;
  161. bool first = true;
  162. /* Read reply 1 byte at a time to get earliest tv_finish */
  163. while (true) {
  164. ret = read(fd, buf, 1);
  165. if (ret < 0)
  166. return AVA_GETS_ERROR;
  167. if (first && tv_finish != NULL)
  168. gettimeofday(tv_finish, NULL);
  169. if (ret >= read_amount)
  170. return AVA_GETS_OK;
  171. if (ret > 0) {
  172. buf += ret;
  173. read_amount -= ret;
  174. first = false;
  175. continue;
  176. }
  177. rc++;
  178. if (rc >= read_count) {
  179. if (opt_debug) {
  180. applog(LOG_WARNING,
  181. "Avalon: No data in %.2f seconds",
  182. (float)rc/(float)TIME_FACTOR);
  183. }
  184. return AVA_GETS_TIMEOUT;
  185. }
  186. if (thr && thr->work_restart) {
  187. if (opt_debug) {
  188. applog(LOG_WARNING,
  189. "Avalon: Work restart at %.2f seconds",
  190. (float)(rc)/(float)TIME_FACTOR);
  191. }
  192. return AVA_GETS_RESTART;
  193. }
  194. }
  195. }
  196. static int avalon_get_result(int fd, struct avalon_result *ar,
  197. struct thr_info *thr, struct timeval *tv_finish)
  198. {
  199. struct cgpu_info *avalon;
  200. struct avalon_info *info;
  201. uint8_t result[AVALON_READ_SIZE];
  202. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  203. if (likely(thr)) {
  204. avalon = thr->cgpu;
  205. info = avalon_info[avalon->device_id];
  206. read_count = info->read_count;
  207. }
  208. memset(result, 0, AVALON_READ_SIZE);
  209. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  210. if (ret == AVA_GETS_OK) {
  211. if (opt_debug) {
  212. applog(LOG_DEBUG, "Avalon: get:");
  213. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  214. }
  215. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  216. }
  217. return ret;
  218. }
  219. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  220. struct avalon_result *ar, uint32_t *nonce)
  221. {
  222. struct cgpu_info *avalon;
  223. struct avalon_info *info;
  224. int avalon_get_work_count, i;
  225. if (unlikely(!work))
  226. return -1;
  227. avalon = thr->cgpu;
  228. info = avalon_info[avalon->device_id];
  229. avalon_get_work_count = info->miner_count;
  230. for (i = 0; i < avalon_get_work_count; i++) {
  231. if (work[i] &&
  232. !memcmp(ar->data, work[i]->data + 64, 12) &&
  233. !memcmp(ar->midstate, work[i]->midstate, 32))
  234. break;
  235. }
  236. if (i == avalon_get_work_count)
  237. return -1;
  238. ++info->matching_work[i];
  239. *nonce = ar->nonce;
  240. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  241. *nonce = swab32(*nonce);
  242. #endif
  243. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  244. info->matching_work[i]);
  245. return i;
  246. }
  247. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  248. uint8_t miner_num_p, struct avalon_result *ar)
  249. {
  250. struct avalon_task at;
  251. uint8_t *buf;
  252. int ret, i = 0;
  253. struct timespec p;
  254. avalon_init_task(NULL,
  255. &at, 1, 0,
  256. AVALON_DEFAULT_FAN_PWM,
  257. timeout_p, asic_num_p, miner_num_p, 1);
  258. ret = avalon_send_task(fd, &at, NULL);
  259. if (ret == AVA_SEND_ERROR)
  260. return 1;
  261. avalon_get_result(fd, ar, NULL, NULL);
  262. buf = (uint8_t *)ar;
  263. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  264. buf[2] == 0xAA && buf[3] == 0x55) {
  265. for (i = 4; i < 11; i++)
  266. if (buf[i] != 0)
  267. break;
  268. }
  269. if (i != 11) {
  270. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  271. " (%d: %02x %02x %02x %02x)",
  272. i, buf[0], buf[1], buf[2], buf[3]);
  273. /* FIXME: return 1; */
  274. }
  275. p.tv_sec = 1;
  276. p.tv_nsec = AVALON_RESET_PITCH;
  277. nanosleep(&p, NULL);
  278. applog(LOG_WARNING,
  279. "Avalon reset: Fan1: %d, Fan2: %d, Fan3: %d\t"
  280. "Temp1: %d, Temp2: %d, Temp3: %d",
  281. ar->fan0, ar->fan1, ar->fan2, ar->temp0, ar->temp1, ar->temp2);
  282. applog(LOG_WARNING, "Avalon: Reset succeeded");
  283. return 0;
  284. }
  285. static void get_options(int this_option_offset, int *baud, int *miner_count,
  286. int *asic_count, int *timeout)
  287. {
  288. char err_buf[BUFSIZ+1];
  289. char buf[BUFSIZ+1];
  290. char *ptr, *comma, *colon, *colon2, *colon3;
  291. size_t max;
  292. int i, tmp;
  293. if (opt_avalon_options == NULL)
  294. buf[0] = '\0';
  295. else {
  296. ptr = opt_avalon_options;
  297. for (i = 0; i < this_option_offset; i++) {
  298. comma = strchr(ptr, ',');
  299. if (comma == NULL)
  300. break;
  301. ptr = comma + 1;
  302. }
  303. comma = strchr(ptr, ',');
  304. if (comma == NULL)
  305. max = strlen(ptr);
  306. else
  307. max = comma - ptr;
  308. if (max > BUFSIZ)
  309. max = BUFSIZ;
  310. strncpy(buf, ptr, max);
  311. buf[max] = '\0';
  312. }
  313. *baud = AVALON_IO_SPEED;
  314. *miner_count = AVALON_DEFAULT_MINER_NUM;
  315. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  316. *timeout = AVALON_DEFAULT_TIMEOUT;
  317. if (!(*buf))
  318. return;
  319. colon = strchr(buf, ':');
  320. if (colon)
  321. *(colon++) = '\0';
  322. tmp = atoi(buf);
  323. switch (tmp) {
  324. case 115200:
  325. *baud = 115200;
  326. break;
  327. case 57600:
  328. *baud = 57600;
  329. break;
  330. case 38400:
  331. *baud = 38400;
  332. break;
  333. case 19200:
  334. *baud = 19200;
  335. break;
  336. default:
  337. sprintf(err_buf,
  338. "Invalid avalon-options for baud (%s) "
  339. "must be 115200, 57600, 38400 or 19200", buf);
  340. quit(1, err_buf);
  341. }
  342. if (colon && *colon) {
  343. colon2 = strchr(colon, ':');
  344. if (colon2)
  345. *(colon2++) = '\0';
  346. if (*colon) {
  347. tmp = atoi(colon);
  348. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  349. *miner_count = tmp;
  350. } else {
  351. sprintf(err_buf,
  352. "Invalid avalon-options for "
  353. "miner_count (%s) must be 1 ~ %d",
  354. colon, AVALON_DEFAULT_MINER_NUM);
  355. quit(1, err_buf);
  356. }
  357. }
  358. if (colon2 && *colon2) {
  359. colon3 = strchr(colon2, ':');
  360. if (colon3)
  361. *(colon3++) = '\0';
  362. tmp = atoi(colon2);
  363. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  364. *asic_count = tmp;
  365. else {
  366. sprintf(err_buf,
  367. "Invalid avalon-options for "
  368. "asic_count (%s) must be 1 ~ %d",
  369. colon2, AVALON_DEFAULT_ASIC_NUM);
  370. quit(1, err_buf);
  371. }
  372. if (colon3 && *colon3) {
  373. tmp = atoi(colon3);
  374. if (tmp > 0 && tmp <= 0xff)
  375. *timeout = tmp;
  376. else {
  377. sprintf(err_buf,
  378. "Invalid avalon-options for "
  379. "timeout (%s) must be 1 ~ %d",
  380. colon3, 0xff);
  381. quit(1, err_buf);
  382. }
  383. }
  384. }
  385. }
  386. }
  387. static bool avalon_detect_one(const char *devpath)
  388. {
  389. struct avalon_info *info;
  390. struct avalon_result ar;
  391. int fd, ret;
  392. int baud, miner_count, asic_count, timeout;
  393. int this_option_offset = ++option_offset;
  394. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  395. &timeout);
  396. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  397. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  398. devpath, baud, miner_count, asic_count, timeout);
  399. fd = avalon_open2(devpath, baud, true);
  400. if (unlikely(fd == -1)) {
  401. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  402. return false;
  403. }
  404. ret = avalon_reset(fd, timeout, asic_count, miner_count, &ar);
  405. avalon_close(fd);
  406. if (ret) {
  407. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  408. }
  409. /* We have a real Avalon! */
  410. struct cgpu_info *avalon;
  411. avalon = calloc(1, sizeof(struct cgpu_info));
  412. avalon->api = &avalon_api;
  413. avalon->device_path = strdup(devpath);
  414. avalon->device_fd = -1;
  415. avalon->threads = AVALON_MINER_THREADS;
  416. add_cgpu(avalon);
  417. avalon_info = realloc(avalon_info,
  418. sizeof(struct avalon_info *) *
  419. (total_devices + 1));
  420. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  421. devpath, avalon->device_id);
  422. avalon_info[avalon->device_id] = (struct avalon_info *)
  423. malloc(sizeof(struct avalon_info));
  424. if (unlikely(!(avalon_info[avalon->device_id])))
  425. quit(1, "Failed to malloc avalon_info");
  426. info = avalon_info[avalon->device_id];
  427. memset(info, 0, sizeof(struct avalon_info));
  428. info->baud = baud;
  429. info->miner_count = miner_count;
  430. info->asic_count = asic_count;
  431. info->timeout = timeout;
  432. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  433. TIME_FACTOR) / (float)info->miner_count;
  434. return true;
  435. }
  436. static inline void avalon_detect()
  437. {
  438. serial_detect(&avalon_api, avalon_detect_one);
  439. }
  440. static bool avalon_prepare(struct thr_info *thr)
  441. {
  442. struct avalon_result ar;
  443. struct cgpu_info *avalon = thr->cgpu;
  444. struct timeval now;
  445. int fd, ret;
  446. struct avalon_info *info = avalon_info[avalon->device_id];
  447. avalon->device_fd = -1;
  448. fd = avalon_open(avalon->device_path,
  449. avalon_info[avalon->device_id]->baud);
  450. if (unlikely(fd == -1)) {
  451. applog(LOG_ERR, "Avalon: Failed to open on %s",
  452. avalon->device_path);
  453. return false;
  454. }
  455. ret = avalon_reset(fd, info->timeout, info->asic_count,
  456. info->miner_count, &ar);
  457. if (ret)
  458. return false;
  459. avalon->device_fd = fd;
  460. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  461. gettimeofday(&now, NULL);
  462. get_datestamp(avalon->init, &now);
  463. return true;
  464. }
  465. static void avalon_free_work(struct thr_info *thr, struct work **work)
  466. {
  467. struct cgpu_info *avalon;
  468. struct avalon_info *info;
  469. int i;
  470. if (unlikely(!work))
  471. return;
  472. avalon = thr->cgpu;
  473. info = avalon_info[avalon->device_id];
  474. for (i = 0; i < info->miner_count; i++)
  475. if (likely(work[i])) {
  476. free_work(work[i]);
  477. work[i] = NULL;
  478. }
  479. }
  480. static void do_avalon_close(struct thr_info *thr)
  481. {
  482. struct cgpu_info *avalon = thr->cgpu;
  483. struct avalon_info *info = avalon_info[avalon->device_id];
  484. avalon_close(avalon->device_fd);
  485. avalon->device_fd = -1;
  486. info->no_matching_work = 0;
  487. avalon_free_work(thr, info->bulk0);
  488. avalon_free_work(thr, info->bulk1);
  489. avalon_free_work(thr, info->bulk2);
  490. avalon_free_work(thr, info->bulk3);
  491. }
  492. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  493. __maybe_unused int64_t max_nonce)
  494. {
  495. struct cgpu_info *avalon;
  496. int fd, ret, full;
  497. struct avalon_info *info;
  498. struct avalon_task at;
  499. struct avalon_result ar;
  500. int i, work_i0, work_i1, work_i2, work_i3;
  501. int avalon_get_work_count;
  502. struct timeval tv_start, tv_finish, elapsed;
  503. uint32_t nonce;
  504. int64_t hash_count;
  505. static int first_try = 0;
  506. avalon = thr->cgpu;
  507. info = avalon_info[avalon->device_id];
  508. avalon_get_work_count = info->miner_count;
  509. if (unlikely(avalon->device_fd == -1))
  510. if (!avalon_prepare(thr)) {
  511. applog(LOG_ERR, "AVA%i: Comms error(open)",
  512. avalon->device_id);
  513. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  514. /* fail the device if the reopen attempt fails */
  515. return -1;
  516. }
  517. fd = avalon->device_fd;
  518. #ifndef WIN32
  519. tcflush(fd, TCOFLUSH);
  520. #endif
  521. for (i = 0; i < avalon_get_work_count; i++) {
  522. info->bulk0[i] = info->bulk1[i];
  523. info->bulk1[i] = info->bulk2[i];
  524. info->bulk2[i] = info->bulk3[i];
  525. info->bulk3[i] = work[i];
  526. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  527. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  528. }
  529. i = 0;
  530. while (true) {
  531. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0, 1);
  532. avalon_create_task(&at, work[i]);
  533. ret = avalon_send_task(fd, &at, thr);
  534. if (unlikely(ret == AVA_SEND_ERROR ||
  535. (ret == AVA_SEND_BUFFER_EMPTY &&
  536. (i + 1 == avalon_get_work_count) &&
  537. first_try))) {
  538. avalon_free_work(thr, info->bulk0);
  539. avalon_free_work(thr, info->bulk1);
  540. avalon_free_work(thr, info->bulk2);
  541. avalon_free_work(thr, info->bulk3);
  542. do_avalon_close(thr);
  543. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  544. avalon->device_id);
  545. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  546. first_try = 0;
  547. sleep(1);
  548. return 0; /* This should never happen */
  549. }
  550. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  551. first_try = 1;
  552. return 0xffffffff;
  553. }
  554. work[i]->blk.nonce = 0xffffffff;
  555. if (ret == AVA_SEND_BUFFER_FULL)
  556. break;
  557. i++;
  558. }
  559. if (unlikely(first_try))
  560. first_try = 0;
  561. elapsed.tv_sec = elapsed.tv_usec = 0;
  562. gettimeofday(&tv_start, NULL);
  563. hash_count = 0;
  564. while (true) {
  565. work_i0 = work_i1 = work_i2 = -1;
  566. full = avalon_buffer_full(fd);
  567. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  568. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  569. if (unlikely(full == AVA_BUFFER_EMPTY))
  570. break;
  571. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  572. if (unlikely(ret == AVA_GETS_ERROR)) {
  573. avalon_free_work(thr, info->bulk0);
  574. avalon_free_work(thr, info->bulk1);
  575. avalon_free_work(thr, info->bulk2);
  576. avalon_free_work(thr, info->bulk3);
  577. do_avalon_close(thr);
  578. applog(LOG_ERR,
  579. "AVA%i: Comms error(read)", avalon->device_id);
  580. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  581. return 0;
  582. }
  583. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  584. timersub(&tv_finish, &tv_start, &elapsed);
  585. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  586. elapsed.tv_sec, elapsed.tv_usec);
  587. continue;
  588. }
  589. if (unlikely(ret == AVA_GETS_RESTART)) {
  590. avalon_free_work(thr, info->bulk0);
  591. avalon_free_work(thr, info->bulk1);
  592. avalon_free_work(thr, info->bulk2);
  593. avalon_free_work(thr, info->bulk3);
  594. continue;
  595. }
  596. avalon->temp = (ar.temp0 + ar.temp1 + ar.temp2) / 3;
  597. info->fan0 = ar.fan0;
  598. info->fan1 = ar.fan1;
  599. info->fan2 = ar.fan2;
  600. info->temp0 = ar.temp0;
  601. info->temp1 = ar.temp1;
  602. info->temp2 = ar.temp2;
  603. if (info->temp0 > info->temp_max)
  604. info->temp_max = info->temp0;
  605. if (info->temp1 > info->temp_max)
  606. info->temp_max = info->temp1;
  607. if (info->temp2 > info->temp_max)
  608. info->temp_max = info->temp2;
  609. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  610. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  611. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  612. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  613. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  614. if (opt_debug) {
  615. timersub(&tv_finish, &tv_start, &elapsed);
  616. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  617. " (%ld.%06lds)", ++info->no_matching_work,
  618. elapsed.tv_sec, elapsed.tv_usec);
  619. }
  620. continue;
  621. }
  622. if (work_i0 >= 0)
  623. submit_nonce(thr, info->bulk0[work_i0], nonce);
  624. if (work_i1 >= 0)
  625. submit_nonce(thr, info->bulk1[work_i1], nonce);
  626. if (work_i2 >= 0)
  627. submit_nonce(thr, info->bulk2[work_i2], nonce);
  628. if (work_i3 >= 0)
  629. submit_nonce(thr, info->bulk3[work_i3], nonce);
  630. hash_count += nonce;
  631. if (opt_debug) {
  632. timersub(&tv_finish, &tv_start, &elapsed);
  633. applog(LOG_DEBUG,
  634. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  635. "(%ld.%06lds)", nonce, hash_count,
  636. elapsed.tv_sec, elapsed.tv_usec);
  637. }
  638. }
  639. avalon_free_work(thr, info->bulk0);
  640. applog(LOG_WARNING,
  641. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  642. "Temp1: %d, Temp2: %d, Temp3: %d, TempMAX: %d",
  643. info->fan0, info->fan1, info->fan2,
  644. info->temp0, info->temp1, info->temp2, info->temp_max);
  645. /*
  646. * TODO: add fan/temp control
  647. * 1. add task_num to init_task
  648. * 2. record the gate_status at info-> [code here].
  649. * when TEMP reach a HIGH gate miner
  650. * when TEMP reach a LOW trigger miner
  651. * 3. enable/disable gate on init_task
  652. */
  653. /*
  654. * FIXME: Each work split to 10 pieces, each piece send to a
  655. * asic(256MHs). one work can be mulit-nonce back. it is not
  656. * easy calculate correct hash on such situation. so I simplely
  657. * add each nonce to hash_count. base on Utility/m hash_count*2
  658. * give a very good result.
  659. *
  660. * Any patch will be great.
  661. */
  662. return (hash_count * 2);
  663. }
  664. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  665. {
  666. struct api_data *root = NULL;
  667. struct avalon_info *info = avalon_info[cgpu->device_id];
  668. root = api_add_int(root, "read_count", &(info->read_count), false);
  669. root = api_add_int(root, "baud", &(info->baud), false);
  670. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  671. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  672. root = api_add_int(root, "fan1", &(info->fan0), false);
  673. root = api_add_int(root, "fan2", &(info->fan1), false);
  674. root = api_add_int(root, "fan3", &(info->fan2), false);
  675. root = api_add_int(root, "temp1", &(info->temp0), false);
  676. root = api_add_int(root, "temp2", &(info->temp1), false);
  677. root = api_add_int(root, "temp3", &(info->temp2), false);
  678. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  679. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  680. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  681. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  682. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  683. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  684. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  685. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  686. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  687. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  688. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  689. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  690. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  691. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  692. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  693. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  694. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  695. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  696. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  697. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  698. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  699. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  700. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  701. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  702. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  703. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  704. return root;
  705. }
  706. static void avalon_shutdown(struct thr_info *thr)
  707. {
  708. do_avalon_close(thr);
  709. }
  710. struct device_api avalon_api = {
  711. .dname = "avalon",
  712. .name = "AVA",
  713. .api_detect = avalon_detect,
  714. .thread_prepare = avalon_prepare,
  715. .scanhash_queue = avalon_scanhash,
  716. .get_api_stats = avalon_api_stats,
  717. .thread_shutdown = avalon_shutdown,
  718. };