driver-avalon.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757
  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (!at)
  48. return -1;
  49. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (thr) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (reset) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (first && !at->reset) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = 1;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at)
  89. {
  90. size_t ret;
  91. int full;
  92. struct timespec p;
  93. uint8_t *buf;
  94. size_t nr_len;
  95. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  96. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  97. if (!buf)
  98. return AVA_SEND_ERROR;
  99. memcpy(buf, at, AVALON_WRITE_SIZE);
  100. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  101. uint8_t tt = 0;
  102. tt = (buf[0] & 0x0f) << 4;
  103. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  104. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  105. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  106. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  107. buf[0] = tt;
  108. buf[4] = rev8(buf[4]);
  109. #endif
  110. if (opt_debug) {
  111. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  112. hexdump((uint8_t *)buf, nr_len);
  113. }
  114. ret = write(fd, buf, nr_len);
  115. free(buf);
  116. if (unlikely(ret != nr_len))
  117. return AVA_SEND_ERROR;
  118. p.tv_sec = 0;
  119. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  120. nanosleep(&p, NULL);
  121. full = avalon_buffer_full(fd);
  122. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  123. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  124. if (full == AVA_BUFFER_EMPTY)
  125. return AVA_SEND_BUFFER_EMPTY;
  126. return AVA_SEND_BUFFER_FULL;
  127. }
  128. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  129. struct thr_info *thr, struct timeval *tv_finish)
  130. {
  131. ssize_t ret = 0;
  132. int rc = 0;
  133. int read_amount = AVALON_READ_SIZE;
  134. bool first = true;
  135. /* Read reply 1 byte at a time to get earliest tv_finish */
  136. while (true) {
  137. ret = read(fd, buf, 1);
  138. if (ret < 0)
  139. return AVA_GETS_ERROR;
  140. if (first && tv_finish != NULL)
  141. gettimeofday(tv_finish, NULL);
  142. if (ret >= read_amount)
  143. return AVA_GETS_OK;
  144. if (ret > 0) {
  145. buf += ret;
  146. read_amount -= ret;
  147. first = false;
  148. continue;
  149. }
  150. rc++;
  151. if (rc >= read_count) {
  152. if (opt_debug) {
  153. applog(LOG_ERR,
  154. "Avalon: No data in %.2f seconds",
  155. (float)rc/(float)TIME_FACTOR);
  156. }
  157. return AVA_GETS_TIMEOUT;
  158. }
  159. if (thr && thr->work_restart) {
  160. if (opt_debug) {
  161. applog(LOG_ERR,
  162. "Avalon: Work restart at %.2f seconds",
  163. (float)(rc)/(float)TIME_FACTOR);
  164. }
  165. return AVA_GETS_RESTART;
  166. }
  167. }
  168. }
  169. static int avalon_get_result(int fd, struct avalon_result *ar,
  170. struct thr_info *thr, struct timeval *tv_finish)
  171. {
  172. struct cgpu_info *avalon;
  173. struct avalon_info *info;
  174. uint8_t result[AVALON_READ_SIZE];
  175. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  176. if (thr) {
  177. avalon = thr->cgpu;
  178. info = avalon_info[avalon->device_id];
  179. read_count = info->read_count;
  180. }
  181. memset(result, 0, AVALON_READ_SIZE);
  182. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  183. if (ret == AVA_GETS_OK) {
  184. if (opt_debug) {
  185. applog(LOG_DEBUG, "Avalon: get:");
  186. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  187. }
  188. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  189. }
  190. return ret;
  191. }
  192. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  193. struct avalon_result *ar, uint32_t *nonce)
  194. {
  195. struct cgpu_info *avalon;
  196. struct avalon_info *info;
  197. int avalon_get_work_count, i;
  198. if (!work)
  199. return -1;
  200. avalon = thr->cgpu;
  201. info = avalon_info[avalon->device_id];
  202. avalon_get_work_count = info->miner_count;
  203. for (i = 0; i < avalon_get_work_count; i++) {
  204. if (work[i] &&
  205. !memcmp(ar->data, work[i]->data + 64, 12) &&
  206. !memcmp(ar->midstate, work[i]->midstate, 32))
  207. break;
  208. }
  209. if (i == avalon_get_work_count)
  210. return -1;
  211. *nonce = ar->nonce;
  212. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  213. *nonce = swab32(*nonce);
  214. #endif
  215. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  216. return i;
  217. }
  218. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  219. {
  220. struct avalon_task at;
  221. struct avalon_result ar;
  222. uint8_t *buf;
  223. int ret, i;
  224. struct timespec p;
  225. avalon_init_task(NULL,
  226. &at, 1, 0,
  227. AVALON_DEFAULT_FAN_PWM,
  228. timeout_p, asic_num_p, miner_num_p);
  229. ret = avalon_send_task(fd, &at);
  230. if (ret == AVA_SEND_ERROR)
  231. return 1;
  232. avalon_get_result(fd, &ar, NULL, NULL);
  233. buf = (uint8_t *)&ar;
  234. for (i = 0; i < 11; i++)
  235. if (buf[i] != 0)
  236. break;
  237. /* FIXME: add more avalon info base on return */
  238. if (i != 11) {
  239. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  240. return 1;
  241. }
  242. p.tv_sec = 1;
  243. p.tv_nsec = AVALON_RESET_PITCH;
  244. nanosleep(&p, NULL);
  245. applog(LOG_ERR,
  246. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  247. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  248. applog(LOG_ERR, "Avalon: Reset succeeded");
  249. return 0;
  250. }
  251. static void do_avalon_close(struct thr_info *thr)
  252. {
  253. struct cgpu_info *avalon = thr->cgpu;
  254. avalon_close(avalon->device_fd);
  255. avalon->device_fd = -1;
  256. /* FIXME: we should free the bulk0/1/2 */
  257. }
  258. static void set_timing_mode(struct cgpu_info *avalon)
  259. {
  260. struct avalon_info *info = avalon_info[avalon->device_id];
  261. /* Anything else in buf just uses DEFAULT mode */
  262. info->Hs = AVALON_HASH_TIME;
  263. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  264. info->read_count =
  265. (int)(info->fullnonce * TIME_FACTOR) - 1;
  266. }
  267. static void get_options(int this_option_offset, int *baud, int *miner_count,
  268. int *asic_count, int *timeout)
  269. {
  270. char err_buf[BUFSIZ+1];
  271. char buf[BUFSIZ+1];
  272. char *ptr, *comma, *colon, *colon2, *colon3;
  273. size_t max;
  274. int i, tmp;
  275. if (opt_avalon_options == NULL)
  276. buf[0] = '\0';
  277. else {
  278. ptr = opt_avalon_options;
  279. for (i = 0; i < this_option_offset; i++) {
  280. comma = strchr(ptr, ',');
  281. if (comma == NULL)
  282. break;
  283. ptr = comma + 1;
  284. }
  285. comma = strchr(ptr, ',');
  286. if (comma == NULL)
  287. max = strlen(ptr);
  288. else
  289. max = comma - ptr;
  290. if (max > BUFSIZ)
  291. max = BUFSIZ;
  292. strncpy(buf, ptr, max);
  293. buf[max] = '\0';
  294. }
  295. *baud = AVALON_IO_SPEED;
  296. *miner_count = AVALON_DEFAULT_MINER_NUM;
  297. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  298. *timeout = AVALON_DEFAULT_TIMEOUT;
  299. if (!(*buf))
  300. return;
  301. colon = strchr(buf, ':');
  302. if (colon)
  303. *(colon++) = '\0';
  304. tmp = atoi(buf);
  305. switch (tmp) {
  306. case 115200:
  307. *baud = 115200;
  308. break;
  309. case 57600:
  310. *baud = 57600;
  311. break;
  312. case 19200:
  313. *baud = 19200;
  314. break;
  315. default:
  316. sprintf(err_buf,
  317. "Invalid avalon-options for baud (%s) "
  318. "must be 115200, 57600 or 19200", buf);
  319. quit(1, err_buf);
  320. }
  321. if (colon && *colon) {
  322. colon2 = strchr(colon, ':');
  323. if (colon2)
  324. *(colon2++) = '\0';
  325. if (*colon) {
  326. tmp = atoi(colon);
  327. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  328. *miner_count = tmp;
  329. } else {
  330. sprintf(err_buf,
  331. "Invalid avalon-options for "
  332. "miner_count (%s) must be 1 ~ %d",
  333. colon, AVALON_DEFAULT_MINER_NUM);
  334. quit(1, err_buf);
  335. }
  336. }
  337. if (colon2 && *colon2) {
  338. colon3 = strchr(colon2, ':');
  339. if (colon3)
  340. *(colon3++) = '\0';
  341. tmp = atoi(colon2);
  342. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  343. *asic_count = tmp;
  344. else {
  345. sprintf(err_buf,
  346. "Invalid avalon-options for "
  347. "asic_count (%s) must be 1 ~ %d",
  348. colon2, AVALON_DEFAULT_ASIC_NUM);
  349. quit(1, err_buf);
  350. }
  351. if (colon3 && *colon3) {
  352. tmp = atoi(colon3);
  353. if (tmp > 0 && tmp <= 0xff)
  354. *timeout = tmp;
  355. else {
  356. sprintf(err_buf,
  357. "Invalid avalon-options for "
  358. "timeout (%s) must be 1 ~ %d",
  359. colon3, 0xff);
  360. quit(1, err_buf);
  361. }
  362. }
  363. }
  364. }
  365. }
  366. static bool avalon_detect_one(const char *devpath)
  367. {
  368. struct avalon_info *info;
  369. int fd, ret;
  370. int baud, miner_count, asic_count, timeout;
  371. int this_option_offset = ++option_offset;
  372. get_options(this_option_offset, &baud, &miner_count, &asic_count, &timeout);
  373. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  374. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  375. devpath, baud, miner_count, asic_count, timeout);
  376. fd = avalon_open2(devpath, baud, true);
  377. if (unlikely(fd == -1)) {
  378. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  379. return false;
  380. }
  381. ret = avalon_reset(fd, timeout, asic_count, miner_count);
  382. avalon_close(fd);
  383. if (ret)
  384. return false;
  385. /* We have a real Avalon! */
  386. struct cgpu_info *avalon;
  387. avalon = calloc(1, sizeof(struct cgpu_info));
  388. avalon->api = &avalon_api;
  389. avalon->device_path = strdup(devpath);
  390. avalon->device_fd = -1;
  391. avalon->threads = AVALON_MINER_THREADS;
  392. add_cgpu(avalon);
  393. avalon_info = realloc(avalon_info,
  394. sizeof(struct avalon_info *) *
  395. (total_devices + 1));
  396. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  397. devpath, avalon->device_id);
  398. avalon_info[avalon->device_id] = (struct avalon_info *)
  399. malloc(sizeof(struct avalon_info));
  400. if (unlikely(!(avalon_info[avalon->device_id])))
  401. quit(1, "Failed to malloc avalon_info");
  402. info = avalon_info[avalon->device_id];
  403. memset(info, 0, sizeof(struct avalon_info));
  404. info->baud = baud;
  405. info->miner_count = miner_count;
  406. info->asic_count = asic_count;
  407. info->timeout = timeout;
  408. set_timing_mode(avalon);
  409. return true;
  410. }
  411. static inline void avalon_detect()
  412. {
  413. serial_detect(&avalon_api, avalon_detect_one);
  414. }
  415. static bool avalon_prepare(struct thr_info *thr)
  416. {
  417. struct cgpu_info *avalon = thr->cgpu;
  418. struct timeval now;
  419. int fd, ret;
  420. struct avalon_info *info = avalon_info[avalon->device_id];
  421. avalon->device_fd = -1;
  422. fd = avalon_open(avalon->device_path,
  423. avalon_info[avalon->device_id]->baud);
  424. if (unlikely(fd == -1)) {
  425. applog(LOG_ERR, "Avalon: Failed to open on %s",
  426. avalon->device_path);
  427. return false;
  428. }
  429. ret = avalon_reset(fd, info->timeout, info->asic_count, info->miner_count);
  430. if (ret)
  431. return false;
  432. avalon->device_fd = fd;
  433. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  434. gettimeofday(&now, NULL);
  435. get_datestamp(avalon->init, &now);
  436. return true;
  437. }
  438. static void avalon_free_work(struct thr_info *thr, struct work **work)
  439. {
  440. struct cgpu_info *avalon;
  441. struct avalon_info *info;
  442. int avalon_get_work_count, i;
  443. if (!work)
  444. return;
  445. avalon = thr->cgpu;
  446. info = avalon_info[avalon->device_id];
  447. avalon_get_work_count = info->miner_count;
  448. for (i = 0; i < avalon_get_work_count; i++)
  449. if (work[i]) {
  450. free_work(work[i]);
  451. work[i] = NULL;
  452. }
  453. }
  454. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  455. __maybe_unused int64_t max_nonce)
  456. {
  457. struct cgpu_info *avalon;
  458. int fd;
  459. int ret;
  460. int full;
  461. struct avalon_info *info;
  462. struct avalon_task at;
  463. struct avalon_result ar;
  464. static struct work *bulk0[AVALON_DEFAULT_MINER_NUM] = {
  465. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  466. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  467. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  468. static struct work *bulk1[AVALON_DEFAULT_MINER_NUM] = {
  469. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  470. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  471. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  472. static struct work *bulk2[AVALON_DEFAULT_MINER_NUM] = {
  473. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  474. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  475. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
  476. struct work **work = NULL;
  477. int i, work_i0, work_i1, work_i2;
  478. int avalon_get_work_count;
  479. uint32_t nonce;
  480. int64_t hash_count;
  481. struct timeval tv_start, tv_finish, elapsed;
  482. int curr_hw_errors;
  483. bool was_hw_error;
  484. int64_t estimate_hashes;
  485. avalon = thr->cgpu;
  486. info = avalon_info[avalon->device_id];
  487. avalon_get_work_count = info->miner_count;
  488. if (avalon->device_fd == -1)
  489. if (!avalon_prepare(thr)) {
  490. applog(LOG_ERR, "AVA%i: Comms error",
  491. avalon->device_id);
  492. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  493. /* fail the device if the reopen attempt fails */
  494. return -1;
  495. }
  496. fd = avalon->device_fd;
  497. #ifndef WIN32
  498. tcflush(fd, TCOFLUSH);
  499. #endif
  500. work = bulk_work;
  501. for (i = 0; i < avalon_get_work_count; i++) {
  502. bulk0[i] = bulk1[i];
  503. bulk1[i] = bulk2[i];
  504. bulk2[i] = work[i];
  505. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  506. i, bulk0[i], bulk1[i], bulk2[i]);
  507. }
  508. i = 0;
  509. while (true) {
  510. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  511. avalon_create_task(&at, work[i]);
  512. ret = avalon_send_task(fd, &at);
  513. if (ret == AVA_SEND_ERROR ||
  514. (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count))) {
  515. avalon_free_work(thr, bulk0);
  516. avalon_free_work(thr, bulk1);
  517. avalon_free_work(thr, bulk2);
  518. do_avalon_close(thr);
  519. applog(LOG_ERR, "AVA%i: Comms error",
  520. avalon->device_id);
  521. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  522. sleep(1);
  523. return 0; /* This should never happen */
  524. }
  525. work[i]->blk.nonce = 0xffffffff;
  526. if (ret == AVA_SEND_BUFFER_FULL)
  527. break;
  528. i++;
  529. }
  530. elapsed.tv_sec = elapsed.tv_usec = 0;
  531. gettimeofday(&tv_start, NULL);
  532. while(true) {
  533. full = avalon_buffer_full(fd);
  534. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  535. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  536. if (full == AVA_BUFFER_EMPTY)
  537. break;
  538. work_i0 = work_i1 = work_i2 = -1;
  539. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  540. if (ret == AVA_GETS_ERROR) {
  541. avalon_free_work(thr, bulk0);
  542. avalon_free_work(thr, bulk1);
  543. avalon_free_work(thr, bulk2);
  544. do_avalon_close(thr);
  545. applog(LOG_ERR,
  546. "AVA%i: Comms error", avalon->device_id);
  547. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  548. return 0;
  549. }
  550. /* aborted before becoming idle, get new work */
  551. if (ret == AVA_GETS_TIMEOUT) {
  552. timersub(&tv_finish, &tv_start, &elapsed);
  553. estimate_hashes = ((double)(elapsed.tv_sec) +
  554. ((double)(elapsed.tv_usec)) /
  555. ((double)1000000)) / info->Hs;
  556. /* If Serial-USB delay allowed the full nonce range to
  557. * complete it can't have done more than a full nonce
  558. */
  559. if (unlikely(estimate_hashes > 0xffffffff))
  560. estimate_hashes = 0xffffffff;
  561. applog(LOG_DEBUG,
  562. "Avalon: no nonce = 0x%08llx hashes "
  563. "(%ld.%06lds)",
  564. estimate_hashes, elapsed.tv_sec,
  565. elapsed.tv_usec);
  566. continue;
  567. }
  568. if (ret == AVA_GETS_RESTART) {
  569. avalon_free_work(thr, bulk0);
  570. avalon_free_work(thr, bulk1);
  571. avalon_free_work(thr, bulk2);
  572. continue;
  573. }
  574. avalon->temp = ar.temp0;
  575. work_i0 = avalon_decode_nonce(thr, bulk0, &ar, &nonce);
  576. work_i1 = avalon_decode_nonce(thr, bulk1, &ar, &nonce);
  577. work_i2 = avalon_decode_nonce(thr, bulk2, &ar, &nonce);
  578. curr_hw_errors = avalon->hw_errors;
  579. if (work_i0 >= 0)
  580. submit_nonce(thr, bulk0[work_i0], nonce);
  581. if (work_i1 >= 0)
  582. submit_nonce(thr, bulk1[work_i1], nonce);
  583. if (work_i2 >= 0)
  584. submit_nonce(thr, bulk2[work_i2], nonce);
  585. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  586. /* Force a USB close/reopen on any hw error */
  587. if (was_hw_error)
  588. do_avalon_close(thr);
  589. hash_count = nonce;
  590. hash_count++;
  591. hash_count *= info->asic_count;
  592. }
  593. avalon_free_work(thr, bulk0);
  594. if (opt_debug) {
  595. timersub(&tv_finish, &tv_start, &elapsed);
  596. applog(LOG_DEBUG,
  597. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  598. "(%ld.%06lds)",
  599. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  600. }
  601. applog(LOG_ERR,
  602. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d. Temp1: %d, Temp2: %d, Temp3: %d",
  603. ar.fan0, ar.fan1, ar.fan2, ar.temp0, ar.temp1, ar.temp2);
  604. return hash_count;
  605. }
  606. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  607. {
  608. struct api_data *root = NULL;
  609. struct avalon_info *info = avalon_info[cgpu->device_id];
  610. /* Warning, access to these is not locked - but we don't really
  611. * care since hashing performance is way more important than
  612. * locking access to displaying API debug 'stats'
  613. * If locking becomes an issue for any of them, use copy_data=true also */
  614. root = api_add_int(root, "read_count", &(info->read_count), false);
  615. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  616. root = api_add_int(root, "baud", &(info->baud), false);
  617. root = api_add_int(root, "miner_count", &(info->miner_count),
  618. false);
  619. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  620. return root;
  621. }
  622. static void avalon_shutdown(struct thr_info *thr)
  623. {
  624. do_avalon_close(thr);
  625. }
  626. struct device_api avalon_api = {
  627. .dname = "avalon",
  628. .name = "AVA",
  629. .api_detect = avalon_detect,
  630. .thread_prepare = avalon_prepare,
  631. .scanhash_queue = avalon_scanhash,
  632. .get_api_stats = avalon_api_stats,
  633. .thread_shutdown = avalon_shutdown,
  634. };