driver-avalon.c 29 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. static int option_offset = -1;
  40. struct device_drv avalon_drv;
  41. static int avalon_init_task(struct avalon_task *at,
  42. uint8_t reset, uint8_t ff, uint8_t fan,
  43. uint8_t timeout, uint8_t asic_num,
  44. uint8_t miner_num, uint8_t nonce_elf,
  45. uint8_t gate_miner, int frequency)
  46. {
  47. uint8_t *buf;
  48. static bool first = true;
  49. if (unlikely(!at))
  50. return -1;
  51. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  52. return -1;
  53. memset(at, 0, sizeof(struct avalon_task));
  54. if (unlikely(reset)) {
  55. at->reset = 1;
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = true;
  59. }
  60. at->flush_fifo = (ff ? 1 : 0);
  61. at->fan_eft = (fan ? 1 : 0);
  62. if (unlikely(first && !at->reset)) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  68. at->timeout_data = timeout;
  69. at->asic_num = asic_num;
  70. at->miner_num = miner_num;
  71. at->nonce_elf = nonce_elf;
  72. at->gate_miner_elf = 1;
  73. at->asic_pll = 1;
  74. if (unlikely(gate_miner)) {
  75. at-> gate_miner = 1;
  76. at->asic_pll = 0;
  77. }
  78. buf = (uint8_t *)at;
  79. buf[5] = 0x00;
  80. buf[8] = 0x74;
  81. buf[9] = 0x01;
  82. buf[10] = 0x00;
  83. buf[11] = 0x00;
  84. if (frequency == 256) {
  85. buf[6] = 0x03;
  86. buf[7] = 0x08;
  87. } else if (frequency == 270) {
  88. buf[6] = 0x73;
  89. buf[7] = 0x08;
  90. } else if (frequency == 282) {
  91. buf[6] = 0xd3;
  92. buf[7] = 0x08;
  93. } else if (frequency == 300) {
  94. buf[6] = 0x63;
  95. buf[7] = 0x09;
  96. }
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  106. {
  107. int err, amount;
  108. err = usb_write(avalon, buf, len, &amount, ep);
  109. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  110. avalon->device_id, err);
  111. if (unlikely(err != 0)) {
  112. applog(LOG_WARNING, "usb_write error on avalon_write");
  113. return AVA_SEND_ERROR;
  114. }
  115. if (amount != len) {
  116. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  117. return AVA_SEND_ERROR;
  118. }
  119. return AVA_SEND_OK;
  120. }
  121. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  122. {
  123. struct timespec p;
  124. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  125. size_t nr_len;
  126. struct avalon_info *info;
  127. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  128. uint32_t nonce_range;
  129. int ret, i, ep = C_AVALON_TASK;
  130. if (at->nonce_elf)
  131. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  132. else
  133. nr_len = AVALON_WRITE_SIZE;
  134. memcpy(buf, at, AVALON_WRITE_SIZE);
  135. if (at->nonce_elf) {
  136. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  137. for (i = 0; i < at->asic_num; i++) {
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  139. (i * nonce_range & 0xff000000) >> 24;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  141. (i * nonce_range & 0x00ff0000) >> 16;
  142. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  143. (i * nonce_range & 0x0000ff00) >> 8;
  144. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  145. (i * nonce_range & 0x000000ff) >> 0;
  146. }
  147. }
  148. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  149. uint8_t tt = 0;
  150. tt = (buf[0] & 0x0f) << 4;
  151. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  152. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  153. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  154. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  155. buf[0] = tt;
  156. tt = (buf[4] & 0x0f) << 4;
  157. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  158. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  159. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  160. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  161. buf[4] = tt;
  162. #endif
  163. if (likely(avalon)) {
  164. info = avalon->device_data;
  165. delay = nr_len * 10 * 1000000000ULL;
  166. delay = delay / info->baud;
  167. }
  168. if (at->reset) {
  169. ep = C_AVALON_RESET;
  170. nr_len = 1;
  171. }
  172. if (opt_debug) {
  173. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  174. hexdump(buf, nr_len);
  175. }
  176. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  177. p.tv_sec = 0;
  178. p.tv_nsec = (long)delay + 4000000;
  179. nanosleep(&p, NULL);
  180. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  181. return ret;
  182. }
  183. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  184. struct avalon_info *info, struct avalon_result *ar,
  185. struct work *work)
  186. {
  187. uint32_t nonce;
  188. info = avalon->device_data;
  189. info->matching_work[work->subid]++;
  190. nonce = htole32(ar->nonce);
  191. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  192. return submit_nonce(thr, work, nonce);
  193. }
  194. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  195. static void wait_avalon_ready(struct cgpu_info *avalon)
  196. {
  197. while (avalon_buffer_full(avalon)) {
  198. nmsleep(40);
  199. }
  200. }
  201. #define AVALON_CTS (1 << 4)
  202. static inline bool avalon_cts(char c)
  203. {
  204. return (c & AVALON_CTS);
  205. }
  206. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  207. size_t bufsize, int timeout, int ep)
  208. {
  209. struct avalon_info *info = avalon->device_data;
  210. size_t total = 0, readsize = bufsize + 2;
  211. char readbuf[AVALON_READBUF_SIZE];
  212. int err, amount, ofs = 2, cp;
  213. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  214. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  215. avalon->drv->name, avalon->device_id, err);
  216. if (amount < 2)
  217. goto out;
  218. /* Use the fact that we're reading the status with the buffer to tell
  219. * the write thread it should send more work without needing to call
  220. * avalon_buffer_full directly. */
  221. if (avalon_cts(buf[0]))
  222. cgsem_post(&info->write_sem);
  223. /* The first 2 of every 64 bytes are status on FTDIRL */
  224. while (amount > 2) {
  225. cp = amount - 2;
  226. if (cp > 62)
  227. cp = 62;
  228. memcpy(&buf[total], &readbuf[ofs], cp);
  229. total += cp;
  230. amount -= cp + 2;
  231. ofs += 64;
  232. }
  233. out:
  234. return total;
  235. }
  236. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  237. {
  238. struct avalon_result ar;
  239. int ret, i, spare;
  240. struct avalon_task at;
  241. uint8_t *buf, *tmp;
  242. struct timespec p;
  243. /* Send reset, then check for result */
  244. avalon_init_task(&at, 1, 0,
  245. AVALON_DEFAULT_FAN_MAX_PWM,
  246. AVALON_DEFAULT_TIMEOUT,
  247. AVALON_DEFAULT_ASIC_NUM,
  248. AVALON_DEFAULT_MINER_NUM,
  249. 0, 0,
  250. AVALON_DEFAULT_FREQUENCY);
  251. wait_avalon_ready(avalon);
  252. ret = avalon_send_task(&at, avalon);
  253. if (unlikely(ret == AVA_SEND_ERROR))
  254. return -1;
  255. if (!initial) {
  256. applog(LOG_ERR, "AVA%d reset sequence sent", avalon->device_id);
  257. return 0;
  258. }
  259. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  260. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  261. /* What do these sleeps do?? */
  262. p.tv_sec = 0;
  263. p.tv_nsec = AVALON_RESET_PITCH;
  264. nanosleep(&p, NULL);
  265. /* Look for the first occurrence of 0xAA, the reset response should be:
  266. * AA 55 AA 55 00 00 00 00 00 00 */
  267. spare = ret - 10;
  268. buf = tmp = (uint8_t *)&ar;
  269. if (opt_debug) {
  270. applog(LOG_DEBUG, "AVA%d reset: get:", avalon->device_id);
  271. hexdump(tmp, AVALON_READ_SIZE);
  272. }
  273. for (i = 0; i <= spare; i++) {
  274. buf = &tmp[i];
  275. if (buf[0] == 0xAA)
  276. break;
  277. }
  278. i = 0;
  279. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  280. buf[2] == 0xAA && buf[3] == 0x55) {
  281. for (i = 4; i < 11; i++)
  282. if (buf[i] != 0)
  283. break;
  284. }
  285. if (i != 11) {
  286. applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
  287. " (%d: %02x %02x %02x %02x)", avalon->device_id,
  288. i, buf[0], buf[1], buf[2], buf[3]);
  289. /* FIXME: return 1; */
  290. } else
  291. applog(LOG_WARNING, "AVA%d: Reset succeeded",
  292. avalon->device_id);
  293. return 0;
  294. }
  295. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  296. int *asic_count, int *timeout, int *frequency)
  297. {
  298. char buf[BUFSIZ+1];
  299. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  300. size_t max;
  301. int i, tmp;
  302. if (opt_avalon_options == NULL)
  303. buf[0] = '\0';
  304. else {
  305. ptr = opt_avalon_options;
  306. for (i = 0; i < this_option_offset; i++) {
  307. comma = strchr(ptr, ',');
  308. if (comma == NULL)
  309. break;
  310. ptr = comma + 1;
  311. }
  312. comma = strchr(ptr, ',');
  313. if (comma == NULL)
  314. max = strlen(ptr);
  315. else
  316. max = comma - ptr;
  317. if (max > BUFSIZ)
  318. max = BUFSIZ;
  319. strncpy(buf, ptr, max);
  320. buf[max] = '\0';
  321. }
  322. if (!(*buf))
  323. return false;
  324. colon = strchr(buf, ':');
  325. if (colon)
  326. *(colon++) = '\0';
  327. tmp = atoi(buf);
  328. switch (tmp) {
  329. case 115200:
  330. *baud = 115200;
  331. break;
  332. case 57600:
  333. *baud = 57600;
  334. break;
  335. case 38400:
  336. *baud = 38400;
  337. break;
  338. case 19200:
  339. *baud = 19200;
  340. break;
  341. default:
  342. quit(1, "Invalid avalon-options for baud (%s) "
  343. "must be 115200, 57600, 38400 or 19200", buf);
  344. }
  345. if (colon && *colon) {
  346. colon2 = strchr(colon, ':');
  347. if (colon2)
  348. *(colon2++) = '\0';
  349. if (*colon) {
  350. tmp = atoi(colon);
  351. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  352. *miner_count = tmp;
  353. } else {
  354. quit(1, "Invalid avalon-options for "
  355. "miner_count (%s) must be 1 ~ %d",
  356. colon, AVALON_DEFAULT_MINER_NUM);
  357. }
  358. }
  359. if (colon2 && *colon2) {
  360. colon3 = strchr(colon2, ':');
  361. if (colon3)
  362. *(colon3++) = '\0';
  363. tmp = atoi(colon2);
  364. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  365. *asic_count = tmp;
  366. else {
  367. quit(1, "Invalid avalon-options for "
  368. "asic_count (%s) must be 1 ~ %d",
  369. colon2, AVALON_DEFAULT_ASIC_NUM);
  370. }
  371. if (colon3 && *colon3) {
  372. colon4 = strchr(colon3, ':');
  373. if (colon4)
  374. *(colon4++) = '\0';
  375. tmp = atoi(colon3);
  376. if (tmp > 0 && tmp <= 0xff)
  377. *timeout = tmp;
  378. else {
  379. quit(1, "Invalid avalon-options for "
  380. "timeout (%s) must be 1 ~ %d",
  381. colon3, 0xff);
  382. }
  383. if (colon4 && *colon4) {
  384. tmp = atoi(colon4);
  385. switch (tmp) {
  386. case 256:
  387. case 270:
  388. case 282:
  389. case 300:
  390. *frequency = tmp;
  391. break;
  392. default:
  393. quit(1, "Invalid avalon-options for "
  394. "frequency must be 256/270/282/300");
  395. }
  396. }
  397. }
  398. }
  399. }
  400. return true;
  401. }
  402. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  403. {
  404. int i;
  405. info->idle = true;
  406. wait_avalon_ready(avalon);
  407. /* Send idle to all miners */
  408. for (i = 0; i < info->miner_count; i++) {
  409. struct avalon_task at;
  410. if (unlikely(avalon_buffer_full(avalon)))
  411. break;
  412. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  413. info->asic_count, info->miner_count, 1, 1,
  414. info->frequency);
  415. avalon_send_task(&at, avalon);
  416. }
  417. applog(LOG_WARNING, "AVA%i: Idling %d miners", avalon->device_id, i);
  418. wait_avalon_ready(avalon);
  419. }
  420. static void avalon_initialise(struct cgpu_info *avalon)
  421. {
  422. int err, interface;
  423. if (avalon->usbinfo.nodev)
  424. return;
  425. interface = avalon->usbdev->found->interface;
  426. // Reset
  427. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  428. FTDI_VALUE_RESET, interface, C_RESET);
  429. applog(LOG_DEBUG, "%s%i: reset got err %d",
  430. avalon->drv->name, avalon->device_id, err);
  431. if (avalon->usbinfo.nodev)
  432. return;
  433. // Set latency
  434. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  435. AVALON_LATENCY, interface, C_LATENCY);
  436. applog(LOG_DEBUG, "%s%i: latency got err %d",
  437. avalon->drv->name, avalon->device_id, err);
  438. if (avalon->usbinfo.nodev)
  439. return;
  440. // Set data
  441. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  442. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  443. applog(LOG_DEBUG, "%s%i: data got err %d",
  444. avalon->drv->name, avalon->device_id, err);
  445. if (avalon->usbinfo.nodev)
  446. return;
  447. // Set the baud
  448. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  449. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  450. C_SETBAUD);
  451. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  452. avalon->drv->name, avalon->device_id, err);
  453. if (avalon->usbinfo.nodev)
  454. return;
  455. // Set Modem Control
  456. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  457. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  458. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  459. avalon->drv->name, avalon->device_id, err);
  460. if (avalon->usbinfo.nodev)
  461. return;
  462. // Set Flow Control
  463. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  464. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  465. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  466. avalon->drv->name, avalon->device_id, err);
  467. if (avalon->usbinfo.nodev)
  468. return;
  469. /* Avalon repeats the following */
  470. // Set Modem Control
  471. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  472. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  473. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  474. avalon->drv->name, avalon->device_id, err);
  475. if (avalon->usbinfo.nodev)
  476. return;
  477. // Set Flow Control
  478. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  479. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  480. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  481. avalon->drv->name, avalon->device_id, err);
  482. }
  483. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  484. {
  485. int baud, miner_count, asic_count, timeout, frequency = 0;
  486. int this_option_offset = ++option_offset;
  487. struct avalon_info *info;
  488. struct cgpu_info *avalon;
  489. bool configured;
  490. int ret;
  491. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  492. configured = get_options(this_option_offset, &baud, &miner_count,
  493. &asic_count, &timeout, &frequency);
  494. if (!usb_init(avalon, dev, found))
  495. goto shin;
  496. /* Even though this is an FTDI type chip, we want to do the parsing
  497. * all ourselves so set it to std usb type */
  498. avalon->usbdev->usb_type = USB_TYPE_STD;
  499. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  500. /* We have a real Avalon! */
  501. avalon_initialise(avalon);
  502. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  503. if (unlikely(!(avalon->device_data)))
  504. quit(1, "Failed to calloc avalon_info data");
  505. info = avalon->device_data;
  506. if (configured) {
  507. info->baud = baud;
  508. info->miner_count = miner_count;
  509. info->asic_count = asic_count;
  510. info->timeout = timeout;
  511. info->frequency = frequency;
  512. } else {
  513. info->baud = AVALON_IO_SPEED;
  514. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  515. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  516. info->timeout = AVALON_DEFAULT_TIMEOUT;
  517. info->frequency = AVALON_DEFAULT_FREQUENCY;
  518. }
  519. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  520. info->temp_max = 0;
  521. /* This is for check the temp/fan every 3~4s */
  522. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  523. if (info->temp_history_count <= 0)
  524. info->temp_history_count = 1;
  525. info->temp_history_index = 0;
  526. info->temp_sum = 0;
  527. info->temp_old = 0;
  528. if (!add_cgpu(avalon))
  529. goto unshin;
  530. ret = avalon_reset(avalon, true);
  531. if (ret && !configured)
  532. goto unshin;
  533. update_usb_stats(avalon);
  534. avalon_idle(avalon, info);
  535. applog(LOG_DEBUG, "Avalon Detected: %s "
  536. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  537. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  538. info->frequency);
  539. return true;
  540. unshin:
  541. usb_uninit(avalon);
  542. shin:
  543. free(avalon->device_data);
  544. avalon->device_data = NULL;
  545. avalon = usb_free_cgpu(avalon);
  546. return false;
  547. }
  548. static void avalon_detect(void)
  549. {
  550. usb_detect(&avalon_drv, avalon_detect_one);
  551. }
  552. static void avalon_init(struct cgpu_info *avalon)
  553. {
  554. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  555. }
  556. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  557. {
  558. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  559. (char *)ar->data, 64, 12);
  560. }
  561. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  562. struct avalon_result *ar);
  563. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  564. {
  565. if (unlikely(info->idle))
  566. return;
  567. applog(LOG_WARNING, "%s%d: No matching work - HW error",
  568. thr->cgpu->drv->name, thr->cgpu->device_id);
  569. inc_hw_errors(thr);
  570. info->no_matching_work++;
  571. }
  572. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  573. struct thr_info *thr, char *buf, int *offset)
  574. {
  575. int i, spare = *offset - AVALON_READ_SIZE;
  576. bool found = false;
  577. for (i = 0; i <= spare; i++) {
  578. struct avalon_result *ar;
  579. struct work *work;
  580. ar = (struct avalon_result *)&buf[i];
  581. work = avalon_valid_result(avalon, ar);
  582. if (work) {
  583. bool gettemp = false;
  584. found = true;
  585. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  586. mutex_lock(&info->lock);
  587. if (!info->nonces++)
  588. gettemp = true;
  589. mutex_unlock(&info->lock);
  590. }
  591. if (gettemp)
  592. avalon_update_temps(avalon, info, ar);
  593. break;
  594. }
  595. }
  596. if (!found) {
  597. spare = *offset - AVALON_READ_SIZE;
  598. /* We are buffering and haven't accumulated one more corrupt
  599. * work result. */
  600. if (spare < (int)AVALON_READ_SIZE)
  601. return;
  602. avalon_inc_nvw(info, thr);
  603. } else {
  604. spare = AVALON_READ_SIZE + i;
  605. if (i) {
  606. if (i >= (int)AVALON_READ_SIZE)
  607. avalon_inc_nvw(info, thr);
  608. else
  609. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  610. }
  611. }
  612. *offset -= spare;
  613. memmove(buf, buf + spare, *offset);
  614. }
  615. static void avalon_running_reset(struct cgpu_info *avalon,
  616. struct avalon_info *info)
  617. {
  618. avalon_reset(avalon, false);
  619. avalon_idle(avalon, info);
  620. avalon->results = 0;
  621. info->reset = false;
  622. }
  623. static void *avalon_get_results(void *userdata)
  624. {
  625. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  626. struct avalon_info *info = avalon->device_data;
  627. int offset = 0, read_delay = 0, ret = 0;
  628. const int rsize = AVALON_FTDI_READSIZE;
  629. char readbuf[AVALON_READBUF_SIZE];
  630. struct thr_info *thr = info->thr;
  631. struct timeval tv_start, tv_end;
  632. char threadname[24];
  633. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  634. RenameThread(threadname);
  635. while (likely(!avalon->shutdown)) {
  636. unsigned char buf[rsize];
  637. struct timeval tv_diff;
  638. int us_diff;
  639. if (offset >= (int)AVALON_READ_SIZE)
  640. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  641. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  642. /* This should never happen */
  643. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  644. offset = 0;
  645. }
  646. if (unlikely(info->reset)) {
  647. avalon_running_reset(avalon, info);
  648. /* Discard anything in the buffer */
  649. offset = 0;
  650. }
  651. /* As the usb read returns after just 1ms, sleep long enough
  652. * to leave the interface idle for writes to occur, but do not
  653. * sleep if we have been receiving data as more may be coming. */
  654. if (ret < 1) {
  655. cgtime(&tv_end);
  656. timersub(&tv_end, &tv_start, &tv_diff);
  657. /* Assume it has not been > 1 second so ignore tv_sec */
  658. us_diff = tv_diff.tv_usec;
  659. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  660. if (likely(read_delay >= 1000))
  661. nusleep(read_delay);
  662. }
  663. cgtime(&tv_start);
  664. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  665. C_AVALON_READ);
  666. if (ret < 1)
  667. continue;
  668. if (opt_debug) {
  669. applog(LOG_DEBUG, "Avalon: get:");
  670. hexdump((uint8_t *)buf, ret);
  671. }
  672. memcpy(&readbuf[offset], &buf, ret);
  673. offset += ret;
  674. }
  675. return NULL;
  676. }
  677. static void avalon_rotate_array(struct cgpu_info *avalon)
  678. {
  679. avalon->queued = 0;
  680. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  681. avalon->work_array = 0;
  682. }
  683. static void *avalon_send_tasks(void *userdata)
  684. {
  685. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  686. struct avalon_info *info = avalon->device_data;
  687. const int avalon_get_work_count = info->miner_count;
  688. char threadname[24];
  689. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  690. RenameThread(threadname);
  691. while (likely(!avalon->shutdown)) {
  692. int start_count, end_count, i, j, ret;
  693. struct avalon_task at;
  694. int idled = 0;
  695. while (avalon_buffer_full(avalon))
  696. cgsem_wait(&info->write_sem);
  697. mutex_lock(&info->qlock);
  698. start_count = avalon->work_array * avalon_get_work_count;
  699. end_count = start_count + avalon_get_work_count;
  700. for (i = start_count, j = 0; i < end_count; i++, j++) {
  701. if (avalon_buffer_full(avalon)) {
  702. applog(LOG_INFO,
  703. "AVA%i: Buffer full after only %d of %d work queued",
  704. avalon->device_id, j, avalon_get_work_count);
  705. break;
  706. }
  707. if (likely(j < avalon->queued)) {
  708. info->idle = false;
  709. avalon_init_task(&at, 0, 0, info->fan_pwm,
  710. info->timeout, info->asic_count,
  711. info->miner_count, 1, 0, info->frequency);
  712. avalon_create_task(&at, avalon->works[i]);
  713. } else {
  714. idled++;
  715. avalon_init_task(&at, 0, 0, info->fan_pwm,
  716. info->timeout, info->asic_count,
  717. info->miner_count, 1, 1, info->frequency);
  718. }
  719. ret = avalon_send_task(&at, avalon);
  720. if (unlikely(ret == AVA_SEND_ERROR)) {
  721. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  722. avalon->device_id);
  723. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  724. info->reset = true;
  725. break;
  726. }
  727. }
  728. avalon_rotate_array(avalon);
  729. pthread_cond_signal(&info->qcond);
  730. mutex_unlock(&info->qlock);
  731. if (unlikely(idled && !info->idle)) {
  732. info->idle = true;
  733. applog(LOG_WARNING, "AVA%i: Idled %d miners",
  734. avalon->device_id, idled);
  735. }
  736. }
  737. return NULL;
  738. }
  739. static bool avalon_prepare(struct thr_info *thr)
  740. {
  741. struct cgpu_info *avalon = thr->cgpu;
  742. struct avalon_info *info = avalon->device_data;
  743. struct timeval now;
  744. free(avalon->works);
  745. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  746. AVALON_ARRAY_SIZE);
  747. if (!avalon->works)
  748. quit(1, "Failed to calloc avalon works in avalon_prepare");
  749. info->thr = thr;
  750. mutex_init(&info->lock);
  751. mutex_init(&info->qlock);
  752. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  753. quit(1, "Failed to pthread_cond_init avalon qcond");
  754. cgsem_init(&info->write_sem);
  755. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  756. quit(1, "Failed to create avalon read_thr");
  757. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  758. quit(1, "Failed to create avalon write_thr");
  759. avalon_init(avalon);
  760. cgtime(&now);
  761. get_datestamp(avalon->init, &now);
  762. return true;
  763. }
  764. static void do_avalon_close(struct thr_info *thr)
  765. {
  766. struct cgpu_info *avalon = thr->cgpu;
  767. struct avalon_info *info = avalon->device_data;
  768. pthread_join(info->read_thr, NULL);
  769. pthread_join(info->write_thr, NULL);
  770. avalon_running_reset(avalon, info);
  771. info->no_matching_work = 0;
  772. cgsem_destroy(&info->write_sem);
  773. }
  774. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  775. {
  776. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  777. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  778. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  779. info->temp0 = ar->temp0;
  780. info->temp1 = ar->temp1;
  781. info->temp2 = ar->temp2;
  782. if (ar->temp0 & 0x80) {
  783. ar->temp0 &= 0x7f;
  784. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  785. }
  786. if (ar->temp1 & 0x80) {
  787. ar->temp1 &= 0x7f;
  788. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  789. }
  790. if (ar->temp2 & 0x80) {
  791. ar->temp2 &= 0x7f;
  792. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  793. }
  794. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  795. if (info->temp0 > info->temp_max)
  796. info->temp_max = info->temp0;
  797. if (info->temp1 > info->temp_max)
  798. info->temp_max = info->temp1;
  799. if (info->temp2 > info->temp_max)
  800. info->temp_max = info->temp2;
  801. }
  802. static inline void adjust_fan(struct avalon_info *info)
  803. {
  804. int temp_new;
  805. temp_new = info->temp_sum / info->temp_history_count;
  806. if (temp_new < 35) {
  807. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  808. info->temp_old = temp_new;
  809. } else if (temp_new > 55) {
  810. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  811. info->temp_old = temp_new;
  812. } else if (abs(temp_new - info->temp_old) >= 2) {
  813. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  814. info->temp_old = temp_new;
  815. }
  816. }
  817. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  818. struct avalon_result *ar)
  819. {
  820. record_temp_fan(info, ar, &(avalon->temp));
  821. applog(LOG_INFO,
  822. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  823. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  824. info->fan0, info->fan1, info->fan2,
  825. info->temp0, info->temp1, info->temp2, info->temp_max);
  826. info->temp_history_index++;
  827. info->temp_sum += avalon->temp;
  828. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  829. info->temp_history_index, info->temp_history_count, info->temp_old);
  830. if (info->temp_history_index == info->temp_history_count) {
  831. adjust_fan(info);
  832. info->temp_history_index = 0;
  833. info->temp_sum = 0;
  834. }
  835. }
  836. static void get_avalon_statline_before(char *buf, struct cgpu_info *avalon)
  837. {
  838. struct avalon_info *info = avalon->device_data;
  839. int lowfan = 10000;
  840. /* Find the lowest fan speed of the ASIC cooling fans. */
  841. if (info->fan1 >= 0 && info->fan1 < lowfan)
  842. lowfan = info->fan1;
  843. if (info->fan2 >= 0 && info->fan2 < lowfan)
  844. lowfan = info->fan2;
  845. tailsprintf(buf, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  846. }
  847. /* We use a replacement algorithm to only remove references to work done from
  848. * the buffer when we need the extra space for new work. */
  849. static bool avalon_fill(struct cgpu_info *avalon)
  850. {
  851. struct avalon_info *info = avalon->device_data;
  852. int subid, slot, mc;
  853. struct work *work;
  854. bool ret = true;
  855. mc = info->miner_count;
  856. mutex_lock(&info->qlock);
  857. if (avalon->queued >= mc)
  858. goto out_unlock;
  859. work = get_queued(avalon);
  860. if (unlikely(!work)) {
  861. ret = false;
  862. goto out_unlock;
  863. }
  864. subid = avalon->queued++;
  865. work->subid = subid;
  866. slot = avalon->work_array * mc + subid;
  867. if (likely(avalon->works[slot]))
  868. work_completed(avalon, avalon->works[slot]);
  869. avalon->works[slot] = work;
  870. if (avalon->queued < mc)
  871. ret = false;
  872. out_unlock:
  873. mutex_unlock(&info->qlock);
  874. return ret;
  875. }
  876. static int64_t avalon_scanhash(struct thr_info *thr)
  877. {
  878. struct cgpu_info *avalon = thr->cgpu;
  879. struct avalon_info *info = avalon->device_data;
  880. const int miner_count = info->miner_count;
  881. struct timeval now, then, tdiff;
  882. int64_t hash_count, us_timeout;
  883. struct timespec abstime;
  884. /* Half nonce range */
  885. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  886. tdiff.tv_sec = us_timeout / 1000000;
  887. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  888. cgtime(&now);
  889. timeradd(&now, &tdiff, &then);
  890. abstime.tv_sec = then.tv_sec;
  891. abstime.tv_nsec = then.tv_usec * 1000;
  892. /* Wait until avalon_send_tasks signals us that it has completed
  893. * sending its work or a full nonce range timeout has occurred */
  894. mutex_lock(&info->qlock);
  895. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  896. mutex_unlock(&info->qlock);
  897. mutex_lock(&info->lock);
  898. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  899. avalon->results += info->nonces;
  900. if (avalon->results > miner_count)
  901. avalon->results = miner_count;
  902. if (!info->idle && !info->reset)
  903. avalon->results -= miner_count / 3;
  904. else
  905. avalon->results = miner_count;
  906. info->nonces = 0;
  907. mutex_unlock(&info->lock);
  908. /* Check for nothing but consecutive bad results or consistently less
  909. * results than we should be getting and reset the FPGA if necessary */
  910. if (avalon->results < -miner_count && !info->reset) {
  911. applog(LOG_ERR, "AVA%d: Result return rate low, resetting!",
  912. avalon->device_id);
  913. info->reset = true;
  914. }
  915. if (unlikely(avalon->usbinfo.nodev)) {
  916. applog(LOG_ERR, "AVA%d: Device disappeared, shutting down thread",
  917. avalon->device_id);
  918. avalon->shutdown = true;
  919. }
  920. /* This hashmeter is just a utility counter based on returned shares */
  921. return hash_count;
  922. }
  923. static void avalon_flush_work(struct cgpu_info *avalon)
  924. {
  925. struct avalon_info *info = avalon->device_data;
  926. mutex_lock(&info->qlock);
  927. /* Will overwrite any work queued */
  928. avalon->queued = 0;
  929. pthread_cond_signal(&info->qcond);
  930. mutex_unlock(&info->qlock);
  931. }
  932. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  933. {
  934. struct api_data *root = NULL;
  935. struct avalon_info *info = cgpu->device_data;
  936. int i;
  937. root = api_add_int(root, "baud", &(info->baud), false);
  938. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  939. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  940. root = api_add_int(root, "timeout", &(info->timeout), false);
  941. root = api_add_int(root, "frequency", &(info->frequency), false);
  942. root = api_add_int(root, "fan1", &(info->fan0), false);
  943. root = api_add_int(root, "fan2", &(info->fan1), false);
  944. root = api_add_int(root, "fan3", &(info->fan2), false);
  945. root = api_add_int(root, "temp1", &(info->temp0), false);
  946. root = api_add_int(root, "temp2", &(info->temp1), false);
  947. root = api_add_int(root, "temp3", &(info->temp2), false);
  948. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  949. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  950. for (i = 0; i < info->miner_count; i++) {
  951. char mcw[24];
  952. sprintf(mcw, "match_work_count%d", i + 1);
  953. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  954. }
  955. return root;
  956. }
  957. static void avalon_shutdown(struct thr_info *thr)
  958. {
  959. do_avalon_close(thr);
  960. }
  961. struct device_drv avalon_drv = {
  962. .drv_id = DRIVER_AVALON,
  963. .dname = "avalon",
  964. .name = "AVA",
  965. .drv_detect = avalon_detect,
  966. .thread_prepare = avalon_prepare,
  967. .hash_work = hash_queued_work,
  968. .queue_full = avalon_fill,
  969. .scanwork = avalon_scanhash,
  970. .flush_work = avalon_flush_work,
  971. .get_api_stats = avalon_api_stats,
  972. .get_statline_before = get_avalon_statline_before,
  973. .reinit_device = avalon_init,
  974. .thread_shutdown = avalon_shutdown,
  975. };