driver-avalon.c 17 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (!at)
  48. return -1;
  49. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (thr) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (reset) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (first && !at->reset) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = 1;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at)
  89. {
  90. size_t ret;
  91. int full;
  92. struct timespec p;
  93. uint8_t *buf;
  94. size_t nr_len;
  95. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  96. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  97. if (!buf)
  98. return AVA_SEND_ERROR;
  99. memcpy(buf, at, AVALON_WRITE_SIZE);
  100. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  101. uint8_t tt = 0;
  102. tt = (buf[0] & 0x0f) << 4;
  103. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  104. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  105. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  106. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  107. buf[0] = tt;
  108. buf[4] = rev8(buf[4]);
  109. #endif
  110. if (opt_debug) {
  111. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  112. hexdump((uint8_t *)buf, nr_len);
  113. }
  114. ret = write(fd, buf, nr_len);
  115. free(buf);
  116. if (unlikely(ret != nr_len))
  117. return AVA_SEND_ERROR;
  118. p.tv_sec = 0;
  119. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  120. nanosleep(&p, NULL);
  121. full = avalon_buffer_full(fd);
  122. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  123. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  124. if (full == AVA_BUFFER_EMPTY)
  125. return AVA_SEND_BUFFER_EMPTY;
  126. return AVA_SEND_BUFFER_FULL;
  127. }
  128. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  129. struct thr_info *thr, struct timeval *tv_finish)
  130. {
  131. ssize_t ret = 0;
  132. int rc = 0;
  133. int read_amount = AVALON_READ_SIZE;
  134. bool first = true;
  135. /* Read reply 1 byte at a time to get earliest tv_finish */
  136. while (true) {
  137. ret = read(fd, buf, 1);
  138. if (ret < 0)
  139. return AVA_GETS_ERROR;
  140. if (first && tv_finish != NULL)
  141. gettimeofday(tv_finish, NULL);
  142. if (ret >= read_amount)
  143. return AVA_GETS_OK;
  144. if (ret > 0) {
  145. buf += ret;
  146. read_amount -= ret;
  147. first = false;
  148. continue;
  149. }
  150. rc++;
  151. if (rc >= read_count) {
  152. if (opt_debug) {
  153. applog(LOG_ERR,
  154. "Avalon: No data in %.2f seconds",
  155. (float)rc/(float)TIME_FACTOR);
  156. }
  157. return AVA_GETS_TIMEOUT;
  158. }
  159. if (thr && thr->work_restart) {
  160. if (opt_debug) {
  161. applog(LOG_ERR,
  162. "Avalon: Work restart at %.2f seconds",
  163. (float)(rc)/(float)TIME_FACTOR);
  164. }
  165. return AVA_GETS_RESTART;
  166. }
  167. }
  168. }
  169. static int avalon_get_result(int fd, struct avalon_result *ar,
  170. struct thr_info *thr, struct timeval *tv_finish)
  171. {
  172. struct cgpu_info *avalon;
  173. struct avalon_info *info;
  174. uint8_t result[AVALON_READ_SIZE];
  175. int ret, read_count = 16;
  176. if (thr) {
  177. avalon = thr->cgpu;
  178. info = avalon_info[avalon->device_id];
  179. read_count = info->read_count;
  180. }
  181. memset(result, 0, AVALON_READ_SIZE);
  182. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  183. if (ret == AVA_GETS_OK) {
  184. if (opt_debug) {
  185. applog(LOG_DEBUG, "Avalon: get:");
  186. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  187. }
  188. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  189. }
  190. return ret;
  191. }
  192. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  193. uint32_t *nonce)
  194. {
  195. int i;
  196. if (!work)
  197. return -1;
  198. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  199. if (work[i] &&
  200. !memcmp(ar->data, work[i]->data + 64, 12) &&
  201. !memcmp(ar->midstate, work[i]->midstate, 32))
  202. break;
  203. }
  204. if (i == AVALON_GET_WORK_COUNT)
  205. return -1;
  206. *nonce = ar->nonce;
  207. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  208. *nonce = swab32(*nonce);
  209. #endif
  210. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  211. return i;
  212. }
  213. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  214. {
  215. struct avalon_task at;
  216. struct avalon_result ar;
  217. uint8_t *buf;
  218. int ret, i;
  219. struct timespec p;
  220. avalon_init_task(NULL,
  221. &at, 1, 0,
  222. AVALON_DEFAULT_FAN_PWM,
  223. timeout_p, asic_num_p, miner_num_p);
  224. ret = avalon_send_task(fd, &at);
  225. if (ret == AVA_SEND_ERROR)
  226. return 1;
  227. avalon_get_result(fd, &ar, NULL, NULL);
  228. buf = (uint8_t *)&ar;
  229. for (i = 0; i < 11; i++)
  230. if (buf[i] != 0)
  231. break;
  232. /* FIXME: add more avalon info base on return */
  233. if (i != 11) {
  234. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  235. return 1;
  236. }
  237. p.tv_sec = 1;
  238. p.tv_nsec = AVALON_RESET_PITCH;
  239. nanosleep(&p, NULL);
  240. applog(LOG_ERR, "Avalon: Reset succeeded");
  241. return 0;
  242. }
  243. static void do_avalon_close(struct thr_info *thr)
  244. {
  245. struct cgpu_info *avalon = thr->cgpu;
  246. avalon_close(avalon->device_fd);
  247. avalon->device_fd = -1;
  248. /* FIXME: we should free the bulk0/1/2 */
  249. }
  250. static void set_timing_mode(struct cgpu_info *avalon)
  251. {
  252. struct avalon_info *info = avalon_info[avalon->device_id];
  253. /* Anything else in buf just uses DEFAULT mode */
  254. info->Hs = AVALON_HASH_TIME;
  255. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  256. info->read_count =
  257. (int)(info->fullnonce * TIME_FACTOR) - 1;
  258. }
  259. static void get_options(int this_option_offset, int *baud, int *miner_count,
  260. int *asic_count, int *timeout)
  261. {
  262. char err_buf[BUFSIZ+1];
  263. char buf[BUFSIZ+1];
  264. char *ptr, *comma, *colon, *colon2, *colon3;
  265. size_t max;
  266. int i, tmp;
  267. if (opt_avalon_options == NULL)
  268. buf[0] = '\0';
  269. else {
  270. ptr = opt_avalon_options;
  271. for (i = 0; i < this_option_offset; i++) {
  272. comma = strchr(ptr, ',');
  273. if (comma == NULL)
  274. break;
  275. ptr = comma + 1;
  276. }
  277. comma = strchr(ptr, ',');
  278. if (comma == NULL)
  279. max = strlen(ptr);
  280. else
  281. max = comma - ptr;
  282. if (max > BUFSIZ)
  283. max = BUFSIZ;
  284. strncpy(buf, ptr, max);
  285. buf[max] = '\0';
  286. }
  287. *baud = AVALON_IO_SPEED;
  288. *miner_count = AVALON_DEFAULT_MINER_NUM;
  289. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  290. *timeout = AVALON_DEFAULT_TIMEOUT;
  291. if (!(*buf))
  292. return;
  293. colon = strchr(buf, ':');
  294. if (colon)
  295. *(colon++) = '\0';
  296. tmp = atoi(buf);
  297. switch (tmp) {
  298. case 115200:
  299. *baud = 115200;
  300. break;
  301. case 57600:
  302. *baud = 57600;
  303. break;
  304. case 19200:
  305. *baud = 19200;
  306. break;
  307. default:
  308. sprintf(err_buf,
  309. "Invalid avalon-options for baud (%s) "
  310. "must be 115200, 57600 or 19200", buf);
  311. quit(1, err_buf);
  312. }
  313. if (colon && *colon) {
  314. colon2 = strchr(colon, ':');
  315. if (colon2)
  316. *(colon2++) = '\0';
  317. if (*colon) {
  318. tmp = atoi(colon);
  319. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  320. *miner_count = tmp;
  321. } else {
  322. sprintf(err_buf,
  323. "Invalid avalon-options for "
  324. "miner_count (%s) must be 1 ~ %d",
  325. colon, AVALON_DEFAULT_MINER_NUM);
  326. quit(1, err_buf);
  327. }
  328. }
  329. if (colon2 && *colon2) {
  330. colon3 = strchr(colon2, ':');
  331. if (colon3)
  332. *(colon3++) = '\0';
  333. tmp = atoi(colon2);
  334. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  335. *asic_count = tmp;
  336. else {
  337. sprintf(err_buf,
  338. "Invalid avalon-options for "
  339. "asic_count (%s) must be 1 ~ %d",
  340. colon2, AVALON_DEFAULT_ASIC_NUM);
  341. quit(1, err_buf);
  342. }
  343. if (colon3 && *colon3) {
  344. tmp = atoi(colon3);
  345. if (tmp > 0 && tmp <= 0xff)
  346. *timeout = tmp;
  347. else {
  348. sprintf(err_buf,
  349. "Invalid avalon-options for "
  350. "timeout (%s) must be 1 ~ %d",
  351. colon3, 0xff);
  352. quit(1, err_buf);
  353. }
  354. }
  355. }
  356. }
  357. }
  358. static bool avalon_detect_one(const char *devpath)
  359. {
  360. struct avalon_info *info;
  361. int fd, ret;
  362. int baud, miner_count, asic_count, timeout;
  363. int this_option_offset = ++option_offset;
  364. get_options(this_option_offset, &baud, &miner_count, &asic_count, &timeout);
  365. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  366. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  367. devpath, baud, miner_count, asic_count, timeout);
  368. fd = avalon_open2(devpath, baud, true);
  369. if (unlikely(fd == -1)) {
  370. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  371. return false;
  372. }
  373. ret = avalon_reset(fd, timeout, asic_count, miner_count);
  374. avalon_close(fd);
  375. if (ret)
  376. return false;
  377. /* We have a real Avalon! */
  378. struct cgpu_info *avalon;
  379. avalon = calloc(1, sizeof(struct cgpu_info));
  380. avalon->api = &avalon_api;
  381. avalon->device_path = strdup(devpath);
  382. avalon->device_fd = -1;
  383. avalon->threads = AVALON_MINER_THREADS;
  384. add_cgpu(avalon);
  385. avalon_info = realloc(avalon_info,
  386. sizeof(struct avalon_info *) *
  387. (total_devices + 1));
  388. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  389. devpath, avalon->device_id);
  390. avalon_info[avalon->device_id] = (struct avalon_info *)
  391. malloc(sizeof(struct avalon_info));
  392. if (unlikely(!(avalon_info[avalon->device_id])))
  393. quit(1, "Failed to malloc avalon_info");
  394. info = avalon_info[avalon->device_id];
  395. memset(info, 0, sizeof(struct avalon_info));
  396. info->baud = baud;
  397. info->miner_count = miner_count;
  398. info->asic_count = asic_count;
  399. info->timeout = timeout;
  400. set_timing_mode(avalon);
  401. return true;
  402. }
  403. static inline void avalon_detect()
  404. {
  405. serial_detect(&avalon_api, avalon_detect_one);
  406. }
  407. static bool avalon_prepare(struct thr_info *thr)
  408. {
  409. struct cgpu_info *avalon = thr->cgpu;
  410. struct timeval now;
  411. int fd, ret;
  412. struct avalon_info *info = avalon_info[avalon->device_id];
  413. avalon->device_fd = -1;
  414. fd = avalon_open(avalon->device_path,
  415. avalon_info[avalon->device_id]->baud);
  416. if (unlikely(fd == -1)) {
  417. applog(LOG_ERR, "Avalon: Failed to open on %s",
  418. avalon->device_path);
  419. return false;
  420. }
  421. ret = avalon_reset(fd, info->timeout, info->asic_count, info->miner_count);
  422. if (ret)
  423. return false;
  424. avalon->device_fd = fd;
  425. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  426. gettimeofday(&now, NULL);
  427. get_datestamp(avalon->init, &now);
  428. return true;
  429. }
  430. static void avalon_free_work(struct work **work)
  431. {
  432. int i;
  433. if (!work)
  434. return;
  435. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  436. if (work[i]) {
  437. free_work(work[i]);
  438. work[i] = NULL;
  439. }
  440. }
  441. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  442. __maybe_unused int64_t max_nonce)
  443. {
  444. struct cgpu_info *avalon;
  445. int fd;
  446. int ret;
  447. int full;
  448. struct avalon_info *info;
  449. struct avalon_task at;
  450. struct avalon_result ar;
  451. static struct work *bulk0[3] = {NULL, NULL, NULL};
  452. static struct work *bulk1[3] = {NULL, NULL, NULL};
  453. static struct work *bulk2[3] = {NULL, NULL, NULL};
  454. struct work **work = NULL;
  455. int i, work_i0, work_i1, work_i2;
  456. uint32_t nonce;
  457. int64_t hash_count;
  458. struct timeval tv_start, tv_finish, elapsed;
  459. int curr_hw_errors;
  460. bool was_hw_error;
  461. int64_t estimate_hashes;
  462. avalon = thr->cgpu;
  463. info = avalon_info[avalon->device_id];
  464. if (avalon->device_fd == -1)
  465. if (!avalon_prepare(thr)) {
  466. applog(LOG_ERR, "AVA%i: Comms error",
  467. avalon->device_id);
  468. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  469. /* fail the device if the reopen attempt fails */
  470. return -1;
  471. }
  472. fd = avalon->device_fd;
  473. #ifndef WIN32
  474. tcflush(fd, TCOFLUSH);
  475. #endif
  476. work = bulk_work;
  477. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  478. bulk0[i] = bulk1[i];
  479. bulk1[i] = bulk2[i];
  480. bulk2[i] = work[i];
  481. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  482. i, bulk0[i], bulk1[i], bulk2[i]);
  483. }
  484. i = 0;
  485. while (true) {
  486. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  487. avalon_create_task(&at, work[i]);
  488. ret = avalon_send_task(fd, &at);
  489. if (ret == AVA_SEND_ERROR) {
  490. avalon_free_work(bulk0);
  491. avalon_free_work(bulk1);
  492. avalon_free_work(bulk2);
  493. do_avalon_close(thr);
  494. applog(LOG_ERR, "AVA%i: Comms error",
  495. avalon->device_id);
  496. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  497. sleep(1);
  498. return 0; /* This should never happen */
  499. }
  500. work[i]->blk.nonce = 0xffffffff;
  501. if (ret == AVA_SEND_BUFFER_FULL)
  502. break;
  503. i++;
  504. if (i == AVALON_GET_WORK_COUNT &&
  505. ret != AVA_SEND_BUFFER_FULL) {
  506. return 0xffffffff;
  507. }
  508. }
  509. elapsed.tv_sec = elapsed.tv_usec = 0;
  510. gettimeofday(&tv_start, NULL);
  511. while(true) {
  512. full = avalon_buffer_full(fd);
  513. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  514. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  515. if (full == AVA_BUFFER_EMPTY)
  516. break;
  517. work_i0 = work_i1 = work_i2 = -1;
  518. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  519. if (ret == AVA_GETS_ERROR) {
  520. avalon_free_work(bulk0);
  521. avalon_free_work(bulk1);
  522. avalon_free_work(bulk2);
  523. do_avalon_close(thr);
  524. applog(LOG_ERR,
  525. "AVA%i: Comms error", avalon->device_id);
  526. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  527. return 0;
  528. }
  529. /* aborted before becoming idle, get new work */
  530. if (ret == AVA_GETS_TIMEOUT) {
  531. timersub(&tv_finish, &tv_start, &elapsed);
  532. estimate_hashes = ((double)(elapsed.tv_sec) +
  533. ((double)(elapsed.tv_usec)) /
  534. ((double)1000000)) / info->Hs;
  535. /* If Serial-USB delay allowed the full nonce range to
  536. * complete it can't have done more than a full nonce
  537. */
  538. if (unlikely(estimate_hashes > 0xffffffff))
  539. estimate_hashes = 0xffffffff;
  540. applog(LOG_DEBUG,
  541. "Avalon: no nonce = 0x%08llx hashes "
  542. "(%ld.%06lds)",
  543. estimate_hashes, elapsed.tv_sec,
  544. elapsed.tv_usec);
  545. continue;
  546. }
  547. if (ret == AVA_GETS_RESTART) {
  548. avalon_free_work(bulk0);
  549. avalon_free_work(bulk1);
  550. avalon_free_work(bulk2);
  551. continue;
  552. }
  553. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  554. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  555. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  556. curr_hw_errors = avalon->hw_errors;
  557. if (work_i0 >= 0)
  558. submit_nonce(thr, bulk0[work_i0], nonce);
  559. if (work_i1 >= 0)
  560. submit_nonce(thr, bulk1[work_i1], nonce);
  561. if (work_i2 >= 0)
  562. submit_nonce(thr, bulk2[work_i2], nonce);
  563. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  564. /* Force a USB close/reopen on any hw error */
  565. if (was_hw_error)
  566. do_avalon_close(thr);
  567. hash_count = nonce;
  568. hash_count++;
  569. hash_count *= info->asic_count;
  570. }
  571. avalon_free_work(bulk0);
  572. if (opt_debug) {
  573. timersub(&tv_finish, &tv_start, &elapsed);
  574. applog(LOG_DEBUG,
  575. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  576. "(%ld.%06lds)",
  577. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  578. }
  579. return hash_count;
  580. }
  581. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  582. {
  583. struct api_data *root = NULL;
  584. struct avalon_info *info = avalon_info[cgpu->device_id];
  585. /* Warning, access to these is not locked - but we don't really
  586. * care since hashing performance is way more important than
  587. * locking access to displaying API debug 'stats'
  588. * If locking becomes an issue for any of them, use copy_data=true also */
  589. root = api_add_int(root, "read_count", &(info->read_count), false);
  590. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  591. root = api_add_int(root, "baud", &(info->baud), false);
  592. root = api_add_int(root, "miner_count", &(info->miner_count),
  593. false);
  594. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  595. return root;
  596. }
  597. static void avalon_shutdown(struct thr_info *thr)
  598. {
  599. do_avalon_close(thr);
  600. }
  601. struct device_api avalon_api = {
  602. .dname = "avalon",
  603. .name = "AVA",
  604. .api_detect = avalon_detect,
  605. .thread_prepare = avalon_prepare,
  606. .scanhash_queue = avalon_scanhash,
  607. .get_api_stats = avalon_api_stats,
  608. .thread_shutdown = avalon_shutdown,
  609. };