driver-avalon.c 38 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  41. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  42. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  43. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  44. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  45. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  46. bool opt_avalon_auto;
  47. static int option_offset = -1;
  48. struct device_drv avalon_drv;
  49. static int avalon_init_task(struct avalon_task *at,
  50. uint8_t reset, uint8_t ff, uint8_t fan,
  51. uint8_t timeout, uint8_t asic_num,
  52. uint8_t miner_num, uint8_t nonce_elf,
  53. uint8_t gate_miner, int frequency)
  54. {
  55. uint16_t *lefreq16;
  56. uint8_t *buf;
  57. static bool first = true;
  58. if (unlikely(!at))
  59. return -1;
  60. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  61. return -1;
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (unlikely(reset)) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (unlikely(first && !at->reset)) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = nonce_elf;
  81. at->gate_miner_elf = 1;
  82. at->asic_pll = 1;
  83. if (unlikely(gate_miner)) {
  84. at-> gate_miner = 1;
  85. at->asic_pll = 0;
  86. }
  87. buf = (uint8_t *)at;
  88. buf[5] = 0x00;
  89. buf[8] = 0x74;
  90. buf[9] = 0x01;
  91. buf[10] = 0x00;
  92. buf[11] = 0x00;
  93. lefreq16 = (uint16_t *)&buf[6];
  94. *lefreq16 = htole16(frequency * 8);
  95. return 0;
  96. }
  97. static inline void avalon_create_task(struct avalon_task *at,
  98. struct work *work)
  99. {
  100. memcpy(at->midstate, work->midstate, 32);
  101. memcpy(at->data, work->data + 64, 12);
  102. }
  103. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  104. {
  105. int err, amount;
  106. err = usb_write(avalon, buf, len, &amount, ep);
  107. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  108. avalon->device_id, err);
  109. if (unlikely(err != 0)) {
  110. applog(LOG_WARNING, "usb_write error on avalon_write");
  111. return AVA_SEND_ERROR;
  112. }
  113. if (amount != len) {
  114. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  115. return AVA_SEND_ERROR;
  116. }
  117. return AVA_SEND_OK;
  118. }
  119. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  120. {
  121. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  122. int delay, ret, i, ep = C_AVALON_TASK;
  123. struct avalon_info *info;
  124. uint32_t nonce_range;
  125. size_t nr_len;
  126. if (at->nonce_elf)
  127. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  128. else
  129. nr_len = AVALON_WRITE_SIZE;
  130. memcpy(buf, at, AVALON_WRITE_SIZE);
  131. if (at->nonce_elf) {
  132. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  133. for (i = 0; i < at->asic_num; i++) {
  134. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  135. (i * nonce_range & 0xff000000) >> 24;
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  137. (i * nonce_range & 0x00ff0000) >> 16;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  139. (i * nonce_range & 0x0000ff00) >> 8;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  141. (i * nonce_range & 0x000000ff) >> 0;
  142. }
  143. }
  144. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  145. uint8_t tt = 0;
  146. tt = (buf[0] & 0x0f) << 4;
  147. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  148. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  149. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  150. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  151. buf[0] = tt;
  152. tt = (buf[4] & 0x0f) << 4;
  153. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  154. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  155. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  156. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  157. buf[4] = tt;
  158. #endif
  159. info = avalon->device_data;
  160. delay = nr_len * 10 * 1000000;
  161. delay = delay / info->baud;
  162. if (at->reset) {
  163. ep = C_AVALON_RESET;
  164. nr_len = 1;
  165. }
  166. if (opt_debug) {
  167. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  168. hexdump(buf, nr_len);
  169. }
  170. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  171. delay += 4000;
  172. nusleep(delay);
  173. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  174. return ret;
  175. }
  176. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  177. struct avalon_info *info, struct avalon_result *ar,
  178. struct work *work)
  179. {
  180. uint32_t nonce;
  181. info = avalon->device_data;
  182. info->matching_work[work->subid]++;
  183. nonce = htole32(ar->nonce);
  184. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  185. return submit_nonce(thr, work, nonce);
  186. }
  187. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  188. static void wait_avalon_ready(struct cgpu_info *avalon)
  189. {
  190. while (avalon_buffer_full(avalon)) {
  191. nmsleep(40);
  192. }
  193. }
  194. #define AVALON_CTS (1 << 4)
  195. static inline bool avalon_cts(char c)
  196. {
  197. return (c & AVALON_CTS);
  198. }
  199. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  200. size_t bufsize, int timeout, int ep)
  201. {
  202. struct avalon_info *info = avalon->device_data;
  203. size_t total = 0, readsize = bufsize + 2;
  204. char readbuf[AVALON_READBUF_SIZE];
  205. int err, amount, ofs = 2, cp;
  206. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  207. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  208. avalon->drv->name, avalon->device_id, err);
  209. if (amount < 2)
  210. goto out;
  211. /* The first 2 of every 64 bytes are status on FTDIRL */
  212. while (amount > 2) {
  213. cp = amount - 2;
  214. if (cp > 62)
  215. cp = 62;
  216. memcpy(&buf[total], &readbuf[ofs], cp);
  217. total += cp;
  218. amount -= cp + 2;
  219. ofs += 64;
  220. }
  221. out:
  222. return total;
  223. }
  224. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  225. {
  226. struct avalon_result ar;
  227. int ret, i, spare;
  228. struct avalon_task at;
  229. uint8_t *buf, *tmp;
  230. struct timespec p;
  231. /* Send reset, then check for result */
  232. avalon_init_task(&at, 1, 0,
  233. AVALON_DEFAULT_FAN_MAX_PWM,
  234. AVALON_DEFAULT_TIMEOUT,
  235. AVALON_DEFAULT_ASIC_NUM,
  236. AVALON_DEFAULT_MINER_NUM,
  237. 0, 0,
  238. AVALON_DEFAULT_FREQUENCY);
  239. wait_avalon_ready(avalon);
  240. ret = avalon_send_task(&at, avalon);
  241. if (unlikely(ret == AVA_SEND_ERROR))
  242. return -1;
  243. if (!initial) {
  244. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  245. return 0;
  246. }
  247. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  248. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  249. /* What do these sleeps do?? */
  250. p.tv_sec = 0;
  251. p.tv_nsec = AVALON_RESET_PITCH;
  252. nanosleep(&p, NULL);
  253. /* Look for the first occurrence of 0xAA, the reset response should be:
  254. * AA 55 AA 55 00 00 00 00 00 00 */
  255. spare = ret - 10;
  256. buf = tmp = (uint8_t *)&ar;
  257. if (opt_debug) {
  258. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  259. hexdump(tmp, AVALON_READ_SIZE);
  260. }
  261. for (i = 0; i <= spare; i++) {
  262. buf = &tmp[i];
  263. if (buf[0] == 0xAA)
  264. break;
  265. }
  266. i = 0;
  267. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  268. buf[2] == 0xAA && buf[3] == 0x55) {
  269. for (i = 4; i < 11; i++)
  270. if (buf[i] != 0)
  271. break;
  272. }
  273. if (i != 11) {
  274. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  275. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  276. i, buf[0], buf[1], buf[2], buf[3]);
  277. /* FIXME: return 1; */
  278. } else
  279. applog(LOG_WARNING, "%s%d: Reset succeeded",
  280. avalon->drv->name, avalon->device_id);
  281. return 0;
  282. }
  283. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  284. int *asic_count, int *timeout, int *frequency)
  285. {
  286. char buf[BUFSIZ+1];
  287. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  288. size_t max;
  289. int i, tmp;
  290. if (opt_avalon_options == NULL)
  291. buf[0] = '\0';
  292. else {
  293. ptr = opt_avalon_options;
  294. for (i = 0; i < this_option_offset; i++) {
  295. comma = strchr(ptr, ',');
  296. if (comma == NULL)
  297. break;
  298. ptr = comma + 1;
  299. }
  300. comma = strchr(ptr, ',');
  301. if (comma == NULL)
  302. max = strlen(ptr);
  303. else
  304. max = comma - ptr;
  305. if (max > BUFSIZ)
  306. max = BUFSIZ;
  307. strncpy(buf, ptr, max);
  308. buf[max] = '\0';
  309. }
  310. if (!(*buf))
  311. return false;
  312. colon = strchr(buf, ':');
  313. if (colon)
  314. *(colon++) = '\0';
  315. tmp = atoi(buf);
  316. switch (tmp) {
  317. case 115200:
  318. *baud = 115200;
  319. break;
  320. case 57600:
  321. *baud = 57600;
  322. break;
  323. case 38400:
  324. *baud = 38400;
  325. break;
  326. case 19200:
  327. *baud = 19200;
  328. break;
  329. default:
  330. quit(1, "Invalid avalon-options for baud (%s) "
  331. "must be 115200, 57600, 38400 or 19200", buf);
  332. }
  333. if (colon && *colon) {
  334. colon2 = strchr(colon, ':');
  335. if (colon2)
  336. *(colon2++) = '\0';
  337. if (*colon) {
  338. tmp = atoi(colon);
  339. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  340. *miner_count = tmp;
  341. } else {
  342. quit(1, "Invalid avalon-options for "
  343. "miner_count (%s) must be 1 ~ %d",
  344. colon, AVALON_DEFAULT_MINER_NUM);
  345. }
  346. }
  347. if (colon2 && *colon2) {
  348. colon3 = strchr(colon2, ':');
  349. if (colon3)
  350. *(colon3++) = '\0';
  351. tmp = atoi(colon2);
  352. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  353. *asic_count = tmp;
  354. else {
  355. quit(1, "Invalid avalon-options for "
  356. "asic_count (%s) must be 1 ~ %d",
  357. colon2, AVALON_DEFAULT_ASIC_NUM);
  358. }
  359. if (colon3 && *colon3) {
  360. colon4 = strchr(colon3, ':');
  361. if (colon4)
  362. *(colon4++) = '\0';
  363. tmp = atoi(colon3);
  364. if (tmp > 0 && tmp <= 0xff)
  365. *timeout = tmp;
  366. else {
  367. quit(1, "Invalid avalon-options for "
  368. "timeout (%s) must be 1 ~ %d",
  369. colon3, 0xff);
  370. }
  371. if (colon4 && *colon4) {
  372. tmp = atoi(colon4);
  373. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  374. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  375. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  376. }
  377. *frequency = tmp;
  378. }
  379. }
  380. }
  381. }
  382. return true;
  383. }
  384. char *set_avalon_fan(char *arg)
  385. {
  386. int val1, val2, ret;
  387. ret = sscanf(arg, "%d-%d", &val1, &val2);
  388. if (ret < 1)
  389. return "No values passed to avalon-fan";
  390. if (ret == 1)
  391. val2 = val1;
  392. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  393. return "Invalid value passed to avalon-fan";
  394. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  395. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  396. return NULL;
  397. }
  398. char *set_avalon_freq(char *arg)
  399. {
  400. int val1, val2, ret;
  401. ret = sscanf(arg, "%d-%d", &val1, &val2);
  402. if (ret < 1)
  403. return "No values passed to avalon-freq";
  404. if (ret == 1)
  405. val2 = val1;
  406. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  407. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  408. val2 < val1)
  409. return "Invalid value passed to avalon-freq";
  410. opt_avalon_freq_min = val1;
  411. opt_avalon_freq_max = val2;
  412. return NULL;
  413. }
  414. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  415. {
  416. int i;
  417. wait_avalon_ready(avalon);
  418. /* Send idle to all miners */
  419. for (i = 0; i < info->miner_count; i++) {
  420. struct avalon_task at;
  421. if (unlikely(avalon_buffer_full(avalon)))
  422. break;
  423. info->idle++;
  424. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  425. info->asic_count, info->miner_count, 1, 1,
  426. info->frequency);
  427. avalon_send_task(&at, avalon);
  428. }
  429. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  430. wait_avalon_ready(avalon);
  431. }
  432. static void avalon_initialise(struct cgpu_info *avalon)
  433. {
  434. int err, interface;
  435. if (avalon->usbinfo.nodev)
  436. return;
  437. interface = avalon->usbdev->found->interface;
  438. // Reset
  439. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  440. FTDI_VALUE_RESET, interface, C_RESET);
  441. applog(LOG_DEBUG, "%s%i: reset got err %d",
  442. avalon->drv->name, avalon->device_id, err);
  443. if (avalon->usbinfo.nodev)
  444. return;
  445. // Set latency
  446. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  447. AVALON_LATENCY, interface, C_LATENCY);
  448. applog(LOG_DEBUG, "%s%i: latency got err %d",
  449. avalon->drv->name, avalon->device_id, err);
  450. if (avalon->usbinfo.nodev)
  451. return;
  452. // Set data
  453. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  454. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  455. applog(LOG_DEBUG, "%s%i: data got err %d",
  456. avalon->drv->name, avalon->device_id, err);
  457. if (avalon->usbinfo.nodev)
  458. return;
  459. // Set the baud
  460. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  461. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  462. C_SETBAUD);
  463. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  464. avalon->drv->name, avalon->device_id, err);
  465. if (avalon->usbinfo.nodev)
  466. return;
  467. // Set Modem Control
  468. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  469. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  470. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  471. avalon->drv->name, avalon->device_id, err);
  472. if (avalon->usbinfo.nodev)
  473. return;
  474. // Set Flow Control
  475. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  476. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  477. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  478. avalon->drv->name, avalon->device_id, err);
  479. if (avalon->usbinfo.nodev)
  480. return;
  481. /* Avalon repeats the following */
  482. // Set Modem Control
  483. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  484. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  485. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  486. avalon->drv->name, avalon->device_id, err);
  487. if (avalon->usbinfo.nodev)
  488. return;
  489. // Set Flow Control
  490. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  491. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  492. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  493. avalon->drv->name, avalon->device_id, err);
  494. }
  495. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  496. {
  497. uint8_t buf[2];
  498. int err;
  499. if (usb_ident(avalon) == IDENT_BTB) {
  500. buf[0] = (uint8_t)core_voltage;
  501. buf[1] = (uint8_t)(core_voltage >> 8);
  502. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  503. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  504. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  505. if (unlikely(err < 0)) {
  506. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  507. avalon->drv->name, avalon->device_id, err);
  508. return false;
  509. } else {
  510. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  511. avalon->drv->name, avalon->device_id,
  512. core_voltage);
  513. }
  514. return true;
  515. }
  516. return false;
  517. }
  518. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  519. {
  520. uint8_t buf[2];
  521. int err;
  522. int amount;
  523. if (usb_ident(avalon) == IDENT_BTB) {
  524. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  525. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  526. (char *)buf, sizeof(buf), &amount,
  527. C_BB_GET_VOLTAGE);
  528. if (unlikely(err != 0 || amount != 2)) {
  529. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  530. avalon->drv->name, avalon->device_id, err, amount);
  531. return 0;
  532. } else {
  533. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  534. }
  535. } else {
  536. return 0;
  537. }
  538. }
  539. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  540. {
  541. int baud, uninitialised_var(miner_count), uninitialised_var(asic_count),
  542. uninitialised_var(timeout), frequency = 0;
  543. int this_option_offset = ++option_offset;
  544. struct avalon_info *info;
  545. struct cgpu_info *avalon;
  546. bool configured;
  547. int ret;
  548. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  549. configured = get_options(this_option_offset, &baud, &miner_count,
  550. &asic_count, &timeout, &frequency);
  551. if (!usb_init(avalon, dev, found))
  552. goto shin;
  553. /* Even though this is an FTDI type chip, we want to do the parsing
  554. * all ourselves so set it to std usb type */
  555. avalon->usbdev->usb_type = USB_TYPE_STD;
  556. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  557. /* We have a real Avalon! */
  558. avalon_initialise(avalon);
  559. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  560. if (unlikely(!(avalon->device_data)))
  561. quit(1, "Failed to calloc avalon_info data");
  562. info = avalon->device_data;
  563. if (configured) {
  564. info->baud = baud;
  565. info->miner_count = miner_count;
  566. info->asic_count = asic_count;
  567. info->timeout = timeout;
  568. info->frequency = frequency;
  569. } else {
  570. info->baud = AVALON_IO_SPEED;
  571. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  572. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  573. info->timeout = AVALON_DEFAULT_TIMEOUT;
  574. info->frequency = AVALON_DEFAULT_FREQUENCY;
  575. }
  576. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  577. info->temp_max = 0;
  578. /* This is for check the temp/fan every 3~4s */
  579. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  580. if (info->temp_history_count <= 0)
  581. info->temp_history_count = 1;
  582. info->temp_history_index = 0;
  583. info->temp_sum = 0;
  584. info->temp_old = 0;
  585. if (!add_cgpu(avalon))
  586. goto unshin;
  587. cgsem_init(&info->write_sem);
  588. ret = avalon_reset(avalon, true);
  589. if (ret && !configured)
  590. goto unshinsem;
  591. update_usb_stats(avalon);
  592. avalon_idle(avalon, info);
  593. applog(LOG_DEBUG, "Avalon Detected: %s "
  594. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  595. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  596. info->frequency);
  597. if (usb_ident(avalon) == IDENT_BTB) {
  598. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  599. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  600. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  601. opt_bitburner_core_voltage,
  602. BITBURNER_MIN_COREMV,
  603. BITBURNER_MAX_COREMV);
  604. } else
  605. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  606. }
  607. return true;
  608. unshinsem:
  609. cgsem_destroy(&info->write_sem);
  610. unshin:
  611. usb_uninit(avalon);
  612. shin:
  613. free(avalon->device_data);
  614. avalon->device_data = NULL;
  615. avalon = usb_free_cgpu(avalon);
  616. return false;
  617. }
  618. static void avalon_detect(void)
  619. {
  620. usb_detect(&avalon_drv, avalon_detect_one);
  621. }
  622. static void avalon_init(struct cgpu_info *avalon)
  623. {
  624. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  625. }
  626. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  627. {
  628. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  629. (char *)ar->data, 64, 12);
  630. }
  631. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  632. struct avalon_result *ar);
  633. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  634. {
  635. applog(LOG_INFO, "%s%d: No matching work - HW error",
  636. thr->cgpu->drv->name, thr->cgpu->device_id);
  637. inc_hw_errors(thr);
  638. info->no_matching_work++;
  639. }
  640. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  641. struct thr_info *thr, char *buf, int *offset)
  642. {
  643. int i, spare = *offset - AVALON_READ_SIZE;
  644. bool found = false;
  645. for (i = 0; i <= spare; i++) {
  646. struct avalon_result *ar;
  647. struct work *work;
  648. ar = (struct avalon_result *)&buf[i];
  649. work = avalon_valid_result(avalon, ar);
  650. if (work) {
  651. bool gettemp = false;
  652. found = true;
  653. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  654. mutex_lock(&info->lock);
  655. if (!info->nonces++)
  656. gettemp = true;
  657. info->auto_nonces++;
  658. mutex_unlock(&info->lock);
  659. } else if (opt_avalon_auto) {
  660. mutex_lock(&info->lock);
  661. info->auto_hw++;
  662. mutex_unlock(&info->lock);
  663. }
  664. if (gettemp)
  665. avalon_update_temps(avalon, info, ar);
  666. break;
  667. }
  668. }
  669. if (!found) {
  670. spare = *offset - AVALON_READ_SIZE;
  671. /* We are buffering and haven't accumulated one more corrupt
  672. * work result. */
  673. if (spare < (int)AVALON_READ_SIZE)
  674. return;
  675. avalon_inc_nvw(info, thr);
  676. } else {
  677. spare = AVALON_READ_SIZE + i;
  678. if (i) {
  679. if (i >= (int)AVALON_READ_SIZE)
  680. avalon_inc_nvw(info, thr);
  681. else
  682. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  683. }
  684. }
  685. *offset -= spare;
  686. memmove(buf, buf + spare, *offset);
  687. }
  688. static void avalon_running_reset(struct cgpu_info *avalon,
  689. struct avalon_info *info)
  690. {
  691. avalon_reset(avalon, false);
  692. avalon_idle(avalon, info);
  693. avalon->results = 0;
  694. info->reset = false;
  695. }
  696. static void *avalon_get_results(void *userdata)
  697. {
  698. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  699. struct avalon_info *info = avalon->device_data;
  700. int offset = 0, read_delay = 0, ret = 0;
  701. const int rsize = AVALON_FTDI_READSIZE;
  702. char readbuf[AVALON_READBUF_SIZE];
  703. struct thr_info *thr = info->thr;
  704. struct timeval tv_start, tv_end;
  705. char threadname[24];
  706. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  707. RenameThread(threadname);
  708. while (likely(!avalon->shutdown)) {
  709. unsigned char buf[rsize];
  710. struct timeval tv_diff;
  711. int us_diff;
  712. if (offset >= (int)AVALON_READ_SIZE)
  713. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  714. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  715. /* This should never happen */
  716. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  717. offset = 0;
  718. }
  719. if (unlikely(info->reset)) {
  720. avalon_running_reset(avalon, info);
  721. /* Discard anything in the buffer */
  722. offset = 0;
  723. }
  724. /* As the usb read returns after just 1ms, sleep long enough
  725. * to leave the interface idle for writes to occur, but do not
  726. * sleep if we have been receiving data as more may be coming. */
  727. if (ret < 1) {
  728. cgtime(&tv_end);
  729. timersub(&tv_end, &tv_start, &tv_diff);
  730. /* Assume it has not been > 1 second so ignore tv_sec */
  731. us_diff = tv_diff.tv_usec;
  732. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  733. if (likely(read_delay >= 1000))
  734. nusleep(read_delay);
  735. }
  736. cgtime(&tv_start);
  737. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  738. C_AVALON_READ);
  739. if (ret < 1)
  740. continue;
  741. if (opt_debug) {
  742. applog(LOG_DEBUG, "Avalon: get:");
  743. hexdump((uint8_t *)buf, ret);
  744. }
  745. memcpy(&readbuf[offset], &buf, ret);
  746. offset += ret;
  747. }
  748. return NULL;
  749. }
  750. static void avalon_rotate_array(struct cgpu_info *avalon)
  751. {
  752. avalon->queued = 0;
  753. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  754. avalon->work_array = 0;
  755. }
  756. static void avalon_set_timeout(struct avalon_info *info)
  757. {
  758. info->timeout = AVALON_TIMEOUT_FACTOR / info->frequency;
  759. }
  760. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  761. {
  762. struct avalon_info *info = avalon->device_data;
  763. info->frequency = frequency;
  764. if (info->frequency > opt_avalon_freq_max)
  765. info->frequency = opt_avalon_freq_max;
  766. if (info->frequency < opt_avalon_freq_min)
  767. info->frequency = opt_avalon_freq_min;
  768. avalon_set_timeout(info);
  769. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  770. avalon->drv->name, avalon->device_id,
  771. info->frequency, info->timeout);
  772. }
  773. static void avalon_inc_freq(struct avalon_info *info)
  774. {
  775. info->frequency += 2;
  776. if (info->frequency > opt_avalon_freq_max)
  777. info->frequency = opt_avalon_freq_max;
  778. avalon_set_timeout(info);
  779. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  780. info->frequency, info->timeout);
  781. }
  782. static void avalon_dec_freq(struct avalon_info *info)
  783. {
  784. info->frequency -= 1;
  785. if (info->frequency < opt_avalon_freq_min)
  786. info->frequency = opt_avalon_freq_min;
  787. avalon_set_timeout(info);
  788. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  789. info->frequency, info->timeout);
  790. }
  791. static void avalon_reset_auto(struct avalon_info *info)
  792. {
  793. info->auto_queued =
  794. info->auto_nonces =
  795. info->auto_hw = 0;
  796. }
  797. static void *avalon_send_tasks(void *userdata)
  798. {
  799. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  800. struct avalon_info *info = avalon->device_data;
  801. const int avalon_get_work_count = info->miner_count;
  802. char threadname[24];
  803. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  804. RenameThread(threadname);
  805. while (likely(!avalon->shutdown)) {
  806. int start_count, end_count, i, j, ret;
  807. struct avalon_task at;
  808. bool idled = false;
  809. while (avalon_buffer_full(avalon))
  810. cgsem_wait(&info->write_sem);
  811. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  812. mutex_lock(&info->lock);
  813. if (!info->optimal) {
  814. if (info->fan_pwm >= opt_avalon_fan_max) {
  815. applog(LOG_WARNING,
  816. "%s%i: Above optimal temperature, throttling",
  817. avalon->drv->name, avalon->device_id);
  818. avalon_dec_freq(info);
  819. }
  820. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  821. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  822. int total = info->auto_nonces + info->auto_hw;
  823. /* Try to keep hw errors < 2% */
  824. if (info->auto_hw * 100 < total)
  825. avalon_inc_freq(info);
  826. else if (info->auto_hw * 66 > total)
  827. avalon_dec_freq(info);
  828. }
  829. avalon_reset_auto(info);
  830. mutex_unlock(&info->lock);
  831. }
  832. mutex_lock(&info->qlock);
  833. start_count = avalon->work_array * avalon_get_work_count;
  834. end_count = start_count + avalon_get_work_count;
  835. for (i = start_count, j = 0; i < end_count; i++, j++) {
  836. if (avalon_buffer_full(avalon)) {
  837. applog(LOG_INFO,
  838. "%s%i: Buffer full after only %d of %d work queued",
  839. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  840. if (usb_ident(avalon) != IDENT_BTB)
  841. break;
  842. else {
  843. while (avalon_buffer_full(avalon))
  844. cgsem_wait(&info->write_sem);
  845. }
  846. }
  847. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  848. avalon_init_task(&at, 0, 0, info->fan_pwm,
  849. info->timeout, info->asic_count,
  850. info->miner_count, 1, 0, info->frequency);
  851. avalon_create_task(&at, avalon->works[i]);
  852. info->auto_queued++;
  853. } else {
  854. int idle_freq = info->frequency;
  855. if (!info->idle++)
  856. idled = true;
  857. if (unlikely(info->overheat && opt_avalon_auto))
  858. idle_freq = AVALON_MIN_FREQUENCY;
  859. avalon_init_task(&at, 0, 0, info->fan_pwm,
  860. info->timeout, info->asic_count,
  861. info->miner_count, 1, 1, idle_freq);
  862. /* Reset the auto_queued count if we end up
  863. * idling any miners. */
  864. avalon_reset_auto(info);
  865. }
  866. ret = avalon_send_task(&at, avalon);
  867. if (unlikely(ret == AVA_SEND_ERROR)) {
  868. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  869. avalon->drv->name, avalon->device_id);
  870. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  871. info->reset = true;
  872. break;
  873. }
  874. }
  875. avalon_rotate_array(avalon);
  876. pthread_cond_signal(&info->qcond);
  877. mutex_unlock(&info->qlock);
  878. if (unlikely(idled)) {
  879. applog(LOG_WARNING, "%s%i: Idled %d miners",
  880. avalon->drv->name, avalon->device_id, idled);
  881. }
  882. }
  883. return NULL;
  884. }
  885. static bool avalon_prepare(struct thr_info *thr)
  886. {
  887. struct cgpu_info *avalon = thr->cgpu;
  888. struct avalon_info *info = avalon->device_data;
  889. free(avalon->works);
  890. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  891. AVALON_ARRAY_SIZE);
  892. if (!avalon->works)
  893. quit(1, "Failed to calloc avalon works in avalon_prepare");
  894. info->thr = thr;
  895. mutex_init(&info->lock);
  896. mutex_init(&info->qlock);
  897. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  898. quit(1, "Failed to pthread_cond_init avalon qcond");
  899. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  900. quit(1, "Failed to create avalon read_thr");
  901. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  902. quit(1, "Failed to create avalon write_thr");
  903. avalon_init(avalon);
  904. return true;
  905. }
  906. static void do_avalon_close(struct thr_info *thr)
  907. {
  908. struct cgpu_info *avalon = thr->cgpu;
  909. struct avalon_info *info = avalon->device_data;
  910. pthread_join(info->read_thr, NULL);
  911. pthread_join(info->write_thr, NULL);
  912. avalon_running_reset(avalon, info);
  913. info->no_matching_work = 0;
  914. cgsem_destroy(&info->write_sem);
  915. }
  916. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  917. {
  918. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  919. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  920. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  921. info->temp0 = ar->temp0;
  922. info->temp1 = ar->temp1;
  923. info->temp2 = ar->temp2;
  924. if (ar->temp0 & 0x80) {
  925. ar->temp0 &= 0x7f;
  926. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  927. }
  928. if (ar->temp1 & 0x80) {
  929. ar->temp1 &= 0x7f;
  930. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  931. }
  932. if (ar->temp2 & 0x80) {
  933. ar->temp2 &= 0x7f;
  934. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  935. }
  936. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  937. if (info->temp0 > info->temp_max)
  938. info->temp_max = info->temp0;
  939. if (info->temp1 > info->temp_max)
  940. info->temp_max = info->temp1;
  941. if (info->temp2 > info->temp_max)
  942. info->temp_max = info->temp2;
  943. }
  944. static void temp_rise(struct avalon_info *info, int temp)
  945. {
  946. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  947. info->fan_pwm = AVALON_PWM_MAX;
  948. return;
  949. }
  950. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  951. info->fan_pwm += 10;
  952. else if (temp > opt_avalon_temp)
  953. info->fan_pwm += 5;
  954. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  955. info->fan_pwm += 1;
  956. else
  957. return;
  958. if (info->fan_pwm > opt_avalon_fan_max)
  959. info->fan_pwm = opt_avalon_fan_max;
  960. }
  961. static void temp_drop(struct avalon_info *info, int temp)
  962. {
  963. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  964. info->fan_pwm = opt_avalon_fan_min;
  965. return;
  966. }
  967. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  968. info->fan_pwm -= 10;
  969. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  970. info->fan_pwm -= 5;
  971. else if (temp < opt_avalon_temp)
  972. info->fan_pwm -= 1;
  973. if (info->fan_pwm < opt_avalon_fan_min)
  974. info->fan_pwm = opt_avalon_fan_min;
  975. }
  976. static inline void adjust_fan(struct avalon_info *info)
  977. {
  978. int temp_new;
  979. temp_new = info->temp_sum / info->temp_history_count;
  980. if (temp_new > info->temp_old)
  981. temp_rise(info, temp_new);
  982. else if (temp_new < info->temp_old)
  983. temp_drop(info, temp_new);
  984. else {
  985. /* temp_new == info->temp_old */
  986. if (temp_new > opt_avalon_temp)
  987. temp_rise(info, temp_new);
  988. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  989. temp_drop(info, temp_new);
  990. }
  991. info->temp_old = temp_new;
  992. if (info->temp_old <= opt_avalon_temp)
  993. info->optimal = true;
  994. else
  995. info->optimal = false;
  996. }
  997. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  998. struct avalon_result *ar)
  999. {
  1000. record_temp_fan(info, ar, &(avalon->temp));
  1001. applog(LOG_INFO,
  1002. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1003. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1004. info->fan0, info->fan1, info->fan2,
  1005. info->temp0, info->temp1, info->temp2, info->temp_max);
  1006. info->temp_history_index++;
  1007. info->temp_sum += avalon->temp;
  1008. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1009. info->temp_history_index, info->temp_history_count, info->temp_old);
  1010. if (usb_ident(avalon) == IDENT_BTB) {
  1011. info->core_voltage = bitburner_get_core_voltage(avalon);
  1012. }
  1013. if (info->temp_history_index == info->temp_history_count) {
  1014. adjust_fan(info);
  1015. info->temp_history_index = 0;
  1016. info->temp_sum = 0;
  1017. }
  1018. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1019. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1020. info->overheat = true;
  1021. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1022. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1023. info->overheat = false;
  1024. }
  1025. }
  1026. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1027. {
  1028. struct avalon_info *info = avalon->device_data;
  1029. int lowfan = 10000;
  1030. if (usb_ident(avalon) == IDENT_BTB) {
  1031. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1032. } else {
  1033. /* Find the lowest fan speed of the ASIC cooling fans. */
  1034. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1035. lowfan = info->fan1;
  1036. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1037. lowfan = info->fan2;
  1038. tailsprintf(buf, bufsiz, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1039. }
  1040. }
  1041. /* We use a replacement algorithm to only remove references to work done from
  1042. * the buffer when we need the extra space for new work. */
  1043. static bool avalon_fill(struct cgpu_info *avalon)
  1044. {
  1045. struct avalon_info *info = avalon->device_data;
  1046. int subid, slot, mc;
  1047. struct work *work;
  1048. bool ret = true;
  1049. mc = info->miner_count;
  1050. mutex_lock(&info->qlock);
  1051. if (avalon->queued >= mc)
  1052. goto out_unlock;
  1053. work = get_queued(avalon);
  1054. if (unlikely(!work)) {
  1055. ret = false;
  1056. goto out_unlock;
  1057. }
  1058. subid = avalon->queued++;
  1059. work->subid = subid;
  1060. slot = avalon->work_array * mc + subid;
  1061. if (likely(avalon->works[slot]))
  1062. work_completed(avalon, avalon->works[slot]);
  1063. avalon->works[slot] = work;
  1064. if (avalon->queued < mc)
  1065. ret = false;
  1066. out_unlock:
  1067. mutex_unlock(&info->qlock);
  1068. return ret;
  1069. }
  1070. static int64_t avalon_scanhash(struct thr_info *thr)
  1071. {
  1072. struct cgpu_info *avalon = thr->cgpu;
  1073. struct avalon_info *info = avalon->device_data;
  1074. const int miner_count = info->miner_count;
  1075. struct timeval now, then, tdiff;
  1076. int64_t hash_count, us_timeout;
  1077. struct timespec abstime;
  1078. int ret;
  1079. /* Half nonce range */
  1080. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1081. tdiff.tv_sec = us_timeout / 1000000;
  1082. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  1083. cgtime(&now);
  1084. timeradd(&now, &tdiff, &then);
  1085. abstime.tv_sec = then.tv_sec;
  1086. abstime.tv_nsec = then.tv_usec * 1000;
  1087. /* Wait until avalon_send_tasks signals us that it has completed
  1088. * sending its work or a full nonce range timeout has occurred */
  1089. mutex_lock(&info->qlock);
  1090. ret = pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1091. mutex_unlock(&info->qlock);
  1092. /* If we timed out, avalon_send_tasks may be stuck waiting on the
  1093. * write_sem, so force it to check for avalon_buffer_full itself. */
  1094. if (ret)
  1095. cgsem_post(&info->write_sem);
  1096. mutex_lock(&info->lock);
  1097. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1098. avalon->results += info->nonces + info->idle;
  1099. if (avalon->results > miner_count)
  1100. avalon->results = miner_count;
  1101. if (!info->reset)
  1102. avalon->results--;
  1103. info->nonces = info->idle = 0;
  1104. mutex_unlock(&info->lock);
  1105. /* Check for nothing but consecutive bad results or consistently less
  1106. * results than we should be getting and reset the FPGA if necessary */
  1107. if (usb_ident(avalon) != IDENT_BTB) {
  1108. if (avalon->results < -miner_count && !info->reset) {
  1109. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1110. avalon->drv->name, avalon->device_id);
  1111. info->reset = true;
  1112. }
  1113. }
  1114. if (unlikely(avalon->usbinfo.nodev)) {
  1115. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1116. avalon->drv->name, avalon->device_id);
  1117. avalon->shutdown = true;
  1118. }
  1119. /* This hashmeter is just a utility counter based on returned shares */
  1120. return hash_count;
  1121. }
  1122. static void avalon_flush_work(struct cgpu_info *avalon)
  1123. {
  1124. struct avalon_info *info = avalon->device_data;
  1125. mutex_lock(&info->qlock);
  1126. /* Will overwrite any work queued */
  1127. avalon->queued = 0;
  1128. pthread_cond_signal(&info->qcond);
  1129. mutex_unlock(&info->qlock);
  1130. }
  1131. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1132. {
  1133. struct api_data *root = NULL;
  1134. struct avalon_info *info = cgpu->device_data;
  1135. int i;
  1136. root = api_add_int(root, "baud", &(info->baud), false);
  1137. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1138. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1139. root = api_add_int(root, "timeout", &(info->timeout), false);
  1140. root = api_add_int(root, "frequency", &(info->frequency), false);
  1141. root = api_add_int(root, "fan1", &(info->fan0), false);
  1142. root = api_add_int(root, "fan2", &(info->fan1), false);
  1143. root = api_add_int(root, "fan3", &(info->fan2), false);
  1144. root = api_add_int(root, "temp1", &(info->temp0), false);
  1145. root = api_add_int(root, "temp2", &(info->temp1), false);
  1146. root = api_add_int(root, "temp3", &(info->temp2), false);
  1147. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1148. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1149. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1150. for (i = 0; i < info->miner_count; i++) {
  1151. char mcw[24];
  1152. sprintf(mcw, "match_work_count%d", i + 1);
  1153. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1154. }
  1155. return root;
  1156. }
  1157. static void avalon_shutdown(struct thr_info *thr)
  1158. {
  1159. do_avalon_close(thr);
  1160. }
  1161. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1162. {
  1163. int val;
  1164. if (strcasecmp(option, "help") == 0) {
  1165. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1166. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1167. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1168. return replybuf;
  1169. }
  1170. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1171. if (usb_ident(avalon) != IDENT_BTB) {
  1172. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1173. return replybuf;
  1174. }
  1175. if (!setting || !*setting) {
  1176. sprintf(replybuf, "missing millivolts setting");
  1177. return replybuf;
  1178. }
  1179. val = atoi(setting);
  1180. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1181. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1182. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1183. return replybuf;
  1184. }
  1185. if (bitburner_set_core_voltage(avalon, val))
  1186. return NULL;
  1187. else {
  1188. sprintf(replybuf, "Set millivolts failed");
  1189. return replybuf;
  1190. }
  1191. }
  1192. if (strcasecmp(option, "freq") == 0) {
  1193. if (!setting || !*setting) {
  1194. sprintf(replybuf, "missing freq setting");
  1195. return replybuf;
  1196. }
  1197. val = atoi(setting);
  1198. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1199. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1200. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1201. return replybuf;
  1202. }
  1203. avalon_set_freq(avalon, val);
  1204. return NULL;
  1205. }
  1206. sprintf(replybuf, "Unknown option: %s", option);
  1207. return replybuf;
  1208. }
  1209. struct device_drv avalon_drv = {
  1210. .drv_id = DRIVER_AVALON,
  1211. .dname = "avalon",
  1212. .name = "AVA",
  1213. .drv_detect = avalon_detect,
  1214. .thread_prepare = avalon_prepare,
  1215. .hash_work = hash_queued_work,
  1216. .queue_full = avalon_fill,
  1217. .scanwork = avalon_scanhash,
  1218. .flush_work = avalon_flush_work,
  1219. .get_api_stats = avalon_api_stats,
  1220. .get_statline_before = get_avalon_statline_before,
  1221. .set_device = avalon_set_device,
  1222. .reinit_device = avalon_init,
  1223. .thread_shutdown = avalon_shutdown,
  1224. };