driver-avalon.c 17 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. static struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  38. uint8_t reset, uint8_t ff, uint8_t fan,
  39. uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (!at)
  48. return -1;
  49. if (!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (thr) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (reset) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (first && !at->reset) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = 1;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at)
  89. {
  90. size_t ret;
  91. int full;
  92. struct timespec p;
  93. uint8_t *buf;
  94. size_t nr_len;
  95. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  96. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  97. if (!buf)
  98. return AVA_SEND_ERROR;
  99. memcpy(buf, at, AVALON_WRITE_SIZE);
  100. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  101. uint8_t tt = 0;
  102. tt = (buf[0] & 0x0f) << 4;
  103. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  104. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  105. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  106. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  107. buf[0] = tt;
  108. buf[4] = rev8(buf[4]);
  109. #endif
  110. if (opt_debug) {
  111. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  112. hexdump((uint8_t *)buf, nr_len);
  113. }
  114. ret = write(fd, buf, nr_len);
  115. free(buf);
  116. if (unlikely(ret != nr_len))
  117. return AVA_SEND_ERROR;
  118. p.tv_sec = 0;
  119. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  120. nanosleep(&p, NULL);
  121. full = avalon_buffer_full(fd);
  122. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  123. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  124. if (full == AVA_BUFFER_EMPTY)
  125. return AVA_SEND_BUFFER_EMPTY;
  126. return AVA_SEND_BUFFER_FULL;
  127. }
  128. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  129. struct thr_info *thr, struct timeval *tv_finish)
  130. {
  131. ssize_t ret = 0;
  132. int rc = 0;
  133. int read_amount = AVALON_READ_SIZE;
  134. bool first = true;
  135. /* Read reply 1 byte at a time to get earliest tv_finish */
  136. while (true) {
  137. ret = read(fd, buf, 1);
  138. if (ret < 0)
  139. return AVA_GETS_ERROR;
  140. if (first && tv_finish != NULL)
  141. gettimeofday(tv_finish, NULL);
  142. if (ret >= read_amount)
  143. return AVA_GETS_OK;
  144. if (ret > 0) {
  145. buf += ret;
  146. read_amount -= ret;
  147. first = false;
  148. continue;
  149. }
  150. rc++;
  151. if (rc >= read_count) {
  152. if (opt_debug) {
  153. applog(LOG_ERR,
  154. "Avalon: No data in %.2f seconds",
  155. (float)rc/(float)TIME_FACTOR);
  156. }
  157. return AVA_GETS_TIMEOUT;
  158. }
  159. if (thr && thr->work_restart) {
  160. if (opt_debug) {
  161. applog(LOG_ERR,
  162. "Avalon: Work restart at %.2f seconds",
  163. (float)(rc)/(float)TIME_FACTOR);
  164. }
  165. return AVA_GETS_RESTART;
  166. }
  167. }
  168. }
  169. static int avalon_get_result(int fd, struct avalon_result *ar,
  170. struct thr_info *thr, struct timeval *tv_finish)
  171. {
  172. struct cgpu_info *avalon;
  173. struct avalon_info *info;
  174. uint8_t result[AVALON_READ_SIZE];
  175. int ret, read_count = 16;
  176. if (thr) {
  177. avalon = thr->cgpu;
  178. info = avalon_info[avalon->device_id];
  179. read_count = info->read_count;
  180. }
  181. memset(result, 0, AVALON_READ_SIZE);
  182. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  183. if (ret == AVA_GETS_OK) {
  184. if (opt_debug) {
  185. applog(LOG_DEBUG, "Avalon: get:");
  186. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  187. }
  188. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  189. }
  190. return ret;
  191. }
  192. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  193. uint32_t *nonce)
  194. {
  195. int i;
  196. if (!work)
  197. return -1;
  198. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  199. if (work[i] &&
  200. !memcmp(ar->data, work[i]->data + 64, 12) &&
  201. !memcmp(ar->midstate, work[i]->midstate, 32))
  202. break;
  203. }
  204. if (i == AVALON_GET_WORK_COUNT)
  205. return -1;
  206. *nonce = ar->nonce;
  207. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  208. *nonce = swab32(*nonce);
  209. #endif
  210. applog(LOG_DEBUG, "Avalon: match to work[%d]: %p", i, work[i]);
  211. return i;
  212. }
  213. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p, uint8_t miner_num_p)
  214. {
  215. struct avalon_task at;
  216. struct avalon_result ar;
  217. uint8_t *buf;
  218. int ret, i;
  219. struct timespec p;
  220. avalon_init_task(NULL,
  221. &at, 1, 0,
  222. AVALON_DEFAULT_FAN_PWM,
  223. timeout_p, asic_num_p, miner_num_p);
  224. ret = avalon_send_task(fd, &at);
  225. if (ret == AVA_SEND_ERROR)
  226. return 1;
  227. avalon_get_result(fd, &ar, NULL, NULL);
  228. buf = (uint8_t *)&ar;
  229. for (i = 0; i < 11; i++)
  230. if (buf[i] != 0)
  231. break;
  232. /* FIXME: add more avalon info base on return */
  233. if (i != 11) {
  234. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  235. return 1;
  236. }
  237. p.tv_sec = 1;
  238. p.tv_nsec = AVALON_RESET_PITCH;
  239. nanosleep(&p, NULL);
  240. applog(LOG_ERR, "Avalon: Reset succeeded");
  241. return 0;
  242. }
  243. static void do_avalon_close(struct thr_info *thr)
  244. {
  245. struct cgpu_info *avalon = thr->cgpu;
  246. avalon_close(avalon->device_fd);
  247. avalon->device_fd = -1;
  248. }
  249. static void set_timing_mode(struct cgpu_info *avalon)
  250. {
  251. struct avalon_info *info = avalon_info[avalon->device_id];
  252. /* Anything else in buf just uses DEFAULT mode */
  253. info->Hs = AVALON_HASH_TIME;
  254. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  255. info->read_count =
  256. (int)(info->fullnonce * TIME_FACTOR) - 1;
  257. }
  258. static void get_options(int this_option_offset, int *baud, int *miner_count,
  259. int *asic_count, int *timeout)
  260. {
  261. char err_buf[BUFSIZ+1];
  262. char buf[BUFSIZ+1];
  263. char *ptr, *comma, *colon, *colon2, *colon3;
  264. size_t max;
  265. int i, tmp;
  266. if (opt_avalon_options == NULL)
  267. buf[0] = '\0';
  268. else {
  269. ptr = opt_avalon_options;
  270. for (i = 0; i < this_option_offset; i++) {
  271. comma = strchr(ptr, ',');
  272. if (comma == NULL)
  273. break;
  274. ptr = comma + 1;
  275. }
  276. comma = strchr(ptr, ',');
  277. if (comma == NULL)
  278. max = strlen(ptr);
  279. else
  280. max = comma - ptr;
  281. if (max > BUFSIZ)
  282. max = BUFSIZ;
  283. strncpy(buf, ptr, max);
  284. buf[max] = '\0';
  285. }
  286. *baud = AVALON_IO_SPEED;
  287. *miner_count = AVALON_DEFAULT_MINER_NUM;
  288. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  289. *timeout = AVALON_DEFAULT_TIMEOUT;
  290. if (!(*buf))
  291. return;
  292. colon = strchr(buf, ':');
  293. if (colon)
  294. *(colon++) = '\0';
  295. tmp = atoi(buf);
  296. switch (tmp) {
  297. case 115200:
  298. *baud = 115200;
  299. break;
  300. case 57600:
  301. *baud = 57600;
  302. break;
  303. case 19200:
  304. *baud = 19200;
  305. break;
  306. default:
  307. sprintf(err_buf,
  308. "Invalid avalon-options for baud (%s) "
  309. "must be 115200, 57600 or 19200", buf);
  310. quit(1, err_buf);
  311. }
  312. if (colon && *colon) {
  313. colon2 = strchr(colon, ':');
  314. if (colon2)
  315. *(colon2++) = '\0';
  316. if (*colon) {
  317. tmp = atoi(colon);
  318. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  319. *miner_count = tmp;
  320. } else {
  321. sprintf(err_buf,
  322. "Invalid avalon-options for "
  323. "miner_count (%s) must be 1 ~ %d",
  324. colon, AVALON_DEFAULT_MINER_NUM);
  325. quit(1, err_buf);
  326. }
  327. }
  328. if (colon2 && *colon2) {
  329. colon3 = strchr(colon2, ':');
  330. if (colon3)
  331. *(colon3++) = '\0';
  332. tmp = atoi(colon2);
  333. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  334. *asic_count = tmp;
  335. else {
  336. sprintf(err_buf,
  337. "Invalid avalon-options for "
  338. "asic_count (%s) must be 1 ~ %d",
  339. colon2, AVALON_DEFAULT_ASIC_NUM);
  340. quit(1, err_buf);
  341. }
  342. if (colon3 && *colon3) {
  343. tmp = atoi(colon3);
  344. if (tmp > 0 && tmp <= AVALON_DEFAULT_TIMEOUT)
  345. *timeout = tmp;
  346. else {
  347. sprintf(err_buf,
  348. "Invalid avalon-options for "
  349. "timeout (%s) must be 1 ~ %d",
  350. colon3, AVALON_DEFAULT_TIMEOUT);
  351. quit(1, err_buf);
  352. }
  353. }
  354. }
  355. }
  356. }
  357. static bool avalon_detect_one(const char *devpath)
  358. {
  359. struct avalon_info *info;
  360. int fd, ret;
  361. int baud, miner_count, asic_count, timeout;
  362. int this_option_offset = ++option_offset;
  363. get_options(this_option_offset, &baud, &miner_count, &asic_count, &timeout);
  364. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  365. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  366. devpath, baud, miner_count, asic_count, timeout);
  367. fd = avalon_open2(devpath, baud, true);
  368. if (unlikely(fd == -1)) {
  369. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  370. return false;
  371. }
  372. ret = avalon_reset(fd, timeout, asic_count, miner_count);
  373. avalon_close(fd);
  374. if (ret)
  375. return false;
  376. /* We have a real Avalon! */
  377. struct cgpu_info *avalon;
  378. avalon = calloc(1, sizeof(struct cgpu_info));
  379. avalon->api = &avalon_api;
  380. avalon->device_path = strdup(devpath);
  381. avalon->device_fd = -1;
  382. avalon->threads = AVALON_MINER_THREADS;
  383. add_cgpu(avalon);
  384. avalon_info = realloc(avalon_info,
  385. sizeof(struct avalon_info *) *
  386. (total_devices + 1));
  387. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  388. devpath, avalon->device_id);
  389. avalon_info[avalon->device_id] = (struct avalon_info *)
  390. malloc(sizeof(struct avalon_info));
  391. if (unlikely(!(avalon_info[avalon->device_id])))
  392. quit(1, "Failed to malloc avalon_info");
  393. info = avalon_info[avalon->device_id];
  394. memset(info, 0, sizeof(struct avalon_info));
  395. info->baud = baud;
  396. info->miner_count = miner_count;
  397. info->asic_count = asic_count;
  398. info->timeout = timeout;
  399. set_timing_mode(avalon);
  400. return true;
  401. }
  402. static inline void avalon_detect()
  403. {
  404. serial_detect(&avalon_api, avalon_detect_one);
  405. }
  406. static bool avalon_prepare(struct thr_info *thr)
  407. {
  408. struct cgpu_info *avalon = thr->cgpu;
  409. struct timeval now;
  410. int fd, ret;
  411. struct avalon_info *info = avalon_info[avalon->device_id];
  412. avalon->device_fd = -1;
  413. fd = avalon_open(avalon->device_path,
  414. avalon_info[avalon->device_id]->baud);
  415. if (unlikely(fd == -1)) {
  416. applog(LOG_ERR, "Avalon: Failed to open on %s",
  417. avalon->device_path);
  418. return false;
  419. }
  420. ret = avalon_reset(fd, info->timeout, info->asic_count, info->miner_count);
  421. if (ret)
  422. return false;
  423. avalon->device_fd = fd;
  424. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  425. gettimeofday(&now, NULL);
  426. get_datestamp(avalon->init, &now);
  427. return true;
  428. }
  429. static void avalon_free_work(struct work **work)
  430. {
  431. int i;
  432. if (!work)
  433. return;
  434. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  435. if (work[i]) {
  436. free_work(work[i]);
  437. work[i] = NULL;
  438. }
  439. }
  440. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  441. __maybe_unused int64_t max_nonce)
  442. {
  443. struct cgpu_info *avalon;
  444. int fd;
  445. int ret;
  446. int full;
  447. struct avalon_info *info;
  448. struct avalon_task at;
  449. struct avalon_result ar;
  450. static struct work *bulk0[3] = {NULL, NULL, NULL};
  451. static struct work *bulk1[3] = {NULL, NULL, NULL};
  452. static struct work *bulk2[3] = {NULL, NULL, NULL};
  453. struct work **work = NULL;
  454. int i, work_i0, work_i1, work_i2;
  455. uint32_t nonce;
  456. int64_t hash_count;
  457. struct timeval tv_start, tv_finish, elapsed;
  458. int curr_hw_errors;
  459. bool was_hw_error;
  460. int64_t estimate_hashes;
  461. avalon = thr->cgpu;
  462. info = avalon_info[avalon->device_id];
  463. if (avalon->device_fd == -1)
  464. if (!avalon_prepare(thr)) {
  465. applog(LOG_ERR, "AVA%i: Comms error",
  466. avalon->device_id);
  467. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  468. /* fail the device if the reopen attempt fails */
  469. return -1;
  470. }
  471. fd = avalon->device_fd;
  472. #ifndef WIN32
  473. tcflush(fd, TCOFLUSH);
  474. #endif
  475. work = bulk_work;
  476. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  477. bulk0[i] = bulk1[i];
  478. bulk1[i] = bulk2[i];
  479. bulk2[i] = work[i];
  480. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  481. i, bulk0[i], bulk1[i], bulk2[i]);
  482. }
  483. i = 0;
  484. while (true) {
  485. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0);
  486. avalon_create_task(&at, work[i]);
  487. ret = avalon_send_task(fd, &at);
  488. if (ret == AVA_SEND_ERROR) {
  489. avalon_free_work(bulk0);
  490. avalon_free_work(bulk1);
  491. avalon_free_work(bulk2);
  492. do_avalon_close(thr);
  493. applog(LOG_ERR, "AVA%i: Comms error",
  494. avalon->device_id);
  495. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  496. sleep(1);
  497. return 0; /* This should never happen */
  498. }
  499. work[i]->blk.nonce = 0xffffffff;
  500. if (ret == AVA_SEND_BUFFER_FULL)
  501. break;
  502. i++;
  503. if (i == AVALON_GET_WORK_COUNT &&
  504. ret != AVA_SEND_BUFFER_FULL) {
  505. return 0xffffffff;
  506. }
  507. }
  508. elapsed.tv_sec = elapsed.tv_usec = 0;
  509. gettimeofday(&tv_start, NULL);
  510. while(true) {
  511. full = avalon_buffer_full(fd);
  512. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  513. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  514. if (full == AVA_BUFFER_EMPTY)
  515. break;
  516. work_i0 = work_i1 = work_i2 = -1;
  517. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  518. if (ret == AVA_GETS_ERROR) {
  519. avalon_free_work(bulk0);
  520. avalon_free_work(bulk1);
  521. avalon_free_work(bulk2);
  522. do_avalon_close(thr);
  523. applog(LOG_ERR,
  524. "AVA%i: Comms error", avalon->device_id);
  525. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  526. return 0;
  527. }
  528. /* aborted before becoming idle, get new work */
  529. if (ret == AVA_GETS_TIMEOUT) {
  530. timersub(&tv_finish, &tv_start, &elapsed);
  531. estimate_hashes = ((double)(elapsed.tv_sec) +
  532. ((double)(elapsed.tv_usec)) /
  533. ((double)1000000)) / info->Hs;
  534. /* If Serial-USB delay allowed the full nonce range to
  535. * complete it can't have done more than a full nonce
  536. */
  537. if (unlikely(estimate_hashes > 0xffffffff))
  538. estimate_hashes = 0xffffffff;
  539. applog(LOG_DEBUG,
  540. "Avalon: no nonce = 0x%08llx hashes "
  541. "(%ld.%06lds)",
  542. estimate_hashes, elapsed.tv_sec,
  543. elapsed.tv_usec);
  544. continue;
  545. }
  546. if (ret == AVA_GETS_RESTART) {
  547. avalon_free_work(bulk0);
  548. avalon_free_work(bulk1);
  549. avalon_free_work(bulk2);
  550. continue;
  551. }
  552. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  553. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  554. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  555. curr_hw_errors = avalon->hw_errors;
  556. if (work_i0 >= 0)
  557. submit_nonce(thr, bulk0[work_i0], nonce);
  558. if (work_i1 >= 0)
  559. submit_nonce(thr, bulk1[work_i1], nonce);
  560. if (work_i2 >= 0)
  561. submit_nonce(thr, bulk2[work_i2], nonce);
  562. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  563. /* Force a USB close/reopen on any hw error */
  564. if (was_hw_error)
  565. do_avalon_close(thr);
  566. hash_count = nonce;
  567. hash_count++;
  568. hash_count *= info->asic_count;
  569. }
  570. avalon_free_work(bulk0);
  571. if (opt_debug) {
  572. timersub(&tv_finish, &tv_start, &elapsed);
  573. applog(LOG_DEBUG,
  574. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  575. "(%ld.%06lds)",
  576. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  577. }
  578. return hash_count;
  579. }
  580. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  581. {
  582. struct api_data *root = NULL;
  583. struct avalon_info *info = avalon_info[cgpu->device_id];
  584. /* Warning, access to these is not locked - but we don't really
  585. * care since hashing performance is way more important than
  586. * locking access to displaying API debug 'stats'
  587. * If locking becomes an issue for any of them, use copy_data=true also */
  588. root = api_add_int(root, "read_count", &(info->read_count), false);
  589. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  590. root = api_add_int(root, "baud", &(info->baud), false);
  591. root = api_add_int(root, "miner_count", &(info->miner_count),
  592. false);
  593. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  594. return root;
  595. }
  596. static void avalon_shutdown(struct thr_info *thr)
  597. {
  598. do_avalon_close(thr);
  599. }
  600. struct device_api avalon_api = {
  601. .dname = "avalon",
  602. .name = "AVA",
  603. .api_detect = avalon_detect,
  604. .thread_prepare = avalon_prepare,
  605. .scanhash_queue = avalon_scanhash,
  606. .get_api_stats = avalon_api_stats,
  607. .thread_shutdown = avalon_shutdown,
  608. };