driver-avalon.c 27 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "fpgautils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. static int option_offset = -1;
  39. struct avalon_info **avalon_infos;
  40. struct device_drv avalon_drv;
  41. static int avalon_init_task(struct avalon_task *at,
  42. uint8_t reset, uint8_t ff, uint8_t fan,
  43. uint8_t timeout, uint8_t asic_num,
  44. uint8_t miner_num, uint8_t nonce_elf,
  45. uint8_t gate_miner, int frequency)
  46. {
  47. uint8_t *buf;
  48. static bool first = true;
  49. if (unlikely(!at))
  50. return -1;
  51. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  52. return -1;
  53. memset(at, 0, sizeof(struct avalon_task));
  54. if (unlikely(reset)) {
  55. at->reset = 1;
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = true;
  59. }
  60. at->flush_fifo = (ff ? 1 : 0);
  61. at->fan_eft = (fan ? 1 : 0);
  62. if (unlikely(first && !at->reset)) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  68. at->timeout_data = timeout;
  69. at->asic_num = asic_num;
  70. at->miner_num = miner_num;
  71. at->nonce_elf = nonce_elf;
  72. at->gate_miner_elf = 1;
  73. at->asic_pll = 1;
  74. if (unlikely(gate_miner)) {
  75. at-> gate_miner = 1;
  76. at->asic_pll = 0;
  77. }
  78. buf = (uint8_t *)at;
  79. buf[5] = 0x00;
  80. buf[8] = 0x74;
  81. buf[9] = 0x01;
  82. buf[10] = 0x00;
  83. buf[11] = 0x00;
  84. if (frequency == 256) {
  85. buf[6] = 0x03;
  86. buf[7] = 0x08;
  87. } else if (frequency == 270) {
  88. buf[6] = 0x73;
  89. buf[7] = 0x08;
  90. } else if (frequency == 282) {
  91. buf[6] = 0xd3;
  92. buf[7] = 0x08;
  93. } else if (frequency == 300) {
  94. buf[6] = 0x63;
  95. buf[7] = 0x09;
  96. }
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_send_task(int fd, const struct avalon_task *at,
  106. struct cgpu_info *avalon)
  107. {
  108. size_t ret;
  109. int full;
  110. struct timespec p;
  111. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  112. size_t nr_len;
  113. struct avalon_info *info;
  114. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  115. uint32_t nonce_range;
  116. int i;
  117. if (at->nonce_elf)
  118. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  119. else
  120. nr_len = AVALON_WRITE_SIZE;
  121. memcpy(buf, at, AVALON_WRITE_SIZE);
  122. if (at->nonce_elf) {
  123. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  124. for (i = 0; i < at->asic_num; i++) {
  125. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  126. (i * nonce_range & 0xff000000) >> 24;
  127. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  128. (i * nonce_range & 0x00ff0000) >> 16;
  129. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  130. (i * nonce_range & 0x0000ff00) >> 8;
  131. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  132. (i * nonce_range & 0x000000ff) >> 0;
  133. }
  134. }
  135. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  136. uint8_t tt = 0;
  137. tt = (buf[0] & 0x0f) << 4;
  138. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  139. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  140. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  141. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  142. buf[0] = tt;
  143. tt = (buf[4] & 0x0f) << 4;
  144. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  145. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  146. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  147. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  148. buf[4] = tt;
  149. #endif
  150. if (likely(avalon)) {
  151. info = avalon_infos[avalon->device_id];
  152. delay = nr_len * 10 * 1000000000ULL;
  153. delay = delay / info->baud;
  154. }
  155. if (at->reset)
  156. nr_len = 1;
  157. if (opt_debug) {
  158. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  159. hexdump((uint8_t *)buf, nr_len);
  160. }
  161. ret = write(fd, buf, nr_len);
  162. if (unlikely(ret != nr_len))
  163. return AVA_SEND_ERROR;
  164. p.tv_sec = 0;
  165. p.tv_nsec = (long)delay + 4000000;
  166. nanosleep(&p, NULL);
  167. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  168. full = avalon_buffer_full(fd);
  169. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  170. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  171. if (unlikely(full == AVA_BUFFER_FULL))
  172. return AVA_SEND_BUFFER_FULL;
  173. return AVA_SEND_BUFFER_EMPTY;
  174. }
  175. static inline int avalon_gets(int fd, uint8_t *buf, struct thr_info *thr,
  176. struct timeval *tv_finish)
  177. {
  178. int read_amount = AVALON_READ_SIZE;
  179. bool first = true;
  180. ssize_t ret = 0;
  181. while (true) {
  182. struct timeval timeout;
  183. fd_set rd;
  184. if (unlikely(thr->work_restart)) {
  185. applog(LOG_DEBUG, "Avalon: Work restart");
  186. return AVA_GETS_RESTART;
  187. }
  188. timeout.tv_sec = 0;
  189. timeout.tv_usec = 100000;
  190. FD_ZERO(&rd);
  191. FD_SET(fd, &rd);
  192. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  193. if (unlikely(ret < 0)) {
  194. applog(LOG_ERR, "Avalon: Error %d on select in avalon_gets", errno);
  195. return AVA_GETS_ERROR;
  196. }
  197. if (ret) {
  198. ret = read(fd, buf, read_amount);
  199. if (unlikely(ret < 0)) {
  200. applog(LOG_ERR, "Avalon: Error %d on read in avalon_gets", errno);
  201. return AVA_GETS_ERROR;
  202. }
  203. if (likely(first)) {
  204. gettimeofday(tv_finish, NULL);
  205. first = false;
  206. }
  207. if (likely(ret >= read_amount))
  208. return AVA_GETS_OK;
  209. buf += ret;
  210. read_amount -= ret;
  211. continue;
  212. }
  213. if (unlikely(thr->work_restart)) {
  214. applog(LOG_DEBUG, "Avalon: Work restart");
  215. return AVA_GETS_RESTART;
  216. }
  217. return AVA_GETS_TIMEOUT;
  218. }
  219. }
  220. static int avalon_get_result(int fd, struct avalon_result *ar,
  221. struct thr_info *thr, struct timeval *tv_finish)
  222. {
  223. uint8_t result[AVALON_READ_SIZE];
  224. int ret;
  225. memset(result, 0, AVALON_READ_SIZE);
  226. ret = avalon_gets(fd, result, thr, tv_finish);
  227. if (ret == AVA_GETS_OK) {
  228. if (opt_debug) {
  229. applog(LOG_DEBUG, "Avalon: get:");
  230. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  231. }
  232. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  233. }
  234. return ret;
  235. }
  236. static bool avalon_decode_nonce(struct thr_info *thr, struct avalon_result *ar,
  237. uint32_t *nonce)
  238. {
  239. struct cgpu_info *avalon;
  240. struct avalon_info *info;
  241. struct work *work;
  242. avalon = thr->cgpu;
  243. if (unlikely(!avalon->works))
  244. return false;
  245. work = find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  246. (char *)ar->data, 64, 12);
  247. if (!work)
  248. return false;
  249. info = avalon_infos[avalon->device_id];
  250. info->matching_work[work->subid]++;
  251. *nonce = htole32(ar->nonce);
  252. submit_nonce(thr, work, *nonce);
  253. return true;
  254. }
  255. static void avalon_get_reset(int fd, struct avalon_result *ar)
  256. {
  257. int read_amount = AVALON_READ_SIZE;
  258. uint8_t result[AVALON_READ_SIZE];
  259. struct timeval timeout = {1, 0};
  260. ssize_t ret = 0, offset = 0;
  261. fd_set rd;
  262. memset(result, 0, AVALON_READ_SIZE);
  263. memset(ar, 0, AVALON_READ_SIZE);
  264. FD_ZERO(&rd);
  265. FD_SET(fd, &rd);
  266. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  267. if (unlikely(ret < 0)) {
  268. applog(LOG_WARNING, "Avalon: Error %d on select in avalon_get_reset", errno);
  269. return;
  270. }
  271. if (!ret) {
  272. applog(LOG_WARNING, "Avalon: Timeout on select in avalon_get_reset");
  273. return;
  274. }
  275. do {
  276. ret = read(fd, result + offset, read_amount);
  277. if (unlikely(ret < 0)) {
  278. applog(LOG_WARNING, "Avalon: Error %d on read in avalon_get_reset", errno);
  279. return;
  280. }
  281. read_amount -= ret;
  282. offset += ret;
  283. } while (read_amount > 0);
  284. if (opt_debug) {
  285. applog(LOG_DEBUG, "Avalon: get:");
  286. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  287. }
  288. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  289. }
  290. static int avalon_reset(int fd, struct avalon_result *ar)
  291. {
  292. struct avalon_task at;
  293. uint8_t *buf;
  294. int ret, i = 0;
  295. struct timespec p;
  296. avalon_init_task(&at, 1, 0,
  297. AVALON_DEFAULT_FAN_MAX_PWM,
  298. AVALON_DEFAULT_TIMEOUT,
  299. AVALON_DEFAULT_ASIC_NUM,
  300. AVALON_DEFAULT_MINER_NUM,
  301. 0, 0,
  302. AVALON_DEFAULT_FREQUENCY);
  303. ret = avalon_send_task(fd, &at, NULL);
  304. if (ret == AVA_SEND_ERROR)
  305. return 1;
  306. avalon_get_reset(fd, ar);
  307. buf = (uint8_t *)ar;
  308. /* Sometimes there is one extra 0 byte for some reason in the buffer,
  309. * so work around it. */
  310. if (buf[0] == 0)
  311. buf = (uint8_t *)(ar + 1);
  312. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  313. buf[2] == 0xAA && buf[3] == 0x55) {
  314. for (i = 4; i < 11; i++)
  315. if (buf[i] != 0)
  316. break;
  317. }
  318. p.tv_sec = 0;
  319. p.tv_nsec = AVALON_RESET_PITCH;
  320. nanosleep(&p, NULL);
  321. if (i != 11) {
  322. applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
  323. " (%d: %02x %02x %02x %02x)",
  324. i, buf[0], buf[1], buf[2], buf[3]);
  325. /* FIXME: return 1; */
  326. } else
  327. applog(LOG_WARNING, "Avalon: Reset succeeded");
  328. return 0;
  329. }
  330. static void avalon_idle(struct cgpu_info *avalon)
  331. {
  332. int i, ret;
  333. struct avalon_task at;
  334. int fd = avalon->device_fd;
  335. struct avalon_info *info = avalon_infos[avalon->device_id];
  336. int avalon_get_work_count = info->miner_count;
  337. i = 0;
  338. while (true) {
  339. avalon_init_task(&at, 0, 0, info->fan_pwm,
  340. info->timeout, info->asic_count,
  341. info->miner_count, 1, 1, info->frequency);
  342. ret = avalon_send_task(fd, &at, avalon);
  343. if (unlikely(ret == AVA_SEND_ERROR ||
  344. (ret == AVA_SEND_BUFFER_EMPTY &&
  345. (i + 1 == avalon_get_work_count * 2)))) {
  346. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  347. return;
  348. }
  349. if (i + 1 == avalon_get_work_count * 2)
  350. break;
  351. if (ret == AVA_SEND_BUFFER_FULL)
  352. break;
  353. i++;
  354. }
  355. applog(LOG_ERR, "Avalon: Goto idle mode");
  356. }
  357. static void get_options(int this_option_offset, int *baud, int *miner_count,
  358. int *asic_count, int *timeout, int *frequency)
  359. {
  360. char err_buf[BUFSIZ+1];
  361. char buf[BUFSIZ+1];
  362. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  363. size_t max;
  364. int i, tmp;
  365. if (opt_avalon_options == NULL)
  366. buf[0] = '\0';
  367. else {
  368. ptr = opt_avalon_options;
  369. for (i = 0; i < this_option_offset; i++) {
  370. comma = strchr(ptr, ',');
  371. if (comma == NULL)
  372. break;
  373. ptr = comma + 1;
  374. }
  375. comma = strchr(ptr, ',');
  376. if (comma == NULL)
  377. max = strlen(ptr);
  378. else
  379. max = comma - ptr;
  380. if (max > BUFSIZ)
  381. max = BUFSIZ;
  382. strncpy(buf, ptr, max);
  383. buf[max] = '\0';
  384. }
  385. *baud = AVALON_IO_SPEED;
  386. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  387. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  388. *timeout = AVALON_DEFAULT_TIMEOUT;
  389. *frequency = AVALON_DEFAULT_FREQUENCY;
  390. if (!(*buf))
  391. return;
  392. colon = strchr(buf, ':');
  393. if (colon)
  394. *(colon++) = '\0';
  395. tmp = atoi(buf);
  396. switch (tmp) {
  397. case 115200:
  398. *baud = 115200;
  399. break;
  400. case 57600:
  401. *baud = 57600;
  402. break;
  403. case 38400:
  404. *baud = 38400;
  405. break;
  406. case 19200:
  407. *baud = 19200;
  408. break;
  409. default:
  410. sprintf(err_buf,
  411. "Invalid avalon-options for baud (%s) "
  412. "must be 115200, 57600, 38400 or 19200", buf);
  413. quit(1, err_buf);
  414. }
  415. if (colon && *colon) {
  416. colon2 = strchr(colon, ':');
  417. if (colon2)
  418. *(colon2++) = '\0';
  419. if (*colon) {
  420. tmp = atoi(colon);
  421. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  422. *miner_count = tmp;
  423. } else {
  424. sprintf(err_buf,
  425. "Invalid avalon-options for "
  426. "miner_count (%s) must be 1 ~ %d",
  427. colon, AVALON_DEFAULT_MINER_NUM);
  428. quit(1, err_buf);
  429. }
  430. }
  431. if (colon2 && *colon2) {
  432. colon3 = strchr(colon2, ':');
  433. if (colon3)
  434. *(colon3++) = '\0';
  435. tmp = atoi(colon2);
  436. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  437. *asic_count = tmp;
  438. else {
  439. sprintf(err_buf,
  440. "Invalid avalon-options for "
  441. "asic_count (%s) must be 1 ~ %d",
  442. colon2, AVALON_DEFAULT_ASIC_NUM);
  443. quit(1, err_buf);
  444. }
  445. if (colon3 && *colon3) {
  446. colon4 = strchr(colon3, ':');
  447. if (colon4)
  448. *(colon4++) = '\0';
  449. tmp = atoi(colon3);
  450. if (tmp > 0 && tmp <= 0xff)
  451. *timeout = tmp;
  452. else {
  453. sprintf(err_buf,
  454. "Invalid avalon-options for "
  455. "timeout (%s) must be 1 ~ %d",
  456. colon3, 0xff);
  457. quit(1, err_buf);
  458. }
  459. if (colon4 && *colon4) {
  460. tmp = atoi(colon4);
  461. switch (tmp) {
  462. case 256:
  463. case 270:
  464. case 282:
  465. case 300:
  466. *frequency = tmp;
  467. break;
  468. default:
  469. sprintf(err_buf,
  470. "Invalid avalon-options for "
  471. "frequency must be 256/270/282/300");
  472. quit(1, err_buf);
  473. }
  474. }
  475. }
  476. }
  477. }
  478. }
  479. static bool avalon_detect_one(const char *devpath)
  480. {
  481. struct avalon_info *info;
  482. struct avalon_result ar;
  483. int fd, ret;
  484. int baud, miner_count, asic_count, timeout, frequency = 0;
  485. struct cgpu_info *avalon;
  486. int this_option_offset = ++option_offset;
  487. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  488. &timeout, &frequency);
  489. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  490. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  491. devpath, baud, miner_count, asic_count, timeout, frequency);
  492. fd = avalon_open2(devpath, baud, true);
  493. if (unlikely(fd == -1)) {
  494. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  495. return false;
  496. }
  497. /* We have a real Avalon! */
  498. avalon = calloc(1, sizeof(struct cgpu_info));
  499. avalon->drv = &avalon_drv;
  500. avalon->device_path = strdup(devpath);
  501. avalon->device_fd = fd;
  502. avalon->threads = AVALON_MINER_THREADS;
  503. add_cgpu(avalon);
  504. ret = avalon_reset(fd, &ar);
  505. if (ret) {
  506. ; /* FIXME: I think IT IS avalon and wait on reset;
  507. * avalon_close(fd);
  508. * return false; */
  509. }
  510. avalon_infos = realloc(avalon_infos,
  511. sizeof(struct avalon_info *) *
  512. (total_devices + 1));
  513. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  514. devpath, avalon->device_id);
  515. avalon_infos[avalon->device_id] = (struct avalon_info *)
  516. malloc(sizeof(struct avalon_info));
  517. if (unlikely(!(avalon_infos[avalon->device_id])))
  518. quit(1, "Failed to malloc avalon_infos");
  519. info = avalon_infos[avalon->device_id];
  520. memset(info, 0, sizeof(struct avalon_info));
  521. info->baud = baud;
  522. info->miner_count = miner_count;
  523. info->asic_count = asic_count;
  524. info->timeout = timeout;
  525. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  526. info->temp_max = 0;
  527. /* This is for check the temp/fan every 3~4s */
  528. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  529. if (info->temp_history_count <= 0)
  530. info->temp_history_count = 1;
  531. info->temp_history_index = 0;
  532. info->temp_sum = 0;
  533. info->temp_old = 0;
  534. info->frequency = frequency;
  535. /* Set asic to idle mode after detect */
  536. avalon_idle(avalon);
  537. avalon->device_fd = -1;
  538. avalon_close(fd);
  539. return true;
  540. }
  541. static inline void avalon_detect()
  542. {
  543. serial_detect(&avalon_drv, avalon_detect_one);
  544. }
  545. static void __avalon_init(struct cgpu_info *avalon)
  546. {
  547. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  548. }
  549. static void avalon_init(struct cgpu_info *avalon)
  550. {
  551. struct avalon_result ar;
  552. int fd, ret;
  553. avalon->device_fd = -1;
  554. fd = avalon_open(avalon->device_path,
  555. avalon_infos[avalon->device_id]->baud);
  556. if (unlikely(fd == -1)) {
  557. applog(LOG_ERR, "Avalon: Failed to open on %s",
  558. avalon->device_path);
  559. return;
  560. }
  561. ret = avalon_reset(fd, &ar);
  562. if (ret) {
  563. avalon_close(fd);
  564. return;
  565. }
  566. avalon->device_fd = fd;
  567. __avalon_init(avalon);
  568. }
  569. static bool avalon_prepare(struct thr_info *thr)
  570. {
  571. struct cgpu_info *avalon = thr->cgpu;
  572. struct avalon_info *info = avalon_infos[avalon->device_id];
  573. struct timeval now;
  574. free(avalon->works);
  575. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  576. AVALON_ARRAY_SIZE);
  577. if (!avalon->works)
  578. quit(1, "Failed to calloc avalon works in avalon_prepare");
  579. if (avalon->device_fd == -1)
  580. avalon_init(avalon);
  581. else
  582. __avalon_init(avalon);
  583. gettimeofday(&now, NULL);
  584. get_datestamp(avalon->init, &now);
  585. return true;
  586. }
  587. static void avalon_free_work(struct thr_info *thr)
  588. {
  589. struct cgpu_info *avalon;
  590. struct avalon_info *info;
  591. struct work **works;
  592. int i;
  593. avalon = thr->cgpu;
  594. avalon->queued = 0;
  595. if (unlikely(!avalon->works))
  596. return;
  597. works = avalon->works;
  598. info = avalon_infos[avalon->device_id];
  599. for (i = 0; i < info->miner_count * 4; i++) {
  600. if (works[i]) {
  601. work_completed(avalon, works[i]);
  602. works[i] = NULL;
  603. }
  604. }
  605. }
  606. static void do_avalon_close(struct thr_info *thr)
  607. {
  608. struct avalon_result ar;
  609. struct cgpu_info *avalon = thr->cgpu;
  610. struct avalon_info *info = avalon_infos[avalon->device_id];
  611. avalon_free_work(thr);
  612. sleep(1);
  613. avalon_reset(avalon->device_fd, &ar);
  614. avalon_idle(avalon);
  615. avalon_close(avalon->device_fd);
  616. avalon->device_fd = -1;
  617. info->no_matching_work = 0;
  618. }
  619. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  620. {
  621. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  622. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  623. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  624. info->temp0 = ar->temp0;
  625. info->temp1 = ar->temp1;
  626. info->temp2 = ar->temp2;
  627. if (ar->temp0 & 0x80) {
  628. ar->temp0 &= 0x7f;
  629. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  630. }
  631. if (ar->temp1 & 0x80) {
  632. ar->temp1 &= 0x7f;
  633. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  634. }
  635. if (ar->temp2 & 0x80) {
  636. ar->temp2 &= 0x7f;
  637. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  638. }
  639. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  640. if (info->temp0 > info->temp_max)
  641. info->temp_max = info->temp0;
  642. if (info->temp1 > info->temp_max)
  643. info->temp_max = info->temp1;
  644. if (info->temp2 > info->temp_max)
  645. info->temp_max = info->temp2;
  646. }
  647. static inline void adjust_fan(struct avalon_info *info)
  648. {
  649. int temp_new;
  650. temp_new = info->temp_sum / info->temp_history_count;
  651. if (temp_new < 35) {
  652. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  653. info->temp_old = temp_new;
  654. } else if (temp_new > 55) {
  655. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  656. info->temp_old = temp_new;
  657. } else if (abs(temp_new - info->temp_old) >= 2) {
  658. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  659. info->temp_old = temp_new;
  660. }
  661. }
  662. /* We use a replacement algorithm to only remove references to work done from
  663. * the buffer when we need the extra space for new work. */
  664. static bool avalon_fill(struct cgpu_info *avalon)
  665. {
  666. int subid, slot, mc = avalon_infos[avalon->device_id]->miner_count;
  667. struct work *work;
  668. if (avalon->queued >= mc)
  669. return true;
  670. work = get_queued(avalon);
  671. if (unlikely(!work))
  672. return false;
  673. subid = avalon->queued++;
  674. work->subid = subid;
  675. slot = avalon->work_array * mc + subid;
  676. if (likely(avalon->works[slot]))
  677. work_completed(avalon, avalon->works[slot]);
  678. avalon->works[slot] = work;
  679. if (avalon->queued >= mc)
  680. return true;
  681. return false;
  682. }
  683. static void avalon_rotate_array(struct cgpu_info *avalon)
  684. {
  685. avalon->queued = 0;
  686. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  687. avalon->work_array = 0;
  688. }
  689. static int64_t avalon_scanhash(struct thr_info *thr)
  690. {
  691. struct cgpu_info *avalon;
  692. struct work **works;
  693. int fd, ret = AVA_GETS_OK, full;
  694. struct avalon_info *info;
  695. struct avalon_task at;
  696. struct avalon_result ar;
  697. int i;
  698. int avalon_get_work_count;
  699. int start_count, end_count;
  700. struct timeval tv_start, tv_finish, elapsed;
  701. uint32_t nonce;
  702. int64_t hash_count;
  703. static int first_try = 0;
  704. int result_wrong;
  705. avalon = thr->cgpu;
  706. works = avalon->works;
  707. info = avalon_infos[avalon->device_id];
  708. avalon_get_work_count = info->miner_count;
  709. if (unlikely(avalon->device_fd == -1)) {
  710. if (!avalon_prepare(thr)) {
  711. applog(LOG_ERR, "AVA%i: Comms error(open)",
  712. avalon->device_id);
  713. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  714. /* fail the device if the reopen attempt fails */
  715. return -1;
  716. }
  717. }
  718. fd = avalon->device_fd;
  719. #ifndef WIN32
  720. tcflush(fd, TCOFLUSH);
  721. #endif
  722. start_count = avalon->work_array * avalon_get_work_count;
  723. end_count = start_count + avalon_get_work_count;
  724. i = start_count;
  725. while (true) {
  726. avalon_init_task(&at, 0, 0, info->fan_pwm,
  727. info->timeout, info->asic_count,
  728. info->miner_count, 1, 0, info->frequency);
  729. avalon_create_task(&at, works[i]);
  730. ret = avalon_send_task(fd, &at, avalon);
  731. if (unlikely(ret == AVA_SEND_ERROR ||
  732. (ret == AVA_SEND_BUFFER_EMPTY &&
  733. (i + 1 == end_count) &&
  734. first_try))) {
  735. do_avalon_close(thr);
  736. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  737. avalon->device_id);
  738. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  739. first_try = 0;
  740. sleep(1);
  741. avalon_init(avalon);
  742. return 0; /* This should never happen */
  743. }
  744. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == end_count)) {
  745. first_try = 1;
  746. avalon_rotate_array(avalon);
  747. return 0xffffffff;
  748. }
  749. works[i]->blk.nonce = 0xffffffff;
  750. if (ret == AVA_SEND_BUFFER_FULL)
  751. break;
  752. i++;
  753. }
  754. if (unlikely(first_try))
  755. first_try = 0;
  756. elapsed.tv_sec = elapsed.tv_usec = 0;
  757. gettimeofday(&tv_start, NULL);
  758. result_wrong = 0;
  759. hash_count = 0;
  760. while (true) {
  761. full = avalon_buffer_full(fd);
  762. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  763. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  764. if (unlikely(full == AVA_BUFFER_EMPTY))
  765. break;
  766. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  767. if (unlikely(ret == AVA_GETS_ERROR)) {
  768. do_avalon_close(thr);
  769. applog(LOG_ERR,
  770. "AVA%i: Comms error(read)", avalon->device_id);
  771. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  772. return 0;
  773. }
  774. if (unlikely(ret == AVA_GETS_RESTART))
  775. break;
  776. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  777. timersub(&tv_finish, &tv_start, &elapsed);
  778. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  779. elapsed.tv_sec, elapsed.tv_usec);
  780. continue;
  781. }
  782. if (!avalon_decode_nonce(thr, &ar, &nonce)) {
  783. info->no_matching_work++;
  784. result_wrong++;
  785. if (unlikely(result_wrong >= avalon_get_work_count))
  786. break;
  787. if (opt_debug) {
  788. timersub(&tv_finish, &tv_start, &elapsed);
  789. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  790. " (%ld.%06lds)", info->no_matching_work,
  791. elapsed.tv_sec, elapsed.tv_usec);
  792. }
  793. continue;
  794. }
  795. hash_count += 0xffffffff;
  796. if (opt_debug) {
  797. timersub(&tv_finish, &tv_start, &elapsed);
  798. applog(LOG_DEBUG,
  799. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  800. "(%ld.%06lds)", nonce, hash_count,
  801. elapsed.tv_sec, elapsed.tv_usec);
  802. }
  803. }
  804. if (hash_count && avalon->results < AVALON_ARRAY_SIZE)
  805. avalon->results++;
  806. if (unlikely((result_wrong >= avalon_get_work_count) ||
  807. (!hash_count && ret != AVA_GETS_RESTART && --avalon->results < 0))) {
  808. /* Look for all invalid results, or consecutive failure
  809. * to generate any results suggesting the FPGA
  810. * controller has screwed up. */
  811. do_avalon_close(thr);
  812. applog(LOG_ERR,
  813. "AVA%i: FPGA controller messed up, %d wrong results",
  814. avalon->device_id, result_wrong);
  815. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  816. sleep(1);
  817. avalon_init(avalon);
  818. return 0;
  819. }
  820. avalon_rotate_array(avalon);
  821. if (hash_count) {
  822. record_temp_fan(info, &ar, &(avalon->temp));
  823. applog(LOG_INFO,
  824. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  825. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  826. info->fan0, info->fan1, info->fan2,
  827. info->temp0, info->temp1, info->temp2, info->temp_max);
  828. info->temp_history_index++;
  829. info->temp_sum += avalon->temp;
  830. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  831. info->temp_history_index, info->temp_history_count, info->temp_old);
  832. if (info->temp_history_index == info->temp_history_count) {
  833. adjust_fan(info);
  834. info->temp_history_index = 0;
  835. info->temp_sum = 0;
  836. }
  837. }
  838. /* This hashmeter is just a utility counter based on returned shares */
  839. return hash_count;
  840. }
  841. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  842. {
  843. struct api_data *root = NULL;
  844. struct avalon_info *info = avalon_infos[cgpu->device_id];
  845. root = api_add_int(root, "baud", &(info->baud), false);
  846. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  847. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  848. root = api_add_int(root, "timeout", &(info->timeout), false);
  849. root = api_add_int(root, "frequency", &(info->frequency), false);
  850. root = api_add_int(root, "fan1", &(info->fan0), false);
  851. root = api_add_int(root, "fan2", &(info->fan1), false);
  852. root = api_add_int(root, "fan3", &(info->fan2), false);
  853. root = api_add_int(root, "temp1", &(info->temp0), false);
  854. root = api_add_int(root, "temp2", &(info->temp1), false);
  855. root = api_add_int(root, "temp3", &(info->temp2), false);
  856. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  857. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  858. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  859. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  860. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  861. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  862. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  863. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  864. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  865. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  866. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  867. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  868. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  869. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  870. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  871. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  872. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  873. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  874. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  875. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  876. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  877. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  878. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  879. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  880. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  881. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  882. return root;
  883. }
  884. static void avalon_shutdown(struct thr_info *thr)
  885. {
  886. do_avalon_close(thr);
  887. }
  888. struct device_drv avalon_drv = {
  889. .drv_id = DRIVER_AVALON,
  890. .dname = "avalon",
  891. .name = "AVA",
  892. .drv_detect = avalon_detect,
  893. .thread_prepare = avalon_prepare,
  894. .hash_work = hash_queued_work,
  895. .queue_full = avalon_fill,
  896. .scanwork = avalon_scanhash,
  897. .get_api_stats = avalon_api_stats,
  898. .reinit_device = avalon_init,
  899. .thread_shutdown = avalon_shutdown,
  900. };