driver-avalon.c 23 KB

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  1. /*
  2. * Copyright 2012 Luke Dashjr
  3. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static struct timeval history_sec = { HISTORY_SEC, 0 };
  36. static const char *MODE_DEFAULT_STR = "default";
  37. static const char *MODE_SHORT_STR = "short";
  38. static const char *MODE_LONG_STR = "long";
  39. static const char *MODE_VALUE_STR = "value";
  40. static const char *MODE_UNKNOWN_STR = "unknown";
  41. static int option_offset = -1;
  42. static struct AVALON_INFO **avalon_info;
  43. struct device_api avalon_api;
  44. static int avalon_init_task(struct avalon_task *at, uint8_t reset, uint8_t ff,
  45. uint8_t fan, uint8_t timeout, uint8_t chip_num,
  46. uint8_t miner_num)
  47. {
  48. static bool first = true;
  49. if (!at)
  50. return -1;
  51. memset(at, 0, sizeof(struct avalon_task));
  52. if (reset) {
  53. at->reset = 1;
  54. first = true;
  55. }
  56. at->flush_fifo = (ff ? 1 : 0);
  57. at->fan_eft = (fan ? 1 : 0);
  58. if (timeout || chip_num || miner_num) {
  59. at->timer_eft = 1;
  60. }
  61. if (first && !at->reset) {
  62. at->fan_eft = 1;
  63. at->timer_eft = 1;
  64. first = false;
  65. }
  66. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  67. at->timeout_data = (timeout ? timeout : AVALON_DEFAULT_TIMEOUT);
  68. at->chip_num = (chip_num ? chip_num : AVALON_DEFAULT_CHIP_NUM);
  69. at->miner_num = (miner_num ? miner_num : AVALON_DEFAULT_MINER_NUM);
  70. at->nonce_elf = 1;
  71. return 0;
  72. }
  73. static inline void avalon_create_task(struct avalon_task *at,
  74. struct work *work)
  75. {
  76. memcpy(at->midstate, work->midstate, 32);
  77. memcpy(at->data, work->data + 64, 12);
  78. }
  79. static int avalon_send_task(int fd, const struct avalon_task *at)
  80. {
  81. size_t ret;
  82. int full;
  83. struct timespec p;
  84. uint8_t *buf;
  85. int nr_len;
  86. nr_len = AVALON_WRITE_SIZE + 4 * at->chip_num;
  87. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  88. if (!buf)
  89. return AVA_SEND_ERROR;
  90. memcpy(buf, at, AVALON_WRITE_SIZE);
  91. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  92. uint8_t tt = 0;
  93. tt = (buf[0] & 0x0f) << 4;
  94. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  95. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  96. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  97. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  98. buf[0] = tt;
  99. buf[4] = rev8(buf[4]);
  100. #endif
  101. if (opt_debug) {
  102. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  103. hexdump((uint8_t *)buf, nr_len);
  104. }
  105. ret = write(fd, buf, nr_len);
  106. free(buf);
  107. if (unlikely(ret != nr_len))
  108. return AVA_SEND_ERROR;
  109. p.tv_sec = 0;
  110. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  111. nanosleep(&p, NULL);
  112. full = avalon_buffer_full(fd);
  113. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  114. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  115. if (full == AVA_BUFFER_EMPTY)
  116. return AVA_SEND_BUFFER_EMPTY;
  117. return AVA_SEND_BUFFER_FULL;
  118. }
  119. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  120. struct thr_info *thr, struct timeval *tv_finish)
  121. {
  122. ssize_t ret = 0;
  123. int rc = 0;
  124. int read_amount = AVALON_READ_SIZE;
  125. bool first = true;
  126. /* Read reply 1 byte at a time to get earliest tv_finish */
  127. while (true) {
  128. ret = read(fd, buf, 1);
  129. if (ret < 0)
  130. return AVA_GETS_ERROR;
  131. if (first && tv_finish != NULL)
  132. gettimeofday(tv_finish, NULL);
  133. if (ret >= read_amount)
  134. return AVA_GETS_OK;
  135. if (ret > 0) {
  136. buf += ret;
  137. read_amount -= ret;
  138. first = false;
  139. continue;
  140. }
  141. rc++;
  142. if (rc >= read_count) {
  143. if (opt_debug) {
  144. applog(LOG_ERR,
  145. "Avalon: No data in %.2f seconds",
  146. (float)rc/(float)TIME_FACTOR);
  147. }
  148. return AVA_GETS_TIMEOUT;
  149. }
  150. if (thr && thr->work_restart) {
  151. if (opt_debug) {
  152. applog(LOG_ERR,
  153. "Avalon: Work restart at %.2f seconds",
  154. (float)(rc)/(float)TIME_FACTOR);
  155. }
  156. return AVA_GETS_RESTART;
  157. }
  158. }
  159. }
  160. static int avalon_get_result(int fd, struct avalon_result *ar,
  161. struct thr_info *thr, struct timeval *tv_finish)
  162. {
  163. struct cgpu_info *avalon;
  164. struct AVALON_INFO *info;
  165. uint8_t result[AVALON_READ_SIZE];
  166. int ret, read_count = 16;
  167. if (thr) {
  168. avalon = thr->cgpu;
  169. info = avalon_info[avalon->device_id];
  170. read_count = info->read_count;
  171. }
  172. memset(result, 0, AVALON_READ_SIZE);
  173. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  174. if (ret == AVA_GETS_OK) {
  175. if (opt_debug) {
  176. applog(LOG_DEBUG, "Avalon: get:");
  177. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  178. }
  179. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  180. }
  181. return ret;
  182. }
  183. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  184. uint32_t *nonce)
  185. {
  186. uint8_t data[12];
  187. int i;
  188. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  189. if (!work || !work[i])
  190. return -1;
  191. }
  192. *nonce = ar->nonce;
  193. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  194. *nonce = swab32(*nonce);
  195. #endif
  196. memcpy(data, ar->data, 12);
  197. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  198. if (!memcmp(data, work[i]->data + 64, 12))
  199. break;
  200. }
  201. applog(LOG_DEBUG, "Avalon: match to work: %d", i);
  202. if (i == AVALON_GET_WORK_COUNT)
  203. return -1;
  204. i -= 1;
  205. return i;
  206. }
  207. static int avalon_reset(int fd)
  208. {
  209. struct avalon_task at;
  210. struct avalon_result ar;
  211. uint8_t *buf;
  212. int ret, i;
  213. struct timespec p;
  214. avalon_init_task(&at,
  215. 1,
  216. 0,
  217. AVALON_DEFAULT_FAN_PWM,
  218. AVALON_DEFAULT_TIMEOUT,
  219. AVALON_DEFAULT_CHIP_NUM,
  220. AVALON_DEFAULT_MINER_NUM);
  221. ret = avalon_send_task(fd, &at);
  222. if (ret == AVA_SEND_ERROR)
  223. return 1;
  224. avalon_get_result(fd, &ar, NULL, NULL);
  225. buf = (uint8_t *)&ar;
  226. for (i = 0; i < 11; i++)
  227. if (buf[i] != 0)
  228. break;
  229. /* FIXME: add more avalon info base on return */
  230. if (i != 11) {
  231. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  232. return 1;
  233. }
  234. p.tv_sec = 1;
  235. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  236. nanosleep(&p, NULL);
  237. applog(LOG_ERR, "Avalon: Reset succeeded");
  238. return 0;
  239. }
  240. static void do_avalon_close(struct thr_info *thr)
  241. {
  242. struct cgpu_info *avalon = thr->cgpu;
  243. avalon_close(avalon->device_fd);
  244. avalon->device_fd = -1;
  245. }
  246. static const char *timing_mode_str(enum timing_mode timing_mode)
  247. {
  248. switch(timing_mode) {
  249. case MODE_DEFAULT:
  250. return MODE_DEFAULT_STR;
  251. case MODE_SHORT:
  252. return MODE_SHORT_STR;
  253. case MODE_LONG:
  254. return MODE_LONG_STR;
  255. case MODE_VALUE:
  256. return MODE_VALUE_STR;
  257. default:
  258. return MODE_UNKNOWN_STR;
  259. }
  260. }
  261. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  262. {
  263. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  264. double Hs;
  265. char buf[BUFSIZ+1];
  266. char *ptr, *comma, *eq;
  267. size_t max;
  268. int i;
  269. if (opt_icarus_timing == NULL)
  270. buf[0] = '\0';
  271. else {
  272. ptr = opt_icarus_timing;
  273. for (i = 0; i < this_option_offset; i++) {
  274. comma = strchr(ptr, ',');
  275. if (comma == NULL)
  276. break;
  277. ptr = comma + 1;
  278. }
  279. comma = strchr(ptr, ',');
  280. if (comma == NULL)
  281. max = strlen(ptr);
  282. else
  283. max = comma - ptr;
  284. if (max > BUFSIZ)
  285. max = BUFSIZ;
  286. strncpy(buf, ptr, max);
  287. buf[max] = '\0';
  288. }
  289. info->Hs = 0;
  290. info->read_count = 0;
  291. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  292. info->Hs = AVALON_HASH_TIME;
  293. info->read_count = AVALON_READ_COUNT_TIMING;
  294. info->timing_mode = MODE_SHORT;
  295. info->do_avalon_timing = true;
  296. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  297. info->Hs = AVALON_HASH_TIME;
  298. info->read_count = AVALON_READ_COUNT_TIMING;
  299. info->timing_mode = MODE_LONG;
  300. info->do_avalon_timing = true;
  301. } else if ((Hs = atof(buf)) != 0) {
  302. info->Hs = Hs / NANOSEC;
  303. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  304. if ((eq = strchr(buf, '=')) != NULL)
  305. info->read_count = atoi(eq+1);
  306. if (info->read_count < 1)
  307. info->read_count =
  308. (int)(info->fullnonce * TIME_FACTOR) - 1;
  309. if (unlikely(info->read_count < 1))
  310. info->read_count = 1;
  311. info->timing_mode = MODE_VALUE;
  312. info->do_avalon_timing = false;
  313. } else {
  314. /* Anything else in buf just uses DEFAULT mode */
  315. info->Hs = AVALON_HASH_TIME;
  316. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  317. if ((eq = strchr(buf, '=')) != NULL)
  318. info->read_count = atoi(eq+1);
  319. if (info->read_count < 1)
  320. info->read_count =
  321. (int)(info->fullnonce * TIME_FACTOR) - 1;
  322. info->timing_mode = MODE_DEFAULT;
  323. info->do_avalon_timing = false;
  324. }
  325. info->min_data_count = MIN_DATA_COUNT;
  326. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  327. avalon->device_id, timing_mode_str(info->timing_mode),
  328. info->read_count, info->Hs);
  329. }
  330. static uint32_t mask(int work_division)
  331. {
  332. char err_buf[BUFSIZ+1];
  333. uint32_t nonce_mask = 0x7fffffff;
  334. switch (work_division) {
  335. case 1:
  336. nonce_mask = 0xffffffff;
  337. break;
  338. case 2:
  339. nonce_mask = 0x7fffffff;
  340. break;
  341. case 4:
  342. nonce_mask = 0x3fffffff;
  343. break;
  344. case 8:
  345. nonce_mask = 0x1fffffff;
  346. break;
  347. default:
  348. sprintf(err_buf,
  349. "Invalid2 avalon-options for work_division (%d)"
  350. " must be 1, 2, 4 or 8", work_division);
  351. quit(1, err_buf);
  352. }
  353. return nonce_mask;
  354. }
  355. static void get_options(int this_option_offset, int *baud, int *work_division,
  356. int *asic_count)
  357. {
  358. char err_buf[BUFSIZ+1];
  359. char buf[BUFSIZ+1];
  360. char *ptr, *comma, *colon, *colon2;
  361. size_t max;
  362. int i, tmp;
  363. if (opt_icarus_options == NULL)
  364. buf[0] = '\0';
  365. else {
  366. ptr = opt_icarus_options;
  367. for (i = 0; i < this_option_offset; i++) {
  368. comma = strchr(ptr, ',');
  369. if (comma == NULL)
  370. break;
  371. ptr = comma + 1;
  372. }
  373. comma = strchr(ptr, ',');
  374. if (comma == NULL)
  375. max = strlen(ptr);
  376. else
  377. max = comma - ptr;
  378. if (max > BUFSIZ)
  379. max = BUFSIZ;
  380. strncpy(buf, ptr, max);
  381. buf[max] = '\0';
  382. }
  383. *baud = AVALON_IO_SPEED;
  384. *work_division = 2;
  385. *asic_count = 2;
  386. if (*buf) {
  387. colon = strchr(buf, ':');
  388. if (colon)
  389. *(colon++) = '\0';
  390. if (*buf) {
  391. tmp = atoi(buf);
  392. switch (tmp) {
  393. case 115200:
  394. *baud = 115200;
  395. break;
  396. case 57600:
  397. *baud = 57600;
  398. break;
  399. default:
  400. sprintf(err_buf,
  401. "Invalid avalon-options for baud (%s) "
  402. "must be 115200 or 57600", buf);
  403. quit(1, err_buf);
  404. }
  405. }
  406. if (colon && *colon) {
  407. colon2 = strchr(colon, ':');
  408. if (colon2)
  409. *(colon2++) = '\0';
  410. if (*colon) {
  411. tmp = atoi(colon);
  412. if (tmp == 1 || tmp == 2 ||
  413. tmp == 4 || tmp == 8) {
  414. *work_division = tmp;
  415. *asic_count = tmp;
  416. } else {
  417. sprintf(err_buf,
  418. "Invalid avalon-options for "
  419. "work_division (%s) must be 1,"
  420. " 2, 4 or 8", colon);
  421. quit(1, err_buf);
  422. }
  423. }
  424. if (colon2 && *colon2) {
  425. tmp = atoi(colon2);
  426. if (tmp > 0 && tmp <= *work_division)
  427. *asic_count = tmp;
  428. else {
  429. sprintf(err_buf,
  430. "Invalid avalon-options for "
  431. "asic_count (%s) must be >0 "
  432. "and <=work_division (%d)",
  433. colon2, *work_division);
  434. quit(1, err_buf);
  435. }
  436. }
  437. }
  438. }
  439. }
  440. static bool avalon_detect_one(const char *devpath)
  441. {
  442. struct AVALON_INFO *info;
  443. int fd, ret;
  444. int baud, work_division, asic_count;
  445. int this_option_offset = ++option_offset;
  446. get_options(this_option_offset, &baud, &work_division, &asic_count);
  447. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  448. fd = avalon_open2(devpath, baud, true);
  449. if (unlikely(fd == -1)) {
  450. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  451. return false;
  452. }
  453. ret = avalon_reset(fd);
  454. avalon_close(fd);
  455. if (ret)
  456. return false;
  457. /* We have a real Avalon! */
  458. struct cgpu_info *avalon;
  459. avalon = calloc(1, sizeof(struct cgpu_info));
  460. avalon->api = &avalon_api;
  461. avalon->device_path = strdup(devpath);
  462. avalon->device_fd = -1;
  463. avalon->threads = AVALON_MINER_THREADS;
  464. add_cgpu(avalon);
  465. avalon_info = realloc(avalon_info,
  466. sizeof(struct AVALON_INFO *) *
  467. (total_devices + 1));
  468. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  469. devpath, avalon->device_id);
  470. applog(LOG_DEBUG,
  471. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  472. avalon->device_id, baud, work_division, asic_count);
  473. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  474. malloc(sizeof(struct AVALON_INFO));
  475. if (unlikely(!(avalon_info[avalon->device_id])))
  476. quit(1, "Failed to malloc AVALON_INFO");
  477. info = avalon_info[avalon->device_id];
  478. memset(info, 0, sizeof(struct AVALON_INFO));
  479. info->baud = baud;
  480. info->work_division = work_division;
  481. info->asic_count = asic_count;
  482. info->nonce_mask = mask(work_division);
  483. set_timing_mode(this_option_offset, avalon);
  484. return true;
  485. }
  486. static inline void avalon_detect()
  487. {
  488. serial_detect(&avalon_api, avalon_detect_one);
  489. }
  490. static bool avalon_prepare(struct thr_info *thr)
  491. {
  492. struct cgpu_info *avalon = thr->cgpu;
  493. struct timeval now;
  494. int fd;
  495. avalon->device_fd = -1;
  496. fd = avalon_open(avalon->device_path,
  497. avalon_info[avalon->device_id]->baud);
  498. if (unlikely(fd == -1)) {
  499. applog(LOG_ERR, "Avalon: Failed to open on %s",
  500. avalon->device_path);
  501. return false;
  502. }
  503. avalon_reset(fd);
  504. avalon->device_fd = fd;
  505. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  506. gettimeofday(&now, NULL);
  507. get_datestamp(avalon->init, &now);
  508. return true;
  509. }
  510. static void avalon_free_work(struct work **work)
  511. {
  512. int i;
  513. if (!work)
  514. return;
  515. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  516. if (work[i])
  517. free_work(work[i++]);
  518. }
  519. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  520. __maybe_unused int64_t max_nonce)
  521. {
  522. struct cgpu_info *avalon;
  523. int fd;
  524. int ret;
  525. int full;
  526. struct AVALON_INFO *info;
  527. struct avalon_task at;
  528. struct avalon_result ar;
  529. static struct work *bulk0[3] = {NULL, NULL, NULL};
  530. static struct work *bulk1[3] = {NULL, NULL, NULL};
  531. static struct work *bulk2[3] = {NULL, NULL, NULL};
  532. struct work **work = NULL;
  533. int i, work_i0, work_i1, work_i2;
  534. uint32_t nonce;
  535. int64_t hash_count;
  536. int read_count;
  537. int count;
  538. struct timeval tv_start, tv_finish, elapsed;
  539. struct timeval tv_history_start, tv_history_finish;
  540. double Ti, Xi;
  541. int curr_hw_errors;
  542. bool was_hw_error;
  543. struct AVALON_HISTORY *history0, *history;
  544. double Hs, W, fullnonce;
  545. int64_t estimate_hashes;
  546. uint32_t values;
  547. int64_t hash_count_range;
  548. avalon = thr->cgpu;
  549. info = avalon_info[avalon->device_id];
  550. if (avalon->device_fd == -1)
  551. if (!avalon_prepare(thr)) {
  552. applog(LOG_ERR, "AVA%i: Comms error",
  553. avalon->device_id);
  554. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  555. /* fail the device if the reopen attempt fails */
  556. return -1;
  557. }
  558. fd = avalon->device_fd;
  559. #ifndef WIN32
  560. tcflush(fd, TCOFLUSH);
  561. #endif
  562. work = bulk_work;
  563. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  564. bulk0[i] = bulk1[i];
  565. bulk1[i] = bulk2[i];
  566. bulk2[i] = bulk_work[i];
  567. }
  568. i = 0;
  569. while (true) {
  570. avalon_init_default_task(&at);
  571. avalon_create_task(&at, work[i++]);
  572. ret = avalon_send_task(fd, &at);
  573. if (ret == AVA_SEND_ERROR) {
  574. avalon_free_work(bulk0);
  575. avalon_free_work(bulk1);
  576. avalon_free_work(bulk2);
  577. do_avalon_close(thr);
  578. applog(LOG_ERR, "AVA%i: Comms error",
  579. avalon->device_id);
  580. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  581. return 0; /* This should never happen */
  582. }
  583. if (ret == AVA_SEND_BUFFER_FULL) {
  584. break;
  585. }
  586. if (i == AVALON_GET_WORK_COUNT &&
  587. ret != AVA_SEND_BUFFER_FULL) {
  588. return 0xffffffff;
  589. }
  590. }
  591. elapsed.tv_sec = elapsed.tv_usec = 0;
  592. gettimeofday(&tv_start, NULL);
  593. /* count may != AVALON_GET_WORK_COUNT */
  594. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  595. work[i]->blk.nonce = 0xffffffff;
  596. work_i0 = work_i1 = work_i2 = -1;
  597. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  598. if (ret == AVA_GETS_ERROR) {
  599. avalon_free_work(bulk0);
  600. avalon_free_work(bulk1);
  601. avalon_free_work(bulk2);
  602. do_avalon_close(thr);
  603. applog(LOG_ERR,
  604. "AVA%i: Comms error", avalon->device_id);
  605. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  606. return 0;
  607. }
  608. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  609. if (work_i0 < 0)
  610. applog(LOG_DEBUG,
  611. "Avalon: can not match nonce to bulk0");
  612. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  613. if (work_i1 < 0)
  614. applog(LOG_DEBUG,
  615. "Avalon: can not match nonce to bulk1");
  616. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  617. if (work_i2 < 0)
  618. applog(LOG_DEBUG,
  619. "Avalon: can not match nonce to bulk2");
  620. /* aborted before becoming idle, get new work */
  621. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  622. timersub(&tv_finish, &tv_start, &elapsed);
  623. estimate_hashes = ((double)(elapsed.tv_sec) +
  624. ((double)(elapsed.tv_usec)) /
  625. ((double)1000000)) / info->Hs;
  626. /* If Serial-USB delay allowed the full nonce range to
  627. * complete it can't have done more than a full nonce
  628. */
  629. if (unlikely(estimate_hashes > 0xffffffff))
  630. estimate_hashes = 0xffffffff;
  631. applog(LOG_DEBUG,
  632. "Avalon: no nonce = 0x%08llx hashes "
  633. "(%ld.%06lds)",
  634. estimate_hashes, elapsed.tv_sec,
  635. elapsed.tv_usec);
  636. avalon_free_work(bulk0);
  637. continue;
  638. //return estimate_hashes;
  639. }
  640. curr_hw_errors = avalon->hw_errors;
  641. if (work_i0 >= 0)
  642. submit_nonce(thr, bulk0[work_i0], nonce);
  643. if (work_i1 >= 0)
  644. submit_nonce(thr, bulk1[work_i1], nonce);
  645. if (work_i2 >= 0)
  646. submit_nonce(thr, bulk2[work_i2], nonce);
  647. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  648. /* Force a USB close/reopen on any hw error */
  649. if (was_hw_error)
  650. do_avalon_close(thr);
  651. hash_count = (nonce & info->nonce_mask);
  652. hash_count++;
  653. hash_count *= info->asic_count;
  654. full = avalon_buffer_full(fd);
  655. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  656. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  657. if (full == AVA_BUFFER_EMPTY) {
  658. applog(LOG_DEBUG, "Avalon: Finished bulk task!");
  659. avalon_free_work(bulk0);
  660. }
  661. }
  662. avalon_free_work(bulk0);
  663. if (opt_debug || info->do_avalon_timing)
  664. timersub(&tv_finish, &tv_start, &elapsed);
  665. if (opt_debug) {
  666. applog(LOG_DEBUG,
  667. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  668. "(%ld.%06lds)",
  669. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  670. }
  671. /* ignore possible end condition values ... and hw errors */
  672. if (info->do_avalon_timing
  673. && !was_hw_error
  674. && ((nonce & info->nonce_mask) > END_CONDITION)
  675. && ((nonce & info->nonce_mask) <
  676. (info->nonce_mask & ~END_CONDITION))) {
  677. gettimeofday(&tv_history_start, NULL);
  678. history0 = &(info->history[0]);
  679. if (history0->values == 0)
  680. timeradd(&tv_start, &history_sec, &(history0->finish));
  681. Ti = (double)(elapsed.tv_sec)
  682. + ((double)(elapsed.tv_usec))/((double)1000000)
  683. - ((double)AVALON_READ_TIME(info->baud));
  684. Xi = (double)hash_count;
  685. history0->sumXiTi += Xi * Ti;
  686. history0->sumXi += Xi;
  687. history0->sumTi += Ti;
  688. history0->sumXi2 += Xi * Xi;
  689. history0->values++;
  690. if (history0->hash_count_max < hash_count)
  691. history0->hash_count_max = hash_count;
  692. if (history0->hash_count_min > hash_count ||
  693. history0->hash_count_min == 0)
  694. history0->hash_count_min = hash_count;
  695. if (history0->values >= info->min_data_count
  696. && timercmp(&tv_start, &(history0->finish), >)) {
  697. for (i = INFO_HISTORY; i > 0; i--)
  698. memcpy(&(info->history[i]),
  699. &(info->history[i-1]),
  700. sizeof(struct AVALON_HISTORY));
  701. /* Init history0 to zero for summary calculation */
  702. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  703. /* We just completed a history data set
  704. * So now recalc read_count based on the
  705. * whole history thus we will
  706. * initially get more accurate until it
  707. * completes INFO_HISTORY
  708. * total data sets */
  709. count = 0;
  710. for (i = 1 ; i <= INFO_HISTORY; i++) {
  711. history = &(info->history[i]);
  712. if (history->values >= MIN_DATA_COUNT) {
  713. count++;
  714. history0->sumXiTi += history->sumXiTi;
  715. history0->sumXi += history->sumXi;
  716. history0->sumTi += history->sumTi;
  717. history0->sumXi2 += history->sumXi2;
  718. history0->values += history->values;
  719. if (history0->hash_count_max < history->hash_count_max)
  720. history0->hash_count_max = history->hash_count_max;
  721. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  722. history0->hash_count_min = history->hash_count_min;
  723. }
  724. }
  725. /* All history data */
  726. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  727. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  728. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  729. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  730. values = history0->values;
  731. /* Initialise history0 to zero for next data set */
  732. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  733. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  734. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  735. info->Hs = Hs;
  736. info->read_count = read_count;
  737. info->fullnonce = fullnonce;
  738. info->count = count;
  739. info->W = W;
  740. info->values = values;
  741. info->hash_count_range = hash_count_range;
  742. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  743. info->min_data_count *= 2;
  744. else if (info->timing_mode == MODE_SHORT)
  745. info->do_avalon_timing = false;
  746. /* applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);*/
  747. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  748. avalon->device_id, Hs, W, read_count, fullnonce);
  749. }
  750. info->history_count++;
  751. gettimeofday(&tv_history_finish, NULL);
  752. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  753. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  754. }
  755. return hash_count;
  756. }
  757. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  758. {
  759. struct api_data *root = NULL;
  760. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  761. /* Warning, access to these is not locked - but we don't really
  762. * care since hashing performance is way more important than
  763. * locking access to displaying API debug 'stats'
  764. * If locking becomes an issue for any of them, use copy_data=true also */
  765. root = api_add_int(root, "read_count", &(info->read_count), false);
  766. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  767. root = api_add_int(root, "count", &(info->count), false);
  768. root = api_add_hs(root, "Hs", &(info->Hs), false);
  769. root = api_add_double(root, "W", &(info->W), false);
  770. root = api_add_uint(root, "total_values", &(info->values), false);
  771. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  772. root = api_add_uint64(root, "history_count", &(info->history_count),
  773. false);
  774. root = api_add_timeval(root, "history_time", &(info->history_time),
  775. false);
  776. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  777. false);
  778. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  779. false);
  780. root = api_add_const(root, "timing_mode",
  781. timing_mode_str(info->timing_mode), false);
  782. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  783. false);
  784. root = api_add_int(root, "baud", &(info->baud), false);
  785. root = api_add_int(root, "work_division", &(info->work_division),
  786. false);
  787. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  788. return root;
  789. }
  790. static void avalon_shutdown(struct thr_info *thr)
  791. {
  792. do_avalon_close(thr);
  793. }
  794. struct device_api avalon_api = {
  795. .dname = "avalon",
  796. .name = "AVA",
  797. .api_detect = avalon_detect,
  798. .thread_prepare = avalon_prepare,
  799. .scanhash_queue = avalon_scanhash,
  800. .get_api_stats = avalon_api_stats,
  801. .thread_shutdown = avalon_shutdown,
  802. };