driver-avalon.c 26 KB

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  1. /*
  2. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Luke Dashjr
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static int option_offset = -1;
  36. struct avalon_info **avalon_info;
  37. struct device_api avalon_api;
  38. static int avalon_init_task(struct avalon_task *at,
  39. uint8_t reset, uint8_t ff, uint8_t fan,
  40. uint8_t timeout, uint8_t asic_num,
  41. uint8_t miner_num, uint8_t nonce_elf,
  42. uint8_t gate_miner, int frequency)
  43. {
  44. uint8_t *buf;
  45. static bool first = true;
  46. if (unlikely(!at))
  47. return -1;
  48. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  49. return -1;
  50. memset(at, 0, sizeof(struct avalon_task));
  51. if (unlikely(reset)) {
  52. at->reset = 1;
  53. at->fan_eft = 1;
  54. at->timer_eft = 1;
  55. first = true;
  56. }
  57. at->flush_fifo = (ff ? 1 : 0);
  58. at->fan_eft = (fan ? 1 : 0);
  59. if (unlikely(first && !at->reset)) {
  60. at->fan_eft = 1;
  61. at->timer_eft = 1;
  62. first = false;
  63. }
  64. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  65. at->timeout_data = timeout;
  66. at->asic_num = asic_num;
  67. at->miner_num = miner_num;
  68. at->nonce_elf = nonce_elf;
  69. at->gate_miner_elf = 1;
  70. at->asic_pll = 1;
  71. if (unlikely(gate_miner)) {
  72. at-> gate_miner = 1;
  73. at->asic_pll = 0;
  74. }
  75. buf = (uint8_t *)at;
  76. buf[5] = 0x00;
  77. buf[8] = 0x74;
  78. buf[9] = 0x01;
  79. buf[10] = 0x00;
  80. buf[11] = 0x00;
  81. if (frequency == 256) {
  82. buf[6] = 0x03;
  83. buf[7] = 0x08;
  84. } else if (frequency == 270) {
  85. buf[6] = 0x73;
  86. buf[7] = 0x08;
  87. } else if (frequency == 282) {
  88. buf[6] = 0xd3;
  89. buf[7] = 0x08;
  90. } else if (frequency == 300) {
  91. buf[6] = 0x63;
  92. buf[7] = 0x09;
  93. }
  94. return 0;
  95. }
  96. static inline void avalon_create_task(struct avalon_task *at,
  97. struct work *work)
  98. {
  99. memcpy(at->midstate, work->midstate, 32);
  100. memcpy(at->data, work->data + 64, 12);
  101. }
  102. static int avalon_send_task(int fd, const struct avalon_task *at,
  103. struct cgpu_info *avalon)
  104. {
  105. size_t ret;
  106. int full;
  107. struct timespec p;
  108. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  109. size_t nr_len;
  110. struct avalon_info *info;
  111. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  112. uint32_t nonce_range;
  113. int i;
  114. if (at->nonce_elf)
  115. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  116. else
  117. nr_len = AVALON_WRITE_SIZE;
  118. memcpy(buf, at, AVALON_WRITE_SIZE);
  119. if (at->nonce_elf) {
  120. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  121. for (i = 0; i < at->asic_num; i++) {
  122. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  123. (i * nonce_range & 0xff000000) >> 24;
  124. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  125. (i * nonce_range & 0x00ff0000) >> 16;
  126. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  127. (i * nonce_range & 0x0000ff00) >> 8;
  128. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  129. (i * nonce_range & 0x000000ff) >> 0;
  130. }
  131. }
  132. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  133. uint8_t tt = 0;
  134. tt = (buf[0] & 0x0f) << 4;
  135. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  136. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  137. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  138. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  139. buf[0] = tt;
  140. tt = (buf[4] & 0x0f) << 4;
  141. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  142. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  143. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  144. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  145. buf[4] = tt;
  146. #endif
  147. if (likely(avalon)) {
  148. info = avalon_info[avalon->device_id];
  149. delay = nr_len * 10 * 1000000000ULL;
  150. delay = delay / info->baud;
  151. }
  152. if (at->reset)
  153. nr_len = 1;
  154. if (opt_debug) {
  155. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  156. hexdump((uint8_t *)buf, nr_len);
  157. }
  158. ret = write(fd, buf, nr_len);
  159. if (unlikely(ret != nr_len))
  160. return AVA_SEND_ERROR;
  161. p.tv_sec = 0;
  162. p.tv_nsec = (long)delay + 4000000;
  163. nanosleep(&p, NULL);
  164. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  165. full = avalon_buffer_full(fd);
  166. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  167. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  168. if (unlikely(full == AVA_BUFFER_FULL))
  169. return AVA_SEND_BUFFER_FULL;
  170. return AVA_SEND_BUFFER_EMPTY;
  171. }
  172. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  173. struct thr_info *thr, struct timeval *tv_finish)
  174. {
  175. ssize_t ret = 0;
  176. int rc = 0;
  177. int read_amount = AVALON_READ_SIZE;
  178. bool first = true;
  179. /* Read reply 1 byte at a time to get earliest tv_finish */
  180. while (true) {
  181. ret = read(fd, buf, 1);
  182. if (ret < 0)
  183. return AVA_GETS_ERROR;
  184. if (first && tv_finish != NULL)
  185. gettimeofday(tv_finish, NULL);
  186. if (ret >= read_amount)
  187. return AVA_GETS_OK;
  188. if (ret > 0) {
  189. buf += ret;
  190. read_amount -= ret;
  191. first = false;
  192. continue;
  193. }
  194. rc++;
  195. if (rc >= read_count) {
  196. if (opt_debug) {
  197. applog(LOG_WARNING,
  198. "Avalon: No data in %.2f seconds",
  199. (float)rc/(float)AVALON_TIME_FACTOR);
  200. }
  201. return AVA_GETS_TIMEOUT;
  202. }
  203. if (thr && thr->work_restart) {
  204. if (opt_debug) {
  205. applog(LOG_WARNING,
  206. "Avalon: Work restart at %.2f seconds",
  207. (float)(rc)/(float)AVALON_TIME_FACTOR);
  208. }
  209. return AVA_GETS_RESTART;
  210. }
  211. }
  212. }
  213. static int avalon_get_result(int fd, struct avalon_result *ar,
  214. struct thr_info *thr, struct timeval *tv_finish)
  215. {
  216. struct cgpu_info *avalon;
  217. struct avalon_info *info;
  218. uint8_t result[AVALON_READ_SIZE];
  219. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  220. if (likely(thr)) {
  221. avalon = thr->cgpu;
  222. info = avalon_info[avalon->device_id];
  223. read_count = info->read_count;
  224. }
  225. memset(result, 0, AVALON_READ_SIZE);
  226. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  227. if (ret == AVA_GETS_OK) {
  228. if (opt_debug) {
  229. applog(LOG_DEBUG, "Avalon: get:");
  230. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  231. }
  232. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  233. }
  234. return ret;
  235. }
  236. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  237. struct avalon_result *ar, uint32_t *nonce)
  238. {
  239. struct cgpu_info *avalon;
  240. struct avalon_info *info;
  241. int avalon_get_work_count, i;
  242. if (unlikely(!work))
  243. return -1;
  244. avalon = thr->cgpu;
  245. info = avalon_info[avalon->device_id];
  246. avalon_get_work_count = info->miner_count;
  247. for (i = 0; i < avalon_get_work_count; i++) {
  248. if (work[i] &&
  249. !memcmp(ar->data, work[i]->data + 64, 12) &&
  250. !memcmp(ar->midstate, work[i]->midstate, 32))
  251. break;
  252. }
  253. if (i == avalon_get_work_count)
  254. return -1;
  255. info->matching_work[i]++;
  256. *nonce = htole32(ar->nonce);
  257. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  258. info->matching_work[i]);
  259. return i;
  260. }
  261. static int avalon_reset(int fd, struct avalon_result *ar)
  262. {
  263. struct avalon_task at;
  264. uint8_t *buf;
  265. int ret, i = 0;
  266. struct timespec p;
  267. avalon_init_task(&at, 1, 0,
  268. AVALON_DEFAULT_FAN_MAX_PWM,
  269. AVALON_DEFAULT_TIMEOUT,
  270. AVALON_DEFAULT_ASIC_NUM,
  271. AVALON_DEFAULT_MINER_NUM,
  272. 0, 0,
  273. AVALON_DEFAULT_FREQUENCY);
  274. ret = avalon_send_task(fd, &at, NULL);
  275. if (ret == AVA_SEND_ERROR)
  276. return 1;
  277. avalon_get_result(fd, ar, NULL, NULL);
  278. buf = (uint8_t *)ar;
  279. if (buf[0] == 0)
  280. buf = (uint8_t *)(ar + 1);
  281. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  282. buf[2] == 0xAA && buf[3] == 0x55) {
  283. for (i = 4; i < 11; i++)
  284. if (buf[i] != 0)
  285. break;
  286. }
  287. p.tv_sec = 0;
  288. p.tv_nsec = AVALON_RESET_PITCH;
  289. nanosleep(&p, NULL);
  290. if (i != 11) {
  291. applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
  292. " (%d: %02x %02x %02x %02x)",
  293. i, buf[0], buf[1], buf[2], buf[3]);
  294. /* FIXME: return 1; */
  295. } else
  296. applog(LOG_WARNING, "Avalon: Reset succeeded");
  297. return 0;
  298. }
  299. static void avalon_idle(struct cgpu_info *avalon)
  300. {
  301. int i, ret;
  302. struct avalon_task at;
  303. int fd = avalon->device_fd;
  304. struct avalon_info *info = avalon_info[avalon->device_id];
  305. int avalon_get_work_count = info->miner_count;
  306. i = 0;
  307. while (true) {
  308. avalon_init_task(&at, 0, 0, info->fan_pwm,
  309. info->timeout, info->asic_count,
  310. info->miner_count, 1, 1, info->frequency);
  311. ret = avalon_send_task(fd, &at, avalon);
  312. if (unlikely(ret == AVA_SEND_ERROR ||
  313. (ret == AVA_SEND_BUFFER_EMPTY &&
  314. (i + 1 == avalon_get_work_count * 2)))) {
  315. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  316. return;
  317. }
  318. if (i + 1 == avalon_get_work_count * 2)
  319. break;
  320. if (ret == AVA_SEND_BUFFER_FULL)
  321. break;
  322. i++;
  323. }
  324. applog(LOG_ERR, "Avalon: Goto idle mode");
  325. }
  326. static void get_options(int this_option_offset, int *baud, int *miner_count,
  327. int *asic_count, int *timeout, int *frequency)
  328. {
  329. char err_buf[BUFSIZ+1];
  330. char buf[BUFSIZ+1];
  331. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  332. size_t max;
  333. int i, tmp;
  334. if (opt_avalon_options == NULL)
  335. buf[0] = '\0';
  336. else {
  337. ptr = opt_avalon_options;
  338. for (i = 0; i < this_option_offset; i++) {
  339. comma = strchr(ptr, ',');
  340. if (comma == NULL)
  341. break;
  342. ptr = comma + 1;
  343. }
  344. comma = strchr(ptr, ',');
  345. if (comma == NULL)
  346. max = strlen(ptr);
  347. else
  348. max = comma - ptr;
  349. if (max > BUFSIZ)
  350. max = BUFSIZ;
  351. strncpy(buf, ptr, max);
  352. buf[max] = '\0';
  353. }
  354. *baud = AVALON_IO_SPEED;
  355. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  356. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  357. *timeout = AVALON_DEFAULT_TIMEOUT;
  358. *frequency = AVALON_DEFAULT_FREQUENCY;
  359. if (!(*buf))
  360. return;
  361. colon = strchr(buf, ':');
  362. if (colon)
  363. *(colon++) = '\0';
  364. tmp = atoi(buf);
  365. switch (tmp) {
  366. case 115200:
  367. *baud = 115200;
  368. break;
  369. case 57600:
  370. *baud = 57600;
  371. break;
  372. case 38400:
  373. *baud = 38400;
  374. break;
  375. case 19200:
  376. *baud = 19200;
  377. break;
  378. default:
  379. sprintf(err_buf,
  380. "Invalid avalon-options for baud (%s) "
  381. "must be 115200, 57600, 38400 or 19200", buf);
  382. quit(1, err_buf);
  383. }
  384. if (colon && *colon) {
  385. colon2 = strchr(colon, ':');
  386. if (colon2)
  387. *(colon2++) = '\0';
  388. if (*colon) {
  389. tmp = atoi(colon);
  390. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  391. *miner_count = tmp;
  392. } else {
  393. sprintf(err_buf,
  394. "Invalid avalon-options for "
  395. "miner_count (%s) must be 1 ~ %d",
  396. colon, AVALON_DEFAULT_MINER_NUM);
  397. quit(1, err_buf);
  398. }
  399. }
  400. if (colon2 && *colon2) {
  401. colon3 = strchr(colon2, ':');
  402. if (colon3)
  403. *(colon3++) = '\0';
  404. tmp = atoi(colon2);
  405. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  406. *asic_count = tmp;
  407. else {
  408. sprintf(err_buf,
  409. "Invalid avalon-options for "
  410. "asic_count (%s) must be 1 ~ %d",
  411. colon2, AVALON_DEFAULT_ASIC_NUM);
  412. quit(1, err_buf);
  413. }
  414. if (colon3 && *colon3) {
  415. colon4 = strchr(colon3, ':');
  416. if (colon4)
  417. *(colon4++) = '\0';
  418. tmp = atoi(colon3);
  419. if (tmp > 0 && tmp <= 0xff)
  420. *timeout = tmp;
  421. else {
  422. sprintf(err_buf,
  423. "Invalid avalon-options for "
  424. "timeout (%s) must be 1 ~ %d",
  425. colon3, 0xff);
  426. quit(1, err_buf);
  427. }
  428. if (colon4 && *colon4) {
  429. tmp = atoi(colon4);
  430. switch (tmp) {
  431. case 256:
  432. case 270:
  433. case 282:
  434. case 300:
  435. *frequency = tmp;
  436. break;
  437. default:
  438. sprintf(err_buf,
  439. "Invalid avalon-options for "
  440. "frequency must be 256/270/282/300");
  441. quit(1, err_buf);
  442. }
  443. }
  444. }
  445. }
  446. }
  447. }
  448. static bool avalon_detect_one(const char *devpath)
  449. {
  450. struct avalon_info *info;
  451. struct avalon_result ar;
  452. int fd, ret;
  453. int baud, miner_count, asic_count, timeout, frequency = 0;
  454. struct cgpu_info *avalon;
  455. int this_option_offset = ++option_offset;
  456. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  457. &timeout, &frequency);
  458. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  459. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  460. devpath, baud, miner_count, asic_count, timeout, frequency);
  461. fd = avalon_open2(devpath, baud, true);
  462. if (unlikely(fd == -1)) {
  463. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  464. return false;
  465. }
  466. /* We have a real Avalon! */
  467. avalon = calloc(1, sizeof(struct cgpu_info));
  468. avalon->api = &avalon_api;
  469. avalon->device_path = strdup(devpath);
  470. avalon->device_fd = fd;
  471. avalon->threads = AVALON_MINER_THREADS;
  472. add_cgpu(avalon);
  473. ret = avalon_reset(fd, &ar);
  474. if (ret) {
  475. ; /* FIXME: I think IT IS avalon and wait on reset;
  476. * avalon_close(fd);
  477. * return false; */
  478. }
  479. avalon_info = realloc(avalon_info,
  480. sizeof(struct avalon_info *) *
  481. (total_devices + 1));
  482. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  483. devpath, avalon->device_id);
  484. avalon_info[avalon->device_id] = (struct avalon_info *)
  485. malloc(sizeof(struct avalon_info));
  486. if (unlikely(!(avalon_info[avalon->device_id])))
  487. quit(1, "Failed to malloc avalon_info");
  488. info = avalon_info[avalon->device_id];
  489. memset(info, 0, sizeof(struct avalon_info));
  490. info->baud = baud;
  491. info->miner_count = miner_count;
  492. info->asic_count = asic_count;
  493. info->timeout = timeout;
  494. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  495. AVALON_TIME_FACTOR) / (float)info->miner_count;
  496. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  497. info->temp_max = 0;
  498. /* This is for check the temp/fan every 3~4s */
  499. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  500. if (info->temp_history_count <= 0)
  501. info->temp_history_count = 1;
  502. info->temp_history_index = 0;
  503. info->temp_sum = 0;
  504. info->temp_old = 0;
  505. info->frequency = frequency;
  506. /* Do something for failed reset ? */
  507. if (0) {
  508. /* Set asic to idle mode after detect */
  509. avalon_idle(avalon);
  510. avalon->device_fd = -1;
  511. avalon_close(fd);
  512. }
  513. return true;
  514. }
  515. static inline void avalon_detect()
  516. {
  517. serial_detect(&avalon_api, avalon_detect_one);
  518. }
  519. static void __avalon_init(struct cgpu_info *avalon)
  520. {
  521. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  522. }
  523. static void avalon_init(struct cgpu_info *avalon)
  524. {
  525. struct avalon_result ar;
  526. int fd, ret;
  527. avalon->device_fd = -1;
  528. fd = avalon_open(avalon->device_path,
  529. avalon_info[avalon->device_id]->baud);
  530. if (unlikely(fd == -1)) {
  531. applog(LOG_ERR, "Avalon: Failed to open on %s",
  532. avalon->device_path);
  533. return;
  534. }
  535. ret = avalon_reset(fd, &ar);
  536. if (ret) {
  537. avalon_close(fd);
  538. return;
  539. }
  540. avalon->device_fd = fd;
  541. __avalon_init(avalon);
  542. }
  543. static bool avalon_prepare(struct thr_info *thr)
  544. {
  545. struct cgpu_info *avalon = thr->cgpu;
  546. struct timeval now;
  547. __avalon_init(avalon);
  548. gettimeofday(&now, NULL);
  549. get_datestamp(avalon->init, &now);
  550. return true;
  551. }
  552. static void avalon_free_work(struct thr_info *thr, struct work **work)
  553. {
  554. struct cgpu_info *avalon;
  555. struct avalon_info *info;
  556. int i;
  557. if (unlikely(!work))
  558. return;
  559. avalon = thr->cgpu;
  560. info = avalon_info[avalon->device_id];
  561. for (i = 0; i < info->miner_count; i++)
  562. if (likely(work[i])) {
  563. free_work(work[i]);
  564. work[i] = NULL;
  565. }
  566. }
  567. static void do_avalon_close(struct thr_info *thr)
  568. {
  569. struct avalon_result ar;
  570. struct cgpu_info *avalon = thr->cgpu;
  571. struct avalon_info *info = avalon_info[avalon->device_id];
  572. sleep(1);
  573. avalon_reset(avalon->device_fd, &ar);
  574. avalon_idle(avalon);
  575. avalon_close(avalon->device_fd);
  576. avalon->device_fd = -1;
  577. info->no_matching_work = 0;
  578. avalon_free_work(thr, info->bulk0);
  579. avalon_free_work(thr, info->bulk1);
  580. avalon_free_work(thr, info->bulk2);
  581. avalon_free_work(thr, info->bulk3);
  582. }
  583. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  584. {
  585. int max;
  586. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  587. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  588. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  589. info->temp0 = ar->temp0;
  590. info->temp1 = ar->temp1;
  591. info->temp2 = ar->temp2;
  592. if (ar->temp0 & 0x80) {
  593. ar->temp0 &= 0x7f;
  594. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  595. }
  596. if (ar->temp1 & 0x80) {
  597. ar->temp1 &= 0x7f;
  598. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  599. }
  600. if (ar->temp2 & 0x80) {
  601. ar->temp2 &= 0x7f;
  602. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  603. }
  604. *temp_avg = info->temp2;
  605. max = info->temp_max;
  606. if (info->temp0 > max)
  607. max = info->temp0;
  608. if (info->temp1 > max)
  609. max = info->temp1;
  610. if (info->temp2 > max)
  611. max = info->temp2;
  612. if (max >= 100) { /* FIXME: fix the root cause on fpga controller firmware */
  613. if (opt_debug) {
  614. applog(LOG_DEBUG, "Avalon: temp_max: %d", max);
  615. hexdump((uint8_t *)ar, AVALON_READ_SIZE);
  616. }
  617. return;
  618. }
  619. info->temp_max = max;
  620. }
  621. static inline void adjust_fan(struct avalon_info *info)
  622. {
  623. int temp_new;
  624. temp_new = info->temp_sum / info->temp_history_count;
  625. if (temp_new < 35) {
  626. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  627. info->temp_old = temp_new;
  628. } else if (temp_new > 55) {
  629. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  630. info->temp_old = temp_new;
  631. } else if (abs(temp_new - info->temp_old) >= 2) {
  632. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  633. info->temp_old = temp_new;
  634. }
  635. }
  636. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  637. __maybe_unused int64_t max_nonce)
  638. {
  639. struct cgpu_info *avalon;
  640. int fd, ret, full;
  641. struct avalon_info *info;
  642. struct avalon_task at;
  643. struct avalon_result ar;
  644. int i, work_i0, work_i1, work_i2, work_i3;
  645. int avalon_get_work_count;
  646. struct timeval tv_start, tv_finish, elapsed;
  647. uint32_t nonce;
  648. int64_t hash_count;
  649. static int first_try = 0;
  650. int result_count, result_wrong;
  651. avalon = thr->cgpu;
  652. info = avalon_info[avalon->device_id];
  653. avalon_get_work_count = info->miner_count;
  654. if (unlikely(avalon->device_fd == -1))
  655. if (!avalon_prepare(thr)) {
  656. applog(LOG_ERR, "AVA%i: Comms error(open)",
  657. avalon->device_id);
  658. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  659. /* fail the device if the reopen attempt fails */
  660. return -1;
  661. }
  662. fd = avalon->device_fd;
  663. #ifndef WIN32
  664. tcflush(fd, TCOFLUSH);
  665. #endif
  666. for (i = 0; i < avalon_get_work_count; i++) {
  667. info->bulk0[i] = info->bulk1[i];
  668. info->bulk1[i] = info->bulk2[i];
  669. info->bulk2[i] = info->bulk3[i];
  670. info->bulk3[i] = work[i];
  671. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  672. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  673. }
  674. i = 0;
  675. while (true) {
  676. avalon_init_task(&at, 0, 0, info->fan_pwm,
  677. info->timeout, info->asic_count,
  678. info->miner_count, 1, 0, info->frequency);
  679. avalon_create_task(&at, work[i]);
  680. ret = avalon_send_task(fd, &at, avalon);
  681. if (unlikely(ret == AVA_SEND_ERROR ||
  682. (ret == AVA_SEND_BUFFER_EMPTY &&
  683. (i + 1 == avalon_get_work_count) &&
  684. first_try))) {
  685. avalon_free_work(thr, info->bulk0);
  686. avalon_free_work(thr, info->bulk1);
  687. avalon_free_work(thr, info->bulk2);
  688. avalon_free_work(thr, info->bulk3);
  689. do_avalon_close(thr);
  690. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  691. avalon->device_id);
  692. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  693. first_try = 0;
  694. sleep(1);
  695. return 0; /* This should never happen */
  696. }
  697. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  698. first_try = 1;
  699. return 0xffffffff;
  700. }
  701. work[i]->blk.nonce = 0xffffffff;
  702. if (ret == AVA_SEND_BUFFER_FULL)
  703. break;
  704. i++;
  705. }
  706. if (unlikely(first_try))
  707. first_try = 0;
  708. elapsed.tv_sec = elapsed.tv_usec = 0;
  709. gettimeofday(&tv_start, NULL);
  710. result_count = 0;
  711. result_wrong = 0;
  712. hash_count = 0;
  713. while (true) {
  714. work_i0 = work_i1 = work_i2 = work_i3 = -1;
  715. full = avalon_buffer_full(fd);
  716. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  717. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  718. if (unlikely(full == AVA_BUFFER_EMPTY))
  719. break;
  720. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  721. if (unlikely(ret == AVA_GETS_ERROR)) {
  722. avalon_free_work(thr, info->bulk0);
  723. avalon_free_work(thr, info->bulk1);
  724. avalon_free_work(thr, info->bulk2);
  725. avalon_free_work(thr, info->bulk3);
  726. do_avalon_close(thr);
  727. applog(LOG_ERR,
  728. "AVA%i: Comms error(read)", avalon->device_id);
  729. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  730. return 0;
  731. }
  732. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  733. timersub(&tv_finish, &tv_start, &elapsed);
  734. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  735. elapsed.tv_sec, elapsed.tv_usec);
  736. continue;
  737. }
  738. if (unlikely(ret == AVA_GETS_RESTART)) {
  739. avalon_free_work(thr, info->bulk0);
  740. avalon_free_work(thr, info->bulk1);
  741. avalon_free_work(thr, info->bulk2);
  742. avalon_free_work(thr, info->bulk3);
  743. continue;
  744. }
  745. result_count++;
  746. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  747. if (work_i0 < 0) {
  748. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  749. if (work_i1 < 0) {
  750. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  751. if (work_i2 < 0) {
  752. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  753. if (work_i3 < 0) {
  754. info->no_matching_work++;
  755. result_wrong++;
  756. if (opt_debug) {
  757. timersub(&tv_finish, &tv_start, &elapsed);
  758. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  759. " (%ld.%06lds)", info->no_matching_work,
  760. elapsed.tv_sec, elapsed.tv_usec);
  761. }
  762. continue;
  763. } else
  764. submit_nonce(thr, info->bulk3[work_i3], nonce);
  765. } else
  766. submit_nonce(thr, info->bulk2[work_i2], nonce);
  767. } else
  768. submit_nonce(thr, info->bulk1[work_i1], nonce);
  769. } else
  770. submit_nonce(thr, info->bulk0[work_i0], nonce);
  771. hash_count += nonce;
  772. if (opt_debug) {
  773. timersub(&tv_finish, &tv_start, &elapsed);
  774. applog(LOG_DEBUG,
  775. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  776. "(%ld.%06lds)", nonce, hash_count,
  777. elapsed.tv_sec, elapsed.tv_usec);
  778. }
  779. }
  780. if (result_count == result_wrong) {
  781. /* This mean FPGA controller give all wrong result
  782. * try to reset the Avalon */
  783. avalon_free_work(thr, info->bulk0);
  784. avalon_free_work(thr, info->bulk1);
  785. avalon_free_work(thr, info->bulk2);
  786. avalon_free_work(thr, info->bulk3);
  787. do_avalon_close(thr);
  788. applog(LOG_ERR,
  789. "AVA%i: FPGA controller mess up", avalon->device_id);
  790. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  791. return 0;
  792. }
  793. avalon_free_work(thr, info->bulk0);
  794. record_temp_fan(info, &ar, &(avalon->temp));
  795. applog(LOG_INFO,
  796. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  797. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  798. info->fan0, info->fan1, info->fan2,
  799. info->temp0, info->temp1, info->temp2, info->temp_max);
  800. info->temp_history_index++;
  801. info->temp_sum += info->temp2;
  802. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  803. info->temp_history_index, info->temp_history_count, info->temp_old);
  804. if (info->temp_history_index == info->temp_history_count) {
  805. adjust_fan(info);
  806. info->temp_history_index = 0;
  807. info->temp_sum = 0;
  808. }
  809. /*
  810. * FIXME: Each work split to 10 pieces, each piece send to a
  811. * asic(256MHs). one work can be mulit-nonce back. it is not
  812. * easy calculate correct hash on such situation. so I simplely
  813. * add each nonce to hash_count. base on Utility/m hash_count*2
  814. * give a very good result.
  815. *
  816. * Any patch will be great.
  817. */
  818. return (hash_count * 2);
  819. }
  820. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  821. {
  822. struct api_data *root = NULL;
  823. struct avalon_info *info = avalon_info[cgpu->device_id];
  824. root = api_add_int(root, "baud", &(info->baud), false);
  825. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  826. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  827. root = api_add_int(root, "read_count", &(info->read_count), false);
  828. root = api_add_int(root, "timeout", &(info->timeout), false);
  829. root = api_add_int(root, "frequency", &(info->frequency), false);
  830. root = api_add_int(root, "fan1", &(info->fan0), false);
  831. root = api_add_int(root, "fan2", &(info->fan1), false);
  832. root = api_add_int(root, "fan3", &(info->fan2), false);
  833. root = api_add_int(root, "temp1", &(info->temp0), false);
  834. root = api_add_int(root, "temp2", &(info->temp1), false);
  835. root = api_add_int(root, "temp3", &(info->temp2), false);
  836. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  837. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  838. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  839. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  840. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  841. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  842. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  843. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  844. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  845. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  846. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  847. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  848. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  849. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  850. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  851. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  852. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  853. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  854. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  855. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  856. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  857. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  858. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  859. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  860. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  861. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  862. return root;
  863. }
  864. static void avalon_shutdown(struct thr_info *thr)
  865. {
  866. do_avalon_close(thr);
  867. }
  868. struct device_api avalon_api = {
  869. .dname = "avalon",
  870. .name = "AVA",
  871. .api_detect = avalon_detect,
  872. .thread_prepare = avalon_prepare,
  873. .scanhash_queue = avalon_scanhash,
  874. .get_api_stats = avalon_api_stats,
  875. .reinit_device = avalon_init,
  876. .thread_shutdown = avalon_shutdown,
  877. };