driver-avalon.c 30 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. static int option_offset = -1;
  40. struct device_drv avalon_drv;
  41. static int avalon_init_task(struct avalon_task *at,
  42. uint8_t reset, uint8_t ff, uint8_t fan,
  43. uint8_t timeout, uint8_t asic_num,
  44. uint8_t miner_num, uint8_t nonce_elf,
  45. uint8_t gate_miner, int frequency)
  46. {
  47. uint8_t *buf;
  48. static bool first = true;
  49. if (unlikely(!at))
  50. return -1;
  51. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  52. return -1;
  53. memset(at, 0, sizeof(struct avalon_task));
  54. if (unlikely(reset)) {
  55. at->reset = 1;
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = true;
  59. }
  60. at->flush_fifo = (ff ? 1 : 0);
  61. at->fan_eft = (fan ? 1 : 0);
  62. if (unlikely(first && !at->reset)) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  68. at->timeout_data = timeout;
  69. at->asic_num = asic_num;
  70. at->miner_num = miner_num;
  71. at->nonce_elf = nonce_elf;
  72. at->gate_miner_elf = 1;
  73. at->asic_pll = 1;
  74. if (unlikely(gate_miner)) {
  75. at-> gate_miner = 1;
  76. at->asic_pll = 0;
  77. }
  78. buf = (uint8_t *)at;
  79. buf[5] = 0x00;
  80. buf[8] = 0x74;
  81. buf[9] = 0x01;
  82. buf[10] = 0x00;
  83. buf[11] = 0x00;
  84. switch (frequency) {
  85. case 256:
  86. buf[6] = 0x03;
  87. buf[7] = 0x08;
  88. break;
  89. default:
  90. case 270:
  91. buf[6] = 0x73;
  92. buf[7] = 0x08;
  93. break;
  94. case 282:
  95. buf[6] = 0xd3;
  96. buf[7] = 0x08;
  97. break;
  98. case 300:
  99. buf[6] = 0x63;
  100. buf[7] = 0x09;
  101. break;
  102. case 325:
  103. buf[6] = 0x28;
  104. buf[7] = 0x0a;
  105. break;
  106. case 350:
  107. buf[6] = 0xf0;
  108. buf[7] = 0x0a;
  109. break;
  110. case 375:
  111. buf[6] = 0xb8;
  112. buf[7] = 0x0b;
  113. break;
  114. }
  115. return 0;
  116. }
  117. static inline void avalon_create_task(struct avalon_task *at,
  118. struct work *work)
  119. {
  120. memcpy(at->midstate, work->midstate, 32);
  121. memcpy(at->data, work->data + 64, 12);
  122. }
  123. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  124. {
  125. int err, amount;
  126. err = usb_write(avalon, buf, len, &amount, ep);
  127. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  128. avalon->device_id, err);
  129. if (unlikely(err != 0)) {
  130. applog(LOG_WARNING, "usb_write error on avalon_write");
  131. return AVA_SEND_ERROR;
  132. }
  133. if (amount != len) {
  134. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  135. return AVA_SEND_ERROR;
  136. }
  137. return AVA_SEND_OK;
  138. }
  139. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  140. {
  141. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  142. int delay, ret, i, ep = C_AVALON_TASK;
  143. struct avalon_info *info;
  144. uint32_t nonce_range;
  145. size_t nr_len;
  146. if (at->nonce_elf)
  147. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  148. else
  149. nr_len = AVALON_WRITE_SIZE;
  150. memcpy(buf, at, AVALON_WRITE_SIZE);
  151. if (at->nonce_elf) {
  152. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  153. for (i = 0; i < at->asic_num; i++) {
  154. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  155. (i * nonce_range & 0xff000000) >> 24;
  156. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  157. (i * nonce_range & 0x00ff0000) >> 16;
  158. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  159. (i * nonce_range & 0x0000ff00) >> 8;
  160. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  161. (i * nonce_range & 0x000000ff) >> 0;
  162. }
  163. }
  164. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  165. uint8_t tt = 0;
  166. tt = (buf[0] & 0x0f) << 4;
  167. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  168. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  169. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  170. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  171. buf[0] = tt;
  172. tt = (buf[4] & 0x0f) << 4;
  173. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  174. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  175. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  176. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  177. buf[4] = tt;
  178. #endif
  179. info = avalon->device_data;
  180. delay = nr_len * 10 * 1000000;
  181. delay = delay / info->baud;
  182. if (at->reset) {
  183. ep = C_AVALON_RESET;
  184. nr_len = 1;
  185. }
  186. if (opt_debug) {
  187. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  188. hexdump(buf, nr_len);
  189. }
  190. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  191. delay += 4000;
  192. nusleep(delay);
  193. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  194. return ret;
  195. }
  196. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  197. struct avalon_info *info, struct avalon_result *ar,
  198. struct work *work)
  199. {
  200. uint32_t nonce;
  201. info = avalon->device_data;
  202. info->matching_work[work->subid]++;
  203. nonce = htole32(ar->nonce);
  204. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  205. return submit_nonce(thr, work, nonce);
  206. }
  207. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  208. static void wait_avalon_ready(struct cgpu_info *avalon)
  209. {
  210. while (avalon_buffer_full(avalon)) {
  211. nmsleep(40);
  212. }
  213. }
  214. #define AVALON_CTS (1 << 4)
  215. static inline bool avalon_cts(char c)
  216. {
  217. return (c & AVALON_CTS);
  218. }
  219. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  220. size_t bufsize, int timeout, int ep)
  221. {
  222. struct avalon_info *info = avalon->device_data;
  223. size_t total = 0, readsize = bufsize + 2;
  224. char readbuf[AVALON_READBUF_SIZE];
  225. int err, amount, ofs = 2, cp;
  226. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  227. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  228. avalon->drv->name, avalon->device_id, err);
  229. if (amount < 2)
  230. goto out;
  231. /* Use the fact that we're reading the status with the buffer to tell
  232. * the write thread it should send more work without needing to call
  233. * avalon_buffer_full directly. */
  234. if (avalon_cts(buf[0]))
  235. cgsem_post(&info->write_sem);
  236. /* The first 2 of every 64 bytes are status on FTDIRL */
  237. while (amount > 2) {
  238. cp = amount - 2;
  239. if (cp > 62)
  240. cp = 62;
  241. memcpy(&buf[total], &readbuf[ofs], cp);
  242. total += cp;
  243. amount -= cp + 2;
  244. ofs += 64;
  245. }
  246. out:
  247. return total;
  248. }
  249. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  250. {
  251. struct avalon_result ar;
  252. int ret, i, spare;
  253. struct avalon_task at;
  254. uint8_t *buf, *tmp;
  255. struct timespec p;
  256. /* Send reset, then check for result */
  257. avalon_init_task(&at, 1, 0,
  258. AVALON_DEFAULT_FAN_MAX_PWM,
  259. AVALON_DEFAULT_TIMEOUT,
  260. AVALON_DEFAULT_ASIC_NUM,
  261. AVALON_DEFAULT_MINER_NUM,
  262. 0, 0,
  263. AVALON_DEFAULT_FREQUENCY);
  264. wait_avalon_ready(avalon);
  265. ret = avalon_send_task(&at, avalon);
  266. if (unlikely(ret == AVA_SEND_ERROR))
  267. return -1;
  268. if (!initial) {
  269. applog(LOG_ERR, "AVA%d reset sequence sent", avalon->device_id);
  270. return 0;
  271. }
  272. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  273. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  274. /* What do these sleeps do?? */
  275. p.tv_sec = 0;
  276. p.tv_nsec = AVALON_RESET_PITCH;
  277. nanosleep(&p, NULL);
  278. /* Look for the first occurrence of 0xAA, the reset response should be:
  279. * AA 55 AA 55 00 00 00 00 00 00 */
  280. spare = ret - 10;
  281. buf = tmp = (uint8_t *)&ar;
  282. if (opt_debug) {
  283. applog(LOG_DEBUG, "AVA%d reset: get:", avalon->device_id);
  284. hexdump(tmp, AVALON_READ_SIZE);
  285. }
  286. for (i = 0; i <= spare; i++) {
  287. buf = &tmp[i];
  288. if (buf[0] == 0xAA)
  289. break;
  290. }
  291. i = 0;
  292. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  293. buf[2] == 0xAA && buf[3] == 0x55) {
  294. for (i = 4; i < 11; i++)
  295. if (buf[i] != 0)
  296. break;
  297. }
  298. if (i != 11) {
  299. applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
  300. " (%d: %02x %02x %02x %02x)", avalon->device_id,
  301. i, buf[0], buf[1], buf[2], buf[3]);
  302. /* FIXME: return 1; */
  303. } else
  304. applog(LOG_WARNING, "AVA%d: Reset succeeded",
  305. avalon->device_id);
  306. return 0;
  307. }
  308. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  309. int *asic_count, int *timeout, int *frequency)
  310. {
  311. char buf[BUFSIZ+1];
  312. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  313. size_t max;
  314. int i, tmp;
  315. if (opt_avalon_options == NULL)
  316. buf[0] = '\0';
  317. else {
  318. ptr = opt_avalon_options;
  319. for (i = 0; i < this_option_offset; i++) {
  320. comma = strchr(ptr, ',');
  321. if (comma == NULL)
  322. break;
  323. ptr = comma + 1;
  324. }
  325. comma = strchr(ptr, ',');
  326. if (comma == NULL)
  327. max = strlen(ptr);
  328. else
  329. max = comma - ptr;
  330. if (max > BUFSIZ)
  331. max = BUFSIZ;
  332. strncpy(buf, ptr, max);
  333. buf[max] = '\0';
  334. }
  335. if (!(*buf))
  336. return false;
  337. colon = strchr(buf, ':');
  338. if (colon)
  339. *(colon++) = '\0';
  340. tmp = atoi(buf);
  341. switch (tmp) {
  342. case 115200:
  343. *baud = 115200;
  344. break;
  345. case 57600:
  346. *baud = 57600;
  347. break;
  348. case 38400:
  349. *baud = 38400;
  350. break;
  351. case 19200:
  352. *baud = 19200;
  353. break;
  354. default:
  355. quit(1, "Invalid avalon-options for baud (%s) "
  356. "must be 115200, 57600, 38400 or 19200", buf);
  357. }
  358. if (colon && *colon) {
  359. colon2 = strchr(colon, ':');
  360. if (colon2)
  361. *(colon2++) = '\0';
  362. if (*colon) {
  363. tmp = atoi(colon);
  364. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  365. *miner_count = tmp;
  366. } else {
  367. quit(1, "Invalid avalon-options for "
  368. "miner_count (%s) must be 1 ~ %d",
  369. colon, AVALON_DEFAULT_MINER_NUM);
  370. }
  371. }
  372. if (colon2 && *colon2) {
  373. colon3 = strchr(colon2, ':');
  374. if (colon3)
  375. *(colon3++) = '\0';
  376. tmp = atoi(colon2);
  377. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  378. *asic_count = tmp;
  379. else {
  380. quit(1, "Invalid avalon-options for "
  381. "asic_count (%s) must be 1 ~ %d",
  382. colon2, AVALON_DEFAULT_ASIC_NUM);
  383. }
  384. if (colon3 && *colon3) {
  385. colon4 = strchr(colon3, ':');
  386. if (colon4)
  387. *(colon4++) = '\0';
  388. tmp = atoi(colon3);
  389. if (tmp > 0 && tmp <= 0xff)
  390. *timeout = tmp;
  391. else {
  392. quit(1, "Invalid avalon-options for "
  393. "timeout (%s) must be 1 ~ %d",
  394. colon3, 0xff);
  395. }
  396. if (colon4 && *colon4) {
  397. tmp = atoi(colon4);
  398. switch (tmp) {
  399. case 256:
  400. case 270:
  401. case 282:
  402. case 300:
  403. case 325:
  404. case 350:
  405. case 375:
  406. *frequency = tmp;
  407. break;
  408. default:
  409. quit(1, "Invalid avalon-options for "
  410. "frequency must be 256/270/282/300/325/350/375");
  411. }
  412. }
  413. }
  414. }
  415. }
  416. return true;
  417. }
  418. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  419. {
  420. int i;
  421. info->idle = true;
  422. wait_avalon_ready(avalon);
  423. /* Send idle to all miners */
  424. for (i = 0; i < info->miner_count; i++) {
  425. struct avalon_task at;
  426. if (unlikely(avalon_buffer_full(avalon)))
  427. break;
  428. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  429. info->asic_count, info->miner_count, 1, 1,
  430. info->frequency);
  431. avalon_send_task(&at, avalon);
  432. }
  433. applog(LOG_WARNING, "AVA%i: Idling %d miners", avalon->device_id, i);
  434. wait_avalon_ready(avalon);
  435. }
  436. static void avalon_initialise(struct cgpu_info *avalon)
  437. {
  438. int err, interface;
  439. if (avalon->usbinfo.nodev)
  440. return;
  441. interface = avalon->usbdev->found->interface;
  442. // Reset
  443. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  444. FTDI_VALUE_RESET, interface, C_RESET);
  445. applog(LOG_DEBUG, "%s%i: reset got err %d",
  446. avalon->drv->name, avalon->device_id, err);
  447. if (avalon->usbinfo.nodev)
  448. return;
  449. // Set latency
  450. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  451. AVALON_LATENCY, interface, C_LATENCY);
  452. applog(LOG_DEBUG, "%s%i: latency got err %d",
  453. avalon->drv->name, avalon->device_id, err);
  454. if (avalon->usbinfo.nodev)
  455. return;
  456. // Set data
  457. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  458. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  459. applog(LOG_DEBUG, "%s%i: data got err %d",
  460. avalon->drv->name, avalon->device_id, err);
  461. if (avalon->usbinfo.nodev)
  462. return;
  463. // Set the baud
  464. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  465. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  466. C_SETBAUD);
  467. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  468. avalon->drv->name, avalon->device_id, err);
  469. if (avalon->usbinfo.nodev)
  470. return;
  471. // Set Modem Control
  472. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  473. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  474. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  475. avalon->drv->name, avalon->device_id, err);
  476. if (avalon->usbinfo.nodev)
  477. return;
  478. // Set Flow Control
  479. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  480. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  481. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  482. avalon->drv->name, avalon->device_id, err);
  483. if (avalon->usbinfo.nodev)
  484. return;
  485. /* Avalon repeats the following */
  486. // Set Modem Control
  487. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  488. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  489. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  490. avalon->drv->name, avalon->device_id, err);
  491. if (avalon->usbinfo.nodev)
  492. return;
  493. // Set Flow Control
  494. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  495. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  496. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  497. avalon->drv->name, avalon->device_id, err);
  498. }
  499. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  500. {
  501. int baud, miner_count, asic_count, timeout, frequency = 0;
  502. int this_option_offset = ++option_offset;
  503. struct avalon_info *info;
  504. struct cgpu_info *avalon;
  505. bool configured;
  506. int ret;
  507. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  508. configured = get_options(this_option_offset, &baud, &miner_count,
  509. &asic_count, &timeout, &frequency);
  510. if (!usb_init(avalon, dev, found))
  511. goto shin;
  512. /* Even though this is an FTDI type chip, we want to do the parsing
  513. * all ourselves so set it to std usb type */
  514. avalon->usbdev->usb_type = USB_TYPE_STD;
  515. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  516. /* We have a real Avalon! */
  517. avalon_initialise(avalon);
  518. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  519. if (unlikely(!(avalon->device_data)))
  520. quit(1, "Failed to calloc avalon_info data");
  521. info = avalon->device_data;
  522. if (configured) {
  523. info->baud = baud;
  524. info->miner_count = miner_count;
  525. info->asic_count = asic_count;
  526. info->timeout = timeout;
  527. info->frequency = frequency;
  528. } else {
  529. info->baud = AVALON_IO_SPEED;
  530. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  531. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  532. info->timeout = AVALON_DEFAULT_TIMEOUT;
  533. info->frequency = AVALON_DEFAULT_FREQUENCY;
  534. }
  535. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  536. info->temp_max = 0;
  537. /* This is for check the temp/fan every 3~4s */
  538. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  539. if (info->temp_history_count <= 0)
  540. info->temp_history_count = 1;
  541. info->temp_history_index = 0;
  542. info->temp_sum = 0;
  543. info->temp_old = 0;
  544. if (!add_cgpu(avalon))
  545. goto unshin;
  546. ret = avalon_reset(avalon, true);
  547. if (ret && !configured)
  548. goto unshin;
  549. update_usb_stats(avalon);
  550. avalon_idle(avalon, info);
  551. applog(LOG_DEBUG, "Avalon Detected: %s "
  552. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  553. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  554. info->frequency);
  555. return true;
  556. unshin:
  557. usb_uninit(avalon);
  558. shin:
  559. free(avalon->device_data);
  560. avalon->device_data = NULL;
  561. avalon = usb_free_cgpu(avalon);
  562. return false;
  563. }
  564. static void avalon_detect(void)
  565. {
  566. usb_detect(&avalon_drv, avalon_detect_one);
  567. }
  568. static void avalon_init(struct cgpu_info *avalon)
  569. {
  570. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  571. }
  572. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  573. {
  574. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  575. (char *)ar->data, 64, 12);
  576. }
  577. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  578. struct avalon_result *ar);
  579. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  580. {
  581. if (unlikely(info->idle))
  582. return;
  583. applog(LOG_WARNING, "%s%d: No matching work - HW error",
  584. thr->cgpu->drv->name, thr->cgpu->device_id);
  585. inc_hw_errors(thr);
  586. info->no_matching_work++;
  587. }
  588. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  589. struct thr_info *thr, char *buf, int *offset)
  590. {
  591. int i, spare = *offset - AVALON_READ_SIZE;
  592. bool found = false;
  593. for (i = 0; i <= spare; i++) {
  594. struct avalon_result *ar;
  595. struct work *work;
  596. ar = (struct avalon_result *)&buf[i];
  597. work = avalon_valid_result(avalon, ar);
  598. if (work) {
  599. bool gettemp = false;
  600. found = true;
  601. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  602. mutex_lock(&info->lock);
  603. if (!info->nonces++)
  604. gettemp = true;
  605. mutex_unlock(&info->lock);
  606. }
  607. if (gettemp)
  608. avalon_update_temps(avalon, info, ar);
  609. break;
  610. }
  611. }
  612. if (!found) {
  613. spare = *offset - AVALON_READ_SIZE;
  614. /* We are buffering and haven't accumulated one more corrupt
  615. * work result. */
  616. if (spare < (int)AVALON_READ_SIZE)
  617. return;
  618. avalon_inc_nvw(info, thr);
  619. } else {
  620. spare = AVALON_READ_SIZE + i;
  621. if (i) {
  622. if (i >= (int)AVALON_READ_SIZE)
  623. avalon_inc_nvw(info, thr);
  624. else
  625. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  626. }
  627. }
  628. *offset -= spare;
  629. memmove(buf, buf + spare, *offset);
  630. }
  631. static void avalon_running_reset(struct cgpu_info *avalon,
  632. struct avalon_info *info)
  633. {
  634. avalon_reset(avalon, false);
  635. avalon_idle(avalon, info);
  636. avalon->results = 0;
  637. info->reset = false;
  638. }
  639. static void *avalon_get_results(void *userdata)
  640. {
  641. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  642. struct avalon_info *info = avalon->device_data;
  643. int offset = 0, read_delay = 0, ret = 0;
  644. const int rsize = AVALON_FTDI_READSIZE;
  645. char readbuf[AVALON_READBUF_SIZE];
  646. struct thr_info *thr = info->thr;
  647. struct timeval tv_start, tv_end;
  648. char threadname[24];
  649. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  650. RenameThread(threadname);
  651. while (likely(!avalon->shutdown)) {
  652. unsigned char buf[rsize];
  653. struct timeval tv_diff;
  654. int us_diff;
  655. if (offset >= (int)AVALON_READ_SIZE)
  656. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  657. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  658. /* This should never happen */
  659. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  660. offset = 0;
  661. }
  662. if (unlikely(info->reset)) {
  663. avalon_running_reset(avalon, info);
  664. /* Discard anything in the buffer */
  665. offset = 0;
  666. }
  667. /* As the usb read returns after just 1ms, sleep long enough
  668. * to leave the interface idle for writes to occur, but do not
  669. * sleep if we have been receiving data as more may be coming. */
  670. if (ret < 1) {
  671. cgtime(&tv_end);
  672. timersub(&tv_end, &tv_start, &tv_diff);
  673. /* Assume it has not been > 1 second so ignore tv_sec */
  674. us_diff = tv_diff.tv_usec;
  675. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  676. if (likely(read_delay >= 1000))
  677. nusleep(read_delay);
  678. }
  679. cgtime(&tv_start);
  680. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  681. C_AVALON_READ);
  682. if (ret < 1)
  683. continue;
  684. if (opt_debug) {
  685. applog(LOG_DEBUG, "Avalon: get:");
  686. hexdump((uint8_t *)buf, ret);
  687. }
  688. memcpy(&readbuf[offset], &buf, ret);
  689. offset += ret;
  690. }
  691. return NULL;
  692. }
  693. static void avalon_rotate_array(struct cgpu_info *avalon)
  694. {
  695. avalon->queued = 0;
  696. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  697. avalon->work_array = 0;
  698. }
  699. static void *avalon_send_tasks(void *userdata)
  700. {
  701. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  702. struct avalon_info *info = avalon->device_data;
  703. const int avalon_get_work_count = info->miner_count;
  704. char threadname[24];
  705. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  706. RenameThread(threadname);
  707. while (likely(!avalon->shutdown)) {
  708. int start_count, end_count, i, j, ret;
  709. struct avalon_task at;
  710. int idled = 0;
  711. while (avalon_buffer_full(avalon))
  712. cgsem_wait(&info->write_sem);
  713. mutex_lock(&info->qlock);
  714. start_count = avalon->work_array * avalon_get_work_count;
  715. end_count = start_count + avalon_get_work_count;
  716. for (i = start_count, j = 0; i < end_count; i++, j++) {
  717. if (avalon_buffer_full(avalon)) {
  718. applog(LOG_INFO,
  719. "AVA%i: Buffer full after only %d of %d work queued",
  720. avalon->device_id, j, avalon_get_work_count);
  721. break;
  722. }
  723. if (likely(j < avalon->queued)) {
  724. info->idle = false;
  725. avalon_init_task(&at, 0, 0, info->fan_pwm,
  726. info->timeout, info->asic_count,
  727. info->miner_count, 1, 0, info->frequency);
  728. avalon_create_task(&at, avalon->works[i]);
  729. } else {
  730. idled++;
  731. avalon_init_task(&at, 0, 0, info->fan_pwm,
  732. info->timeout, info->asic_count,
  733. info->miner_count, 1, 1, info->frequency);
  734. }
  735. ret = avalon_send_task(&at, avalon);
  736. if (unlikely(ret == AVA_SEND_ERROR)) {
  737. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  738. avalon->device_id);
  739. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  740. info->reset = true;
  741. break;
  742. }
  743. }
  744. avalon_rotate_array(avalon);
  745. pthread_cond_signal(&info->qcond);
  746. mutex_unlock(&info->qlock);
  747. if (unlikely(idled && !info->idle)) {
  748. info->idle = true;
  749. applog(LOG_WARNING, "AVA%i: Idled %d miners",
  750. avalon->device_id, idled);
  751. }
  752. }
  753. return NULL;
  754. }
  755. static bool avalon_prepare(struct thr_info *thr)
  756. {
  757. struct cgpu_info *avalon = thr->cgpu;
  758. struct avalon_info *info = avalon->device_data;
  759. struct timeval now;
  760. free(avalon->works);
  761. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  762. AVALON_ARRAY_SIZE);
  763. if (!avalon->works)
  764. quit(1, "Failed to calloc avalon works in avalon_prepare");
  765. info->thr = thr;
  766. mutex_init(&info->lock);
  767. mutex_init(&info->qlock);
  768. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  769. quit(1, "Failed to pthread_cond_init avalon qcond");
  770. cgsem_init(&info->write_sem);
  771. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  772. quit(1, "Failed to create avalon read_thr");
  773. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  774. quit(1, "Failed to create avalon write_thr");
  775. avalon_init(avalon);
  776. cgtime(&now);
  777. get_datestamp(avalon->init, &now);
  778. return true;
  779. }
  780. static void do_avalon_close(struct thr_info *thr)
  781. {
  782. struct cgpu_info *avalon = thr->cgpu;
  783. struct avalon_info *info = avalon->device_data;
  784. pthread_join(info->read_thr, NULL);
  785. pthread_join(info->write_thr, NULL);
  786. avalon_running_reset(avalon, info);
  787. info->no_matching_work = 0;
  788. cgsem_destroy(&info->write_sem);
  789. }
  790. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  791. {
  792. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  793. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  794. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  795. info->temp0 = ar->temp0;
  796. info->temp1 = ar->temp1;
  797. info->temp2 = ar->temp2;
  798. if (ar->temp0 & 0x80) {
  799. ar->temp0 &= 0x7f;
  800. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  801. }
  802. if (ar->temp1 & 0x80) {
  803. ar->temp1 &= 0x7f;
  804. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  805. }
  806. if (ar->temp2 & 0x80) {
  807. ar->temp2 &= 0x7f;
  808. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  809. }
  810. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  811. if (info->temp0 > info->temp_max)
  812. info->temp_max = info->temp0;
  813. if (info->temp1 > info->temp_max)
  814. info->temp_max = info->temp1;
  815. if (info->temp2 > info->temp_max)
  816. info->temp_max = info->temp2;
  817. }
  818. static void temp_rise(struct avalon_info *info, int temp)
  819. {
  820. if (temp >= AVALON_TEMP_TARGET + AVALON_TEMP_HYSTERESIS * 3) {
  821. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  822. return;
  823. }
  824. if (temp >= AVALON_TEMP_TARGET + AVALON_TEMP_HYSTERESIS * 2)
  825. info->fan_pwm += 10;
  826. else if (temp > AVALON_TEMP_TARGET)
  827. info->fan_pwm += 5;
  828. else if (temp >= AVALON_TEMP_TARGET - AVALON_TEMP_HYSTERESIS)
  829. info->fan_pwm += 1;
  830. else
  831. return;
  832. if (info->fan_pwm > AVALON_DEFAULT_FAN_MAX_PWM)
  833. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  834. }
  835. static void temp_drop(struct avalon_info *info, int temp)
  836. {
  837. if (temp <= AVALON_TEMP_TARGET - AVALON_TEMP_HYSTERESIS * 3) {
  838. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  839. return;
  840. }
  841. if (temp <= AVALON_TEMP_TARGET - AVALON_TEMP_HYSTERESIS * 2)
  842. info->fan_pwm -= 10;
  843. else if (temp <= AVALON_TEMP_TARGET - AVALON_TEMP_HYSTERESIS)
  844. info->fan_pwm -= 5;
  845. else if (temp < AVALON_TEMP_TARGET)
  846. info->fan_pwm -= 1;
  847. if (info->fan_pwm < AVALON_DEFAULT_FAN_MIN_PWM)
  848. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  849. }
  850. static inline void adjust_fan(struct avalon_info *info)
  851. {
  852. int temp_new;
  853. temp_new = info->temp_sum / info->temp_history_count;
  854. if (temp_new > info->temp_old)
  855. temp_rise(info, temp_new);
  856. else if (temp_new < info->temp_old)
  857. temp_drop(info, temp_new);
  858. else {
  859. /* temp_new == info->temp_old */
  860. if (temp_new > AVALON_TEMP_TARGET)
  861. temp_rise(info, temp_new);
  862. else if (temp_new < AVALON_TEMP_TARGET - AVALON_TEMP_HYSTERESIS)
  863. temp_drop(info, temp_new);
  864. }
  865. info->temp_old = temp_new;
  866. }
  867. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  868. struct avalon_result *ar)
  869. {
  870. record_temp_fan(info, ar, &(avalon->temp));
  871. applog(LOG_INFO,
  872. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  873. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  874. info->fan0, info->fan1, info->fan2,
  875. info->temp0, info->temp1, info->temp2, info->temp_max);
  876. info->temp_history_index++;
  877. info->temp_sum += avalon->temp;
  878. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  879. info->temp_history_index, info->temp_history_count, info->temp_old);
  880. if (info->temp_history_index == info->temp_history_count) {
  881. adjust_fan(info);
  882. info->temp_history_index = 0;
  883. info->temp_sum = 0;
  884. }
  885. }
  886. static void get_avalon_statline_before(char *buf, struct cgpu_info *avalon)
  887. {
  888. struct avalon_info *info = avalon->device_data;
  889. int lowfan = 10000;
  890. /* Find the lowest fan speed of the ASIC cooling fans. */
  891. if (info->fan1 >= 0 && info->fan1 < lowfan)
  892. lowfan = info->fan1;
  893. if (info->fan2 >= 0 && info->fan2 < lowfan)
  894. lowfan = info->fan2;
  895. tailsprintf(buf, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  896. }
  897. /* We use a replacement algorithm to only remove references to work done from
  898. * the buffer when we need the extra space for new work. */
  899. static bool avalon_fill(struct cgpu_info *avalon)
  900. {
  901. struct avalon_info *info = avalon->device_data;
  902. int subid, slot, mc;
  903. struct work *work;
  904. bool ret = true;
  905. mc = info->miner_count;
  906. mutex_lock(&info->qlock);
  907. if (avalon->queued >= mc)
  908. goto out_unlock;
  909. work = get_queued(avalon);
  910. if (unlikely(!work)) {
  911. ret = false;
  912. goto out_unlock;
  913. }
  914. subid = avalon->queued++;
  915. work->subid = subid;
  916. slot = avalon->work_array * mc + subid;
  917. if (likely(avalon->works[slot]))
  918. work_completed(avalon, avalon->works[slot]);
  919. avalon->works[slot] = work;
  920. if (avalon->queued < mc)
  921. ret = false;
  922. out_unlock:
  923. mutex_unlock(&info->qlock);
  924. return ret;
  925. }
  926. static int64_t avalon_scanhash(struct thr_info *thr)
  927. {
  928. struct cgpu_info *avalon = thr->cgpu;
  929. struct avalon_info *info = avalon->device_data;
  930. const int miner_count = info->miner_count;
  931. struct timeval now, then, tdiff;
  932. int64_t hash_count, us_timeout;
  933. struct timespec abstime;
  934. /* Half nonce range */
  935. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  936. tdiff.tv_sec = us_timeout / 1000000;
  937. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  938. cgtime(&now);
  939. timeradd(&now, &tdiff, &then);
  940. abstime.tv_sec = then.tv_sec;
  941. abstime.tv_nsec = then.tv_usec * 1000;
  942. /* Wait until avalon_send_tasks signals us that it has completed
  943. * sending its work or a full nonce range timeout has occurred */
  944. mutex_lock(&info->qlock);
  945. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  946. mutex_unlock(&info->qlock);
  947. mutex_lock(&info->lock);
  948. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  949. avalon->results += info->nonces;
  950. if (avalon->results > miner_count)
  951. avalon->results = miner_count;
  952. if (!info->idle && !info->reset)
  953. avalon->results -= miner_count / 3;
  954. else
  955. avalon->results = miner_count;
  956. info->nonces = 0;
  957. mutex_unlock(&info->lock);
  958. /* Check for nothing but consecutive bad results or consistently less
  959. * results than we should be getting and reset the FPGA if necessary */
  960. if (avalon->results < -miner_count && !info->reset) {
  961. applog(LOG_ERR, "AVA%d: Result return rate low, resetting!",
  962. avalon->device_id);
  963. info->reset = true;
  964. }
  965. if (unlikely(avalon->usbinfo.nodev)) {
  966. applog(LOG_ERR, "AVA%d: Device disappeared, shutting down thread",
  967. avalon->device_id);
  968. avalon->shutdown = true;
  969. }
  970. /* This hashmeter is just a utility counter based on returned shares */
  971. return hash_count;
  972. }
  973. static void avalon_flush_work(struct cgpu_info *avalon)
  974. {
  975. struct avalon_info *info = avalon->device_data;
  976. mutex_lock(&info->qlock);
  977. /* Will overwrite any work queued */
  978. avalon->queued = 0;
  979. pthread_cond_signal(&info->qcond);
  980. mutex_unlock(&info->qlock);
  981. }
  982. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  983. {
  984. struct api_data *root = NULL;
  985. struct avalon_info *info = cgpu->device_data;
  986. int i;
  987. root = api_add_int(root, "baud", &(info->baud), false);
  988. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  989. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  990. root = api_add_int(root, "timeout", &(info->timeout), false);
  991. root = api_add_int(root, "frequency", &(info->frequency), false);
  992. root = api_add_int(root, "fan1", &(info->fan0), false);
  993. root = api_add_int(root, "fan2", &(info->fan1), false);
  994. root = api_add_int(root, "fan3", &(info->fan2), false);
  995. root = api_add_int(root, "temp1", &(info->temp0), false);
  996. root = api_add_int(root, "temp2", &(info->temp1), false);
  997. root = api_add_int(root, "temp3", &(info->temp2), false);
  998. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  999. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1000. for (i = 0; i < info->miner_count; i++) {
  1001. char mcw[24];
  1002. sprintf(mcw, "match_work_count%d", i + 1);
  1003. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1004. }
  1005. return root;
  1006. }
  1007. static void avalon_shutdown(struct thr_info *thr)
  1008. {
  1009. do_avalon_close(thr);
  1010. }
  1011. struct device_drv avalon_drv = {
  1012. .drv_id = DRIVER_AVALON,
  1013. .dname = "avalon",
  1014. .name = "AVA",
  1015. .drv_detect = avalon_detect,
  1016. .thread_prepare = avalon_prepare,
  1017. .hash_work = hash_queued_work,
  1018. .queue_full = avalon_fill,
  1019. .scanwork = avalon_scanhash,
  1020. .flush_work = avalon_flush_work,
  1021. .get_api_stats = avalon_api_stats,
  1022. .get_statline_before = get_avalon_statline_before,
  1023. .reinit_device = avalon_init,
  1024. .thread_shutdown = avalon_shutdown,
  1025. };