driver-avalon.c 26 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <sys/select.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #ifndef WIN32
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include "elist.h"
  33. #include "miner.h"
  34. #include "fpgautils.h"
  35. #include "driver-avalon.h"
  36. #include "hexdump.c"
  37. static int option_offset = -1;
  38. struct avalon_info **avalon_infos;
  39. struct device_drv avalon_drv;
  40. static int avalon_init_task(struct avalon_task *at,
  41. uint8_t reset, uint8_t ff, uint8_t fan,
  42. uint8_t timeout, uint8_t asic_num,
  43. uint8_t miner_num, uint8_t nonce_elf,
  44. uint8_t gate_miner, int frequency)
  45. {
  46. uint8_t *buf;
  47. static bool first = true;
  48. if (unlikely(!at))
  49. return -1;
  50. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  51. return -1;
  52. memset(at, 0, sizeof(struct avalon_task));
  53. if (unlikely(reset)) {
  54. at->reset = 1;
  55. at->fan_eft = 1;
  56. at->timer_eft = 1;
  57. first = true;
  58. }
  59. at->flush_fifo = (ff ? 1 : 0);
  60. at->fan_eft = (fan ? 1 : 0);
  61. if (unlikely(first && !at->reset)) {
  62. at->fan_eft = 1;
  63. at->timer_eft = 1;
  64. first = false;
  65. }
  66. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  67. at->timeout_data = timeout;
  68. at->asic_num = asic_num;
  69. at->miner_num = miner_num;
  70. at->nonce_elf = nonce_elf;
  71. at->gate_miner_elf = 1;
  72. at->asic_pll = 1;
  73. if (unlikely(gate_miner)) {
  74. at-> gate_miner = 1;
  75. at->asic_pll = 0;
  76. }
  77. buf = (uint8_t *)at;
  78. buf[5] = 0x00;
  79. buf[8] = 0x74;
  80. buf[9] = 0x01;
  81. buf[10] = 0x00;
  82. buf[11] = 0x00;
  83. if (frequency == 256) {
  84. buf[6] = 0x03;
  85. buf[7] = 0x08;
  86. } else if (frequency == 270) {
  87. buf[6] = 0x73;
  88. buf[7] = 0x08;
  89. } else if (frequency == 282) {
  90. buf[6] = 0xd3;
  91. buf[7] = 0x08;
  92. } else if (frequency == 300) {
  93. buf[6] = 0x63;
  94. buf[7] = 0x09;
  95. }
  96. return 0;
  97. }
  98. static inline void avalon_create_task(struct avalon_task *at,
  99. struct work *work)
  100. {
  101. memcpy(at->midstate, work->midstate, 32);
  102. memcpy(at->data, work->data + 64, 12);
  103. }
  104. static int avalon_send_task(int fd, const struct avalon_task *at,
  105. struct cgpu_info *avalon)
  106. {
  107. size_t ret;
  108. int full;
  109. struct timespec p;
  110. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  111. size_t nr_len;
  112. struct avalon_info *info;
  113. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  114. uint32_t nonce_range;
  115. int i;
  116. if (at->nonce_elf)
  117. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  118. else
  119. nr_len = AVALON_WRITE_SIZE;
  120. memcpy(buf, at, AVALON_WRITE_SIZE);
  121. if (at->nonce_elf) {
  122. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  123. for (i = 0; i < at->asic_num; i++) {
  124. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  125. (i * nonce_range & 0xff000000) >> 24;
  126. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  127. (i * nonce_range & 0x00ff0000) >> 16;
  128. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  129. (i * nonce_range & 0x0000ff00) >> 8;
  130. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  131. (i * nonce_range & 0x000000ff) >> 0;
  132. }
  133. }
  134. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  135. uint8_t tt = 0;
  136. tt = (buf[0] & 0x0f) << 4;
  137. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  138. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  139. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  140. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  141. buf[0] = tt;
  142. tt = (buf[4] & 0x0f) << 4;
  143. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  144. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  145. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  146. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  147. buf[4] = tt;
  148. #endif
  149. if (likely(avalon)) {
  150. info = avalon_infos[avalon->device_id];
  151. delay = nr_len * 10 * 1000000000ULL;
  152. delay = delay / info->baud;
  153. }
  154. if (at->reset)
  155. nr_len = 1;
  156. if (opt_debug) {
  157. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  158. hexdump((uint8_t *)buf, nr_len);
  159. }
  160. ret = write(fd, buf, nr_len);
  161. if (unlikely(ret != nr_len))
  162. return AVA_SEND_ERROR;
  163. p.tv_sec = 0;
  164. p.tv_nsec = (long)delay + 4000000;
  165. nanosleep(&p, NULL);
  166. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  167. full = avalon_buffer_full(fd);
  168. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  169. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  170. if (unlikely(full == AVA_BUFFER_FULL))
  171. return AVA_SEND_BUFFER_FULL;
  172. return AVA_SEND_BUFFER_EMPTY;
  173. }
  174. static inline int avalon_gets(int fd, uint8_t *buf, struct thr_info *thr,
  175. struct timeval *tv_finish)
  176. {
  177. int read_amount = AVALON_READ_SIZE;
  178. bool first = true;
  179. ssize_t ret = 0;
  180. while (true) {
  181. struct timeval timeout;
  182. fd_set rd;
  183. if (unlikely(thr->work_restart)) {
  184. applog(LOG_DEBUG, "Avalon: Work restart");
  185. return AVA_GETS_RESTART;
  186. }
  187. timeout.tv_sec = 0;
  188. timeout.tv_usec = 100000;
  189. FD_ZERO(&rd);
  190. FD_SET(fd, &rd);
  191. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  192. if (unlikely(ret < 0)) {
  193. applog(LOG_ERR, "Avalon: Error %d on select in avalon_gets", errno);
  194. return AVA_GETS_ERROR;
  195. }
  196. if (ret) {
  197. ret = read(fd, buf, read_amount);
  198. if (unlikely(ret < 0)) {
  199. applog(LOG_ERR, "Avalon: Error %d on read in avalon_gets", errno);
  200. return AVA_GETS_ERROR;
  201. }
  202. if (likely(first)) {
  203. gettimeofday(tv_finish, NULL);
  204. first = false;
  205. }
  206. if (likely(ret >= read_amount))
  207. return AVA_GETS_OK;
  208. buf += ret;
  209. read_amount -= ret;
  210. continue;
  211. }
  212. if (unlikely(thr->work_restart)) {
  213. applog(LOG_DEBUG, "Avalon: Work restart");
  214. return AVA_GETS_RESTART;
  215. }
  216. return AVA_GETS_TIMEOUT;
  217. }
  218. }
  219. static int avalon_get_result(int fd, struct avalon_result *ar,
  220. struct thr_info *thr, struct timeval *tv_finish)
  221. {
  222. uint8_t result[AVALON_READ_SIZE];
  223. int ret;
  224. memset(result, 0, AVALON_READ_SIZE);
  225. ret = avalon_gets(fd, result, thr, tv_finish);
  226. if (ret == AVA_GETS_OK) {
  227. if (opt_debug) {
  228. applog(LOG_DEBUG, "Avalon: get:");
  229. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  230. }
  231. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  232. }
  233. return ret;
  234. }
  235. static bool avalon_decode_nonce(struct thr_info *thr, struct avalon_result *ar,
  236. uint32_t *nonce)
  237. {
  238. struct cgpu_info *avalon;
  239. struct avalon_info *info;
  240. struct work *work;
  241. avalon = thr->cgpu;
  242. if (unlikely(!avalon->works))
  243. return false;
  244. work = find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  245. (char *)ar->data, 64, 12);
  246. if (!work)
  247. return false;
  248. info = avalon_infos[avalon->device_id];
  249. info->matching_work[work->subid]++;
  250. *nonce = htole32(ar->nonce);
  251. submit_nonce(thr, work, *nonce);
  252. return true;
  253. }
  254. static void avalon_get_reset(int fd, struct avalon_result *ar)
  255. {
  256. int read_amount = AVALON_READ_SIZE;
  257. uint8_t result[AVALON_READ_SIZE];
  258. struct timeval timeout = {1, 0};
  259. ssize_t ret = 0, offset = 0;
  260. fd_set rd;
  261. memset(result, 0, AVALON_READ_SIZE);
  262. memset(ar, 0, AVALON_READ_SIZE);
  263. FD_ZERO(&rd);
  264. FD_SET(fd, &rd);
  265. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  266. if (unlikely(ret < 0)) {
  267. applog(LOG_WARNING, "Avalon: Error %d on select in avalon_get_reset", errno);
  268. return;
  269. }
  270. if (!ret) {
  271. applog(LOG_WARNING, "Avalon: Timeout on select in avalon_get_reset");
  272. return;
  273. }
  274. do {
  275. ret = read(fd, result + offset, read_amount);
  276. if (unlikely(ret < 0)) {
  277. applog(LOG_WARNING, "Avalon: Error %d on read in avalon_get_reset", errno);
  278. return;
  279. }
  280. read_amount -= ret;
  281. offset += ret;
  282. } while (read_amount > 0);
  283. if (opt_debug) {
  284. applog(LOG_DEBUG, "Avalon: get:");
  285. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  286. }
  287. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  288. }
  289. static int avalon_reset(int fd, struct avalon_result *ar)
  290. {
  291. struct avalon_task at;
  292. uint8_t *buf;
  293. int ret, i = 0;
  294. struct timespec p;
  295. avalon_init_task(&at, 1, 0,
  296. AVALON_DEFAULT_FAN_MAX_PWM,
  297. AVALON_DEFAULT_TIMEOUT,
  298. AVALON_DEFAULT_ASIC_NUM,
  299. AVALON_DEFAULT_MINER_NUM,
  300. 0, 0,
  301. AVALON_DEFAULT_FREQUENCY);
  302. ret = avalon_send_task(fd, &at, NULL);
  303. if (ret == AVA_SEND_ERROR)
  304. return 1;
  305. avalon_get_reset(fd, ar);
  306. buf = (uint8_t *)ar;
  307. /* Sometimes there is one extra 0 byte for some reason in the buffer,
  308. * so work around it. */
  309. if (buf[0] == 0)
  310. buf = (uint8_t *)(ar + 1);
  311. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  312. buf[2] == 0xAA && buf[3] == 0x55) {
  313. for (i = 4; i < 11; i++)
  314. if (buf[i] != 0)
  315. break;
  316. }
  317. p.tv_sec = 0;
  318. p.tv_nsec = AVALON_RESET_PITCH;
  319. nanosleep(&p, NULL);
  320. if (i != 11) {
  321. applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
  322. " (%d: %02x %02x %02x %02x)",
  323. i, buf[0], buf[1], buf[2], buf[3]);
  324. /* FIXME: return 1; */
  325. } else
  326. applog(LOG_WARNING, "Avalon: Reset succeeded");
  327. return 0;
  328. }
  329. static void avalon_idle(struct cgpu_info *avalon)
  330. {
  331. int i, ret;
  332. struct avalon_task at;
  333. int fd = avalon->device_fd;
  334. struct avalon_info *info = avalon_infos[avalon->device_id];
  335. int avalon_get_work_count = info->miner_count;
  336. i = 0;
  337. while (true) {
  338. avalon_init_task(&at, 0, 0, info->fan_pwm,
  339. info->timeout, info->asic_count,
  340. info->miner_count, 1, 1, info->frequency);
  341. ret = avalon_send_task(fd, &at, avalon);
  342. if (unlikely(ret == AVA_SEND_ERROR ||
  343. (ret == AVA_SEND_BUFFER_EMPTY &&
  344. (i + 1 == avalon_get_work_count * 2)))) {
  345. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  346. return;
  347. }
  348. if (i + 1 == avalon_get_work_count * 2)
  349. break;
  350. if (ret == AVA_SEND_BUFFER_FULL)
  351. break;
  352. i++;
  353. }
  354. applog(LOG_ERR, "Avalon: Goto idle mode");
  355. }
  356. static void get_options(int this_option_offset, int *baud, int *miner_count,
  357. int *asic_count, int *timeout, int *frequency)
  358. {
  359. char err_buf[BUFSIZ+1];
  360. char buf[BUFSIZ+1];
  361. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  362. size_t max;
  363. int i, tmp;
  364. if (opt_avalon_options == NULL)
  365. buf[0] = '\0';
  366. else {
  367. ptr = opt_avalon_options;
  368. for (i = 0; i < this_option_offset; i++) {
  369. comma = strchr(ptr, ',');
  370. if (comma == NULL)
  371. break;
  372. ptr = comma + 1;
  373. }
  374. comma = strchr(ptr, ',');
  375. if (comma == NULL)
  376. max = strlen(ptr);
  377. else
  378. max = comma - ptr;
  379. if (max > BUFSIZ)
  380. max = BUFSIZ;
  381. strncpy(buf, ptr, max);
  382. buf[max] = '\0';
  383. }
  384. *baud = AVALON_IO_SPEED;
  385. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  386. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  387. *timeout = AVALON_DEFAULT_TIMEOUT;
  388. *frequency = AVALON_DEFAULT_FREQUENCY;
  389. if (!(*buf))
  390. return;
  391. colon = strchr(buf, ':');
  392. if (colon)
  393. *(colon++) = '\0';
  394. tmp = atoi(buf);
  395. switch (tmp) {
  396. case 115200:
  397. *baud = 115200;
  398. break;
  399. case 57600:
  400. *baud = 57600;
  401. break;
  402. case 38400:
  403. *baud = 38400;
  404. break;
  405. case 19200:
  406. *baud = 19200;
  407. break;
  408. default:
  409. sprintf(err_buf,
  410. "Invalid avalon-options for baud (%s) "
  411. "must be 115200, 57600, 38400 or 19200", buf);
  412. quit(1, err_buf);
  413. }
  414. if (colon && *colon) {
  415. colon2 = strchr(colon, ':');
  416. if (colon2)
  417. *(colon2++) = '\0';
  418. if (*colon) {
  419. tmp = atoi(colon);
  420. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  421. *miner_count = tmp;
  422. } else {
  423. sprintf(err_buf,
  424. "Invalid avalon-options for "
  425. "miner_count (%s) must be 1 ~ %d",
  426. colon, AVALON_DEFAULT_MINER_NUM);
  427. quit(1, err_buf);
  428. }
  429. }
  430. if (colon2 && *colon2) {
  431. colon3 = strchr(colon2, ':');
  432. if (colon3)
  433. *(colon3++) = '\0';
  434. tmp = atoi(colon2);
  435. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  436. *asic_count = tmp;
  437. else {
  438. sprintf(err_buf,
  439. "Invalid avalon-options for "
  440. "asic_count (%s) must be 1 ~ %d",
  441. colon2, AVALON_DEFAULT_ASIC_NUM);
  442. quit(1, err_buf);
  443. }
  444. if (colon3 && *colon3) {
  445. colon4 = strchr(colon3, ':');
  446. if (colon4)
  447. *(colon4++) = '\0';
  448. tmp = atoi(colon3);
  449. if (tmp > 0 && tmp <= 0xff)
  450. *timeout = tmp;
  451. else {
  452. sprintf(err_buf,
  453. "Invalid avalon-options for "
  454. "timeout (%s) must be 1 ~ %d",
  455. colon3, 0xff);
  456. quit(1, err_buf);
  457. }
  458. if (colon4 && *colon4) {
  459. tmp = atoi(colon4);
  460. switch (tmp) {
  461. case 256:
  462. case 270:
  463. case 282:
  464. case 300:
  465. *frequency = tmp;
  466. break;
  467. default:
  468. sprintf(err_buf,
  469. "Invalid avalon-options for "
  470. "frequency must be 256/270/282/300");
  471. quit(1, err_buf);
  472. }
  473. }
  474. }
  475. }
  476. }
  477. }
  478. static bool avalon_detect_one(const char *devpath)
  479. {
  480. struct avalon_info *info;
  481. struct avalon_result ar;
  482. int fd, ret;
  483. int baud, miner_count, asic_count, timeout, frequency = 0;
  484. struct cgpu_info *avalon;
  485. int this_option_offset = ++option_offset;
  486. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  487. &timeout, &frequency);
  488. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  489. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  490. devpath, baud, miner_count, asic_count, timeout, frequency);
  491. fd = avalon_open2(devpath, baud, true);
  492. if (unlikely(fd == -1)) {
  493. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  494. return false;
  495. }
  496. /* We have a real Avalon! */
  497. avalon = calloc(1, sizeof(struct cgpu_info));
  498. avalon->drv = &avalon_drv;
  499. avalon->device_path = strdup(devpath);
  500. avalon->device_fd = fd;
  501. avalon->threads = AVALON_MINER_THREADS;
  502. add_cgpu(avalon);
  503. ret = avalon_reset(fd, &ar);
  504. if (ret) {
  505. ; /* FIXME: I think IT IS avalon and wait on reset;
  506. * avalon_close(fd);
  507. * return false; */
  508. }
  509. avalon_infos = realloc(avalon_infos,
  510. sizeof(struct avalon_info *) *
  511. (total_devices + 1));
  512. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  513. devpath, avalon->device_id);
  514. avalon_infos[avalon->device_id] = (struct avalon_info *)
  515. malloc(sizeof(struct avalon_info));
  516. if (unlikely(!(avalon_infos[avalon->device_id])))
  517. quit(1, "Failed to malloc avalon_infos");
  518. info = avalon_infos[avalon->device_id];
  519. memset(info, 0, sizeof(struct avalon_info));
  520. info->baud = baud;
  521. info->miner_count = miner_count;
  522. info->asic_count = asic_count;
  523. info->timeout = timeout;
  524. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  525. info->temp_max = 0;
  526. /* This is for check the temp/fan every 3~4s */
  527. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  528. if (info->temp_history_count <= 0)
  529. info->temp_history_count = 1;
  530. info->temp_history_index = 0;
  531. info->temp_sum = 0;
  532. info->temp_old = 0;
  533. info->frequency = frequency;
  534. /* Do something for failed reset ? */
  535. if (0) {
  536. /* Set asic to idle mode after detect */
  537. avalon_idle(avalon);
  538. avalon->device_fd = -1;
  539. avalon_close(fd);
  540. }
  541. return true;
  542. }
  543. static inline void avalon_detect()
  544. {
  545. serial_detect(&avalon_drv, avalon_detect_one);
  546. }
  547. static void __avalon_init(struct cgpu_info *avalon)
  548. {
  549. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  550. }
  551. static void avalon_init(struct cgpu_info *avalon)
  552. {
  553. struct avalon_result ar;
  554. int fd, ret;
  555. avalon->device_fd = -1;
  556. fd = avalon_open(avalon->device_path,
  557. avalon_infos[avalon->device_id]->baud);
  558. if (unlikely(fd == -1)) {
  559. applog(LOG_ERR, "Avalon: Failed to open on %s",
  560. avalon->device_path);
  561. return;
  562. }
  563. ret = avalon_reset(fd, &ar);
  564. if (ret) {
  565. avalon_close(fd);
  566. return;
  567. }
  568. avalon->device_fd = fd;
  569. __avalon_init(avalon);
  570. }
  571. static bool avalon_prepare(struct thr_info *thr)
  572. {
  573. struct cgpu_info *avalon = thr->cgpu;
  574. struct avalon_info *info = avalon_infos[avalon->device_id];
  575. struct timeval now;
  576. free(avalon->works);
  577. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  578. AVALON_ARRAY_SIZE);
  579. if (!avalon->works)
  580. quit(1, "Failed to calloc avalon works in avalon_prepare");
  581. if (avalon->device_fd == -1)
  582. avalon_init(avalon);
  583. else
  584. __avalon_init(avalon);
  585. gettimeofday(&now, NULL);
  586. get_datestamp(avalon->init, &now);
  587. return true;
  588. }
  589. static void avalon_free_work(struct thr_info *thr)
  590. {
  591. struct cgpu_info *avalon;
  592. struct avalon_info *info;
  593. struct work **works;
  594. int i;
  595. avalon = thr->cgpu;
  596. avalon->queued = 0;
  597. if (unlikely(!avalon->works))
  598. return;
  599. works = avalon->works;
  600. info = avalon_infos[avalon->device_id];
  601. for (i = 0; i < info->miner_count * 4; i++) {
  602. if (works[i]) {
  603. work_completed(avalon, works[i]);
  604. works[i] = NULL;
  605. }
  606. }
  607. }
  608. static void do_avalon_close(struct thr_info *thr)
  609. {
  610. struct avalon_result ar;
  611. struct cgpu_info *avalon = thr->cgpu;
  612. struct avalon_info *info = avalon_infos[avalon->device_id];
  613. avalon_free_work(thr);
  614. sleep(1);
  615. avalon_reset(avalon->device_fd, &ar);
  616. avalon_idle(avalon);
  617. avalon_close(avalon->device_fd);
  618. avalon->device_fd = -1;
  619. info->no_matching_work = 0;
  620. }
  621. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  622. {
  623. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  624. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  625. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  626. info->temp0 = ar->temp0;
  627. info->temp1 = ar->temp1;
  628. info->temp2 = ar->temp2;
  629. if (ar->temp0 & 0x80) {
  630. ar->temp0 &= 0x7f;
  631. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  632. }
  633. if (ar->temp1 & 0x80) {
  634. ar->temp1 &= 0x7f;
  635. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  636. }
  637. if (ar->temp2 & 0x80) {
  638. ar->temp2 &= 0x7f;
  639. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  640. }
  641. *temp_avg = info->temp2;
  642. if (info->temp0 > info->temp_max)
  643. info->temp_max = info->temp0;
  644. if (info->temp1 > info->temp_max)
  645. info->temp_max = info->temp1;
  646. if (info->temp2 > info->temp_max)
  647. info->temp_max = info->temp2;
  648. }
  649. static inline void adjust_fan(struct avalon_info *info)
  650. {
  651. int temp_new;
  652. temp_new = info->temp_sum / info->temp_history_count;
  653. if (temp_new < 35) {
  654. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  655. info->temp_old = temp_new;
  656. } else if (temp_new > 55) {
  657. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  658. info->temp_old = temp_new;
  659. } else if (abs(temp_new - info->temp_old) >= 2) {
  660. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  661. info->temp_old = temp_new;
  662. }
  663. }
  664. /* We use a replacement algorithm to only remove references to work done from
  665. * the buffer when we need the extra space for new work. */
  666. static bool avalon_fill(struct cgpu_info *avalon)
  667. {
  668. int subid, slot, mc = avalon_infos[avalon->device_id]->miner_count;
  669. struct work *work;
  670. if (avalon->queued >= mc)
  671. return true;
  672. work = get_queued(avalon);
  673. if (unlikely(!work))
  674. return false;
  675. subid = avalon->queued++;
  676. work->subid = subid;
  677. slot = avalon->work_array * mc + subid;
  678. if (likely(avalon->works[slot]))
  679. work_completed(avalon, avalon->works[slot]);
  680. avalon->works[slot] = work;
  681. if (avalon->queued >= mc)
  682. return true;
  683. return false;
  684. }
  685. static void avalon_rotate_array(struct cgpu_info *avalon)
  686. {
  687. avalon->queued = 0;
  688. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  689. avalon->work_array = 0;
  690. }
  691. static int64_t avalon_scanhash(struct thr_info *thr)
  692. {
  693. struct cgpu_info *avalon;
  694. struct work **works;
  695. int fd, ret = AVA_GETS_OK, full;
  696. struct avalon_info *info;
  697. struct avalon_task at;
  698. struct avalon_result ar;
  699. int i;
  700. int avalon_get_work_count;
  701. int start_count, end_count;
  702. struct timeval tv_start, tv_finish, elapsed;
  703. uint32_t nonce;
  704. int64_t hash_count;
  705. static int first_try = 0;
  706. int result_wrong;
  707. avalon = thr->cgpu;
  708. works = avalon->works;
  709. info = avalon_infos[avalon->device_id];
  710. avalon_get_work_count = info->miner_count;
  711. if (unlikely(avalon->device_fd == -1)) {
  712. if (!avalon_prepare(thr)) {
  713. applog(LOG_ERR, "AVA%i: Comms error(open)",
  714. avalon->device_id);
  715. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  716. /* fail the device if the reopen attempt fails */
  717. return -1;
  718. }
  719. }
  720. fd = avalon->device_fd;
  721. #ifndef WIN32
  722. tcflush(fd, TCOFLUSH);
  723. #endif
  724. start_count = avalon->work_array * avalon_get_work_count;
  725. end_count = start_count + avalon_get_work_count;
  726. i = start_count;
  727. while (true) {
  728. avalon_init_task(&at, 0, 0, info->fan_pwm,
  729. info->timeout, info->asic_count,
  730. info->miner_count, 1, 0, info->frequency);
  731. avalon_create_task(&at, works[i]);
  732. ret = avalon_send_task(fd, &at, avalon);
  733. if (unlikely(ret == AVA_SEND_ERROR ||
  734. (ret == AVA_SEND_BUFFER_EMPTY &&
  735. (i + 1 == end_count) &&
  736. first_try))) {
  737. do_avalon_close(thr);
  738. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  739. avalon->device_id);
  740. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  741. first_try = 0;
  742. sleep(1);
  743. avalon_init(avalon);
  744. return 0; /* This should never happen */
  745. }
  746. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == end_count)) {
  747. first_try = 1;
  748. avalon_rotate_array(avalon);
  749. return 0xffffffff;
  750. }
  751. works[i]->blk.nonce = 0xffffffff;
  752. if (ret == AVA_SEND_BUFFER_FULL)
  753. break;
  754. i++;
  755. }
  756. if (unlikely(first_try))
  757. first_try = 0;
  758. elapsed.tv_sec = elapsed.tv_usec = 0;
  759. gettimeofday(&tv_start, NULL);
  760. result_wrong = 0;
  761. hash_count = 0;
  762. while (true) {
  763. full = avalon_buffer_full(fd);
  764. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  765. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  766. if (unlikely(full == AVA_BUFFER_EMPTY))
  767. break;
  768. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  769. if (unlikely(ret == AVA_GETS_ERROR)) {
  770. do_avalon_close(thr);
  771. applog(LOG_ERR,
  772. "AVA%i: Comms error(read)", avalon->device_id);
  773. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  774. return 0;
  775. }
  776. if (unlikely(ret == AVA_GETS_RESTART))
  777. break;
  778. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  779. timersub(&tv_finish, &tv_start, &elapsed);
  780. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  781. elapsed.tv_sec, elapsed.tv_usec);
  782. continue;
  783. }
  784. if (!avalon_decode_nonce(thr, &ar, &nonce)) {
  785. info->no_matching_work++;
  786. result_wrong++;
  787. if (opt_debug) {
  788. timersub(&tv_finish, &tv_start, &elapsed);
  789. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  790. " (%ld.%06lds)", info->no_matching_work,
  791. elapsed.tv_sec, elapsed.tv_usec);
  792. }
  793. continue;
  794. }
  795. hash_count += 0xffffffff;
  796. if (opt_debug) {
  797. timersub(&tv_finish, &tv_start, &elapsed);
  798. applog(LOG_DEBUG,
  799. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  800. "(%ld.%06lds)", nonce, hash_count,
  801. elapsed.tv_sec, elapsed.tv_usec);
  802. }
  803. }
  804. if (result_wrong >= avalon_get_work_count) {
  805. /* This means FPGA controller gave all wrong results, so
  806. * try to reset the Avalon */
  807. do_avalon_close(thr);
  808. applog(LOG_ERR,
  809. "AVA%i: FPGA controller mess up, %d wrong results", avalon->device_id, result_wrong);
  810. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  811. sleep(1);
  812. avalon_init(avalon);
  813. return 0;
  814. }
  815. avalon_rotate_array(avalon);
  816. record_temp_fan(info, &ar, &(avalon->temp));
  817. applog(LOG_INFO,
  818. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  819. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  820. info->fan0, info->fan1, info->fan2,
  821. info->temp0, info->temp1, info->temp2, info->temp_max);
  822. info->temp_history_index++;
  823. info->temp_sum += info->temp2;
  824. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  825. info->temp_history_index, info->temp_history_count, info->temp_old);
  826. if (info->temp_history_index == info->temp_history_count) {
  827. adjust_fan(info);
  828. info->temp_history_index = 0;
  829. info->temp_sum = 0;
  830. }
  831. /* This hashmeter is just a utility counter based on returned shares */
  832. return hash_count;
  833. }
  834. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  835. {
  836. struct api_data *root = NULL;
  837. struct avalon_info *info = avalon_infos[cgpu->device_id];
  838. root = api_add_int(root, "baud", &(info->baud), false);
  839. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  840. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  841. root = api_add_int(root, "timeout", &(info->timeout), false);
  842. root = api_add_int(root, "frequency", &(info->frequency), false);
  843. root = api_add_int(root, "fan1", &(info->fan0), false);
  844. root = api_add_int(root, "fan2", &(info->fan1), false);
  845. root = api_add_int(root, "fan3", &(info->fan2), false);
  846. root = api_add_int(root, "temp1", &(info->temp0), false);
  847. root = api_add_int(root, "temp2", &(info->temp1), false);
  848. root = api_add_int(root, "temp3", &(info->temp2), false);
  849. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  850. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  851. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  852. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  853. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  854. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  855. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  856. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  857. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  858. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  859. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  860. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  861. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  862. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  863. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  864. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  865. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  866. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  867. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  868. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  869. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  870. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  871. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  872. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  873. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  874. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  875. return root;
  876. }
  877. static void avalon_shutdown(struct thr_info *thr)
  878. {
  879. do_avalon_close(thr);
  880. }
  881. struct device_drv avalon_drv = {
  882. .drv_id = DRIVER_AVALON,
  883. .dname = "avalon",
  884. .name = "AVA",
  885. .drv_detect = avalon_detect,
  886. .thread_prepare = avalon_prepare,
  887. .hash_work = hash_queued_work,
  888. .queue_full = avalon_fill,
  889. .scanwork = avalon_scanhash,
  890. .get_api_stats = avalon_api_stats,
  891. .reinit_device = avalon_init,
  892. .thread_shutdown = avalon_shutdown,
  893. };