driver-avalon.c 42 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #include <time.h>
  22. #ifndef WIN32
  23. #include <sys/select.h>
  24. #include <termios.h>
  25. #include <sys/stat.h>
  26. #include <fcntl.h>
  27. #ifndef O_CLOEXEC
  28. #define O_CLOEXEC 0
  29. #endif
  30. #else
  31. #include "compat.h"
  32. #include <windows.h>
  33. #include <io.h>
  34. #endif
  35. #include "elist.h"
  36. #include "miner.h"
  37. #include "usbutils.h"
  38. #include "driver-avalon.h"
  39. #include "hexdump.c"
  40. #include "util.h"
  41. int opt_avalon_temp = AVALON_TEMP_TARGET;
  42. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  43. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  44. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  45. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  46. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  47. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  48. bool opt_avalon_auto;
  49. static int option_offset = -1;
  50. struct device_drv avalon_drv;
  51. static int avalon_init_task(struct avalon_task *at,
  52. uint8_t reset, uint8_t ff, uint8_t fan,
  53. uint8_t timeout, uint8_t asic_num,
  54. uint8_t miner_num, uint8_t nonce_elf,
  55. uint8_t gate_miner, int frequency)
  56. {
  57. uint16_t *lefreq16;
  58. uint8_t *buf;
  59. static bool first = true;
  60. if (unlikely(!at))
  61. return -1;
  62. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  63. return -1;
  64. memset(at, 0, sizeof(struct avalon_task));
  65. if (unlikely(reset)) {
  66. at->reset = 1;
  67. at->fan_eft = 1;
  68. at->timer_eft = 1;
  69. first = true;
  70. }
  71. at->flush_fifo = (ff ? 1 : 0);
  72. at->fan_eft = (fan ? 1 : 0);
  73. if (unlikely(first && !at->reset)) {
  74. at->fan_eft = 1;
  75. at->timer_eft = 1;
  76. first = false;
  77. }
  78. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  79. at->timeout_data = timeout;
  80. at->asic_num = asic_num;
  81. at->miner_num = miner_num;
  82. at->nonce_elf = nonce_elf;
  83. at->gate_miner_elf = 1;
  84. at->asic_pll = 1;
  85. if (unlikely(gate_miner)) {
  86. at-> gate_miner = 1;
  87. at->asic_pll = 0;
  88. }
  89. buf = (uint8_t *)at;
  90. buf[5] = 0x00;
  91. buf[8] = 0x74;
  92. buf[9] = 0x01;
  93. buf[10] = 0x00;
  94. buf[11] = 0x00;
  95. lefreq16 = (uint16_t *)&buf[6];
  96. *lefreq16 = htole16(frequency * 8);
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  106. {
  107. int err, amount;
  108. err = usb_write(avalon, buf, len, &amount, ep);
  109. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  110. avalon->device_id, err);
  111. if (unlikely(err != 0)) {
  112. applog(LOG_WARNING, "usb_write error on avalon_write");
  113. return AVA_SEND_ERROR;
  114. }
  115. if (amount != len) {
  116. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  117. return AVA_SEND_ERROR;
  118. }
  119. return AVA_SEND_OK;
  120. }
  121. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  122. {
  123. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  124. int delay, ret, i, ep = C_AVALON_TASK;
  125. struct avalon_info *info;
  126. cgtimer_t ts_start;
  127. uint32_t nonce_range;
  128. size_t nr_len;
  129. if (at->nonce_elf)
  130. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  131. else
  132. nr_len = AVALON_WRITE_SIZE;
  133. memcpy(buf, at, AVALON_WRITE_SIZE);
  134. if (at->nonce_elf) {
  135. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  136. for (i = 0; i < at->asic_num; i++) {
  137. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  138. (i * nonce_range & 0xff000000) >> 24;
  139. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  140. (i * nonce_range & 0x00ff0000) >> 16;
  141. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  142. (i * nonce_range & 0x0000ff00) >> 8;
  143. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  144. (i * nonce_range & 0x000000ff) >> 0;
  145. }
  146. }
  147. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  148. uint8_t tt = 0;
  149. tt = (buf[0] & 0x0f) << 4;
  150. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  151. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  152. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  153. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  154. buf[0] = tt;
  155. tt = (buf[4] & 0x0f) << 4;
  156. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  157. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  158. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  159. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  160. buf[4] = tt;
  161. #endif
  162. info = avalon->device_data;
  163. delay = nr_len * 10 * 1000000;
  164. delay = delay / info->baud;
  165. delay += 4000;
  166. if (at->reset) {
  167. ep = C_AVALON_RESET;
  168. nr_len = 1;
  169. }
  170. if (opt_debug) {
  171. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  172. hexdump(buf, nr_len);
  173. }
  174. cgsleep_prepare_r(&ts_start);
  175. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  176. cgsleep_us_r(&ts_start, delay);
  177. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  178. return ret;
  179. }
  180. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  181. struct avalon_info *info, struct avalon_result *ar,
  182. struct work *work)
  183. {
  184. uint32_t nonce;
  185. info = avalon->device_data;
  186. info->matching_work[work->subid]++;
  187. nonce = htole32(ar->nonce);
  188. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  189. return submit_nonce(thr, work, nonce);
  190. }
  191. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  192. static void wait_avalon_ready(struct cgpu_info *avalon)
  193. {
  194. while (avalon_buffer_full(avalon)) {
  195. cgsleep_ms(40);
  196. }
  197. }
  198. #define AVALON_CTS (1 << 4)
  199. static inline bool avalon_cts(char c)
  200. {
  201. return (c & AVALON_CTS);
  202. }
  203. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  204. size_t bufsize, int timeout, int ep)
  205. {
  206. size_t total = 0, readsize = bufsize + 2;
  207. char readbuf[AVALON_READBUF_SIZE];
  208. int err, amount, ofs = 2, cp;
  209. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  210. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  211. avalon->drv->name, avalon->device_id, err);
  212. if (amount < 2)
  213. goto out;
  214. /* The first 2 of every 64 bytes are status on FTDIRL */
  215. while (amount > 2) {
  216. cp = amount - 2;
  217. if (cp > 62)
  218. cp = 62;
  219. memcpy(&buf[total], &readbuf[ofs], cp);
  220. total += cp;
  221. amount -= cp + 2;
  222. ofs += 64;
  223. }
  224. out:
  225. return total;
  226. }
  227. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  228. {
  229. struct avalon_result ar;
  230. int ret, i, spare;
  231. struct avalon_task at;
  232. uint8_t *buf, *tmp;
  233. struct timespec p;
  234. struct avalon_info *info = avalon->device_data;
  235. /* Send reset, then check for result */
  236. avalon_init_task(&at, 1, 0,
  237. AVALON_DEFAULT_FAN_MAX_PWM,
  238. AVALON_DEFAULT_TIMEOUT,
  239. AVALON_DEFAULT_ASIC_NUM,
  240. AVALON_DEFAULT_MINER_NUM,
  241. 0, 0,
  242. AVALON_DEFAULT_FREQUENCY);
  243. wait_avalon_ready(avalon);
  244. ret = avalon_send_task(&at, avalon);
  245. if (unlikely(ret == AVA_SEND_ERROR))
  246. return -1;
  247. if (!initial) {
  248. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  249. return 0;
  250. }
  251. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  252. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  253. /* What do these sleeps do?? */
  254. p.tv_sec = 0;
  255. p.tv_nsec = AVALON_RESET_PITCH;
  256. nanosleep(&p, NULL);
  257. /* Look for the first occurrence of 0xAA, the reset response should be:
  258. * AA 55 AA 55 00 00 00 00 00 00 */
  259. spare = ret - 10;
  260. buf = tmp = (uint8_t *)&ar;
  261. if (opt_debug) {
  262. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  263. hexdump(tmp, AVALON_READ_SIZE);
  264. }
  265. for (i = 0; i <= spare; i++) {
  266. buf = &tmp[i];
  267. if (buf[0] == 0xAA)
  268. break;
  269. }
  270. i = 0;
  271. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  272. buf[2] == 0xAA && buf[3] == 0x55) {
  273. for (i = 4; i < 11; i++)
  274. if (buf[i] != 0)
  275. break;
  276. }
  277. if (i != 11) {
  278. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  279. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  280. i, buf[0], buf[1], buf[2], buf[3]);
  281. /* FIXME: return 1; */
  282. } else {
  283. /* buf[44]: minor
  284. * buf[45]: day
  285. * buf[46]: year,month, d6: 201306
  286. */
  287. info->ctlr_ver = ((buf[46] >> 4) + 2000) * 1000000 +
  288. (buf[46] & 0x0f) * 10000 +
  289. buf[45] * 100 + buf[44];
  290. applog(LOG_WARNING, "%s%d: Reset succeeded (Controller version: %d)",
  291. avalon->drv->name, avalon->device_id, info->ctlr_ver);
  292. }
  293. return 0;
  294. }
  295. static int avalon_calc_timeout(int frequency)
  296. {
  297. return AVALON_TIMEOUT_FACTOR / frequency;
  298. }
  299. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  300. int *asic_count, int *timeout, int *frequency)
  301. {
  302. char buf[BUFSIZ+1];
  303. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  304. bool timeout_default;
  305. size_t max;
  306. int i, tmp;
  307. if (opt_avalon_options == NULL)
  308. buf[0] = '\0';
  309. else {
  310. ptr = opt_avalon_options;
  311. for (i = 0; i < this_option_offset; i++) {
  312. comma = strchr(ptr, ',');
  313. if (comma == NULL)
  314. break;
  315. ptr = comma + 1;
  316. }
  317. comma = strchr(ptr, ',');
  318. if (comma == NULL)
  319. max = strlen(ptr);
  320. else
  321. max = comma - ptr;
  322. if (max > BUFSIZ)
  323. max = BUFSIZ;
  324. strncpy(buf, ptr, max);
  325. buf[max] = '\0';
  326. }
  327. if (!(*buf))
  328. return false;
  329. colon = strchr(buf, ':');
  330. if (colon)
  331. *(colon++) = '\0';
  332. tmp = atoi(buf);
  333. switch (tmp) {
  334. case 115200:
  335. *baud = 115200;
  336. break;
  337. case 57600:
  338. *baud = 57600;
  339. break;
  340. case 38400:
  341. *baud = 38400;
  342. break;
  343. case 19200:
  344. *baud = 19200;
  345. break;
  346. default:
  347. quit(1, "Invalid avalon-options for baud (%s) "
  348. "must be 115200, 57600, 38400 or 19200", buf);
  349. }
  350. if (colon && *colon) {
  351. colon2 = strchr(colon, ':');
  352. if (colon2)
  353. *(colon2++) = '\0';
  354. if (*colon) {
  355. tmp = atoi(colon);
  356. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  357. *miner_count = tmp;
  358. } else {
  359. quit(1, "Invalid avalon-options for "
  360. "miner_count (%s) must be 1 ~ %d",
  361. colon, AVALON_DEFAULT_MINER_NUM);
  362. }
  363. }
  364. if (colon2 && *colon2) {
  365. colon3 = strchr(colon2, ':');
  366. if (colon3)
  367. *(colon3++) = '\0';
  368. tmp = atoi(colon2);
  369. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  370. *asic_count = tmp;
  371. else {
  372. quit(1, "Invalid avalon-options for "
  373. "asic_count (%s) must be 1 ~ %d",
  374. colon2, AVALON_DEFAULT_ASIC_NUM);
  375. }
  376. timeout_default = false;
  377. if (colon3 && *colon3) {
  378. colon4 = strchr(colon3, ':');
  379. if (colon4)
  380. *(colon4++) = '\0';
  381. if (tolower(*colon3) == 'd')
  382. timeout_default = true;
  383. else {
  384. tmp = atoi(colon3);
  385. if (tmp > 0 && tmp <= 0xff)
  386. *timeout = tmp;
  387. else {
  388. quit(1, "Invalid avalon-options for "
  389. "timeout (%s) must be 1 ~ %d",
  390. colon3, 0xff);
  391. }
  392. }
  393. if (colon4 && *colon4) {
  394. tmp = atoi(colon4);
  395. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  396. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  397. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  398. }
  399. *frequency = tmp;
  400. if (timeout_default)
  401. *timeout = avalon_calc_timeout(*frequency);
  402. }
  403. }
  404. }
  405. }
  406. return true;
  407. }
  408. char *set_avalon_fan(char *arg)
  409. {
  410. int val1, val2, ret;
  411. ret = sscanf(arg, "%d-%d", &val1, &val2);
  412. if (ret < 1)
  413. return "No values passed to avalon-fan";
  414. if (ret == 1)
  415. val2 = val1;
  416. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  417. return "Invalid value passed to avalon-fan";
  418. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  419. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  420. return NULL;
  421. }
  422. char *set_avalon_freq(char *arg)
  423. {
  424. int val1, val2, ret;
  425. ret = sscanf(arg, "%d-%d", &val1, &val2);
  426. if (ret < 1)
  427. return "No values passed to avalon-freq";
  428. if (ret == 1)
  429. val2 = val1;
  430. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  431. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  432. val2 < val1)
  433. return "Invalid value passed to avalon-freq";
  434. opt_avalon_freq_min = val1;
  435. opt_avalon_freq_max = val2;
  436. return NULL;
  437. }
  438. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  439. {
  440. int i;
  441. wait_avalon_ready(avalon);
  442. /* Send idle to all miners */
  443. for (i = 0; i < info->miner_count; i++) {
  444. struct avalon_task at;
  445. if (unlikely(avalon_buffer_full(avalon)))
  446. break;
  447. info->idle++;
  448. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  449. info->asic_count, info->miner_count, 1, 1,
  450. info->frequency);
  451. avalon_send_task(&at, avalon);
  452. }
  453. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  454. wait_avalon_ready(avalon);
  455. }
  456. static void avalon_initialise(struct cgpu_info *avalon)
  457. {
  458. int err, interface;
  459. if (avalon->usbinfo.nodev)
  460. return;
  461. interface = usb_interface(avalon);
  462. // Reset
  463. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  464. FTDI_VALUE_RESET, interface, C_RESET);
  465. applog(LOG_DEBUG, "%s%i: reset got err %d",
  466. avalon->drv->name, avalon->device_id, err);
  467. if (avalon->usbinfo.nodev)
  468. return;
  469. // Set latency
  470. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  471. AVALON_LATENCY, interface, C_LATENCY);
  472. applog(LOG_DEBUG, "%s%i: latency got err %d",
  473. avalon->drv->name, avalon->device_id, err);
  474. if (avalon->usbinfo.nodev)
  475. return;
  476. // Set data
  477. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  478. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  479. applog(LOG_DEBUG, "%s%i: data got err %d",
  480. avalon->drv->name, avalon->device_id, err);
  481. if (avalon->usbinfo.nodev)
  482. return;
  483. // Set the baud
  484. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  485. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  486. C_SETBAUD);
  487. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  488. avalon->drv->name, avalon->device_id, err);
  489. if (avalon->usbinfo.nodev)
  490. return;
  491. // Set Modem Control
  492. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  493. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  494. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  495. avalon->drv->name, avalon->device_id, err);
  496. if (avalon->usbinfo.nodev)
  497. return;
  498. // Set Flow Control
  499. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  500. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  501. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  502. avalon->drv->name, avalon->device_id, err);
  503. if (avalon->usbinfo.nodev)
  504. return;
  505. /* Avalon repeats the following */
  506. // Set Modem Control
  507. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  508. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  509. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  510. avalon->drv->name, avalon->device_id, err);
  511. if (avalon->usbinfo.nodev)
  512. return;
  513. // Set Flow Control
  514. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  515. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  516. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  517. avalon->drv->name, avalon->device_id, err);
  518. }
  519. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  520. {
  521. uint8_t buf[2];
  522. int err;
  523. if (usb_ident(avalon) == IDENT_BTB) {
  524. buf[0] = (uint8_t)core_voltage;
  525. buf[1] = (uint8_t)(core_voltage >> 8);
  526. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  527. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  528. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  529. if (unlikely(err < 0)) {
  530. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  531. avalon->drv->name, avalon->device_id, err);
  532. return false;
  533. } else {
  534. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  535. avalon->drv->name, avalon->device_id,
  536. core_voltage);
  537. }
  538. return true;
  539. }
  540. return false;
  541. }
  542. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  543. {
  544. uint8_t buf[2];
  545. int err;
  546. int amount;
  547. if (usb_ident(avalon) == IDENT_BTB) {
  548. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  549. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  550. (char *)buf, sizeof(buf), &amount,
  551. C_BB_GET_VOLTAGE);
  552. if (unlikely(err != 0 || amount != 2)) {
  553. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  554. avalon->drv->name, avalon->device_id, err, amount);
  555. return 0;
  556. } else {
  557. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  558. }
  559. } else {
  560. return 0;
  561. }
  562. }
  563. static void bitburner_get_version(struct cgpu_info *avalon)
  564. {
  565. struct avalon_info *info = avalon->device_data;
  566. uint8_t buf[3];
  567. int err;
  568. int amount;
  569. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  570. BITBURNER_VALUE, BITBURNER_INDEX_GET_VERSION,
  571. (char *)buf, sizeof(buf), &amount,
  572. C_GETVERSION);
  573. if (unlikely(err != 0 || amount != sizeof(buf))) {
  574. applog(LOG_DEBUG, "%s%i: GetVersion failed: err=%d, amt=%d assuming %d.%d.%d",
  575. avalon->drv->name, avalon->device_id, err, amount,
  576. BITBURNER_VERSION1, BITBURNER_VERSION2, BITBURNER_VERSION3);
  577. info->version1 = BITBURNER_VERSION1;
  578. info->version2 = BITBURNER_VERSION2;
  579. info->version3 = BITBURNER_VERSION3;
  580. } else {
  581. info->version1 = buf[0];
  582. info->version2 = buf[1];
  583. info->version3 = buf[2];
  584. }
  585. }
  586. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  587. {
  588. int baud, miner_count, asic_count, timeout, frequency;
  589. int this_option_offset = ++option_offset;
  590. struct avalon_info *info;
  591. struct cgpu_info *avalon;
  592. bool configured;
  593. int ret;
  594. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  595. baud = AVALON_IO_SPEED;
  596. miner_count = AVALON_DEFAULT_MINER_NUM;
  597. asic_count = AVALON_DEFAULT_ASIC_NUM;
  598. timeout = AVALON_DEFAULT_TIMEOUT;
  599. frequency = AVALON_DEFAULT_FREQUENCY;
  600. configured = get_options(this_option_offset, &baud, &miner_count,
  601. &asic_count, &timeout, &frequency);
  602. if (!usb_init(avalon, dev, found))
  603. goto shin;
  604. /* Even though this is an FTDI type chip, we want to do the parsing
  605. * all ourselves so set it to std usb type */
  606. avalon->usbdev->usb_type = USB_TYPE_STD;
  607. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  608. /* We have a real Avalon! */
  609. avalon_initialise(avalon);
  610. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  611. if (unlikely(!(avalon->device_data)))
  612. quit(1, "Failed to calloc avalon_info data");
  613. info = avalon->device_data;
  614. if (configured) {
  615. info->baud = baud;
  616. info->miner_count = miner_count;
  617. info->asic_count = asic_count;
  618. info->timeout = timeout;
  619. info->frequency = frequency;
  620. } else {
  621. info->baud = AVALON_IO_SPEED;
  622. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  623. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  624. info->timeout = AVALON_DEFAULT_TIMEOUT;
  625. info->frequency = AVALON_DEFAULT_FREQUENCY;
  626. }
  627. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  628. info->temp_max = 0;
  629. /* This is for check the temp/fan every 3~4s */
  630. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  631. if (info->temp_history_count <= 0)
  632. info->temp_history_count = 1;
  633. info->temp_history_index = 0;
  634. info->temp_sum = 0;
  635. info->temp_old = 0;
  636. if (!add_cgpu(avalon))
  637. goto unshin;
  638. ret = avalon_reset(avalon, true);
  639. if (ret && !configured)
  640. goto unshin;
  641. update_usb_stats(avalon);
  642. avalon_idle(avalon, info);
  643. applog(LOG_DEBUG, "Avalon Detected: %s "
  644. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  645. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  646. info->frequency);
  647. if (usb_ident(avalon) == IDENT_BTB) {
  648. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  649. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  650. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  651. opt_bitburner_core_voltage,
  652. BITBURNER_MIN_COREMV,
  653. BITBURNER_MAX_COREMV);
  654. } else
  655. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  656. bitburner_get_version(avalon);
  657. }
  658. return true;
  659. unshin:
  660. usb_uninit(avalon);
  661. shin:
  662. free(avalon->device_data);
  663. avalon->device_data = NULL;
  664. avalon = usb_free_cgpu(avalon);
  665. return false;
  666. }
  667. static void avalon_detect(void)
  668. {
  669. usb_detect(&avalon_drv, avalon_detect_one);
  670. }
  671. static void avalon_init(struct cgpu_info *avalon)
  672. {
  673. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  674. }
  675. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  676. {
  677. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  678. (char *)ar->data, 64, 12);
  679. }
  680. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  681. struct avalon_result *ar);
  682. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  683. {
  684. applog(LOG_INFO, "%s%d: No matching work - HW error",
  685. thr->cgpu->drv->name, thr->cgpu->device_id);
  686. inc_hw_errors(thr);
  687. info->no_matching_work++;
  688. }
  689. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  690. struct thr_info *thr, char *buf, int *offset)
  691. {
  692. int i, spare = *offset - AVALON_READ_SIZE;
  693. bool found = false;
  694. for (i = 0; i <= spare; i++) {
  695. struct avalon_result *ar;
  696. struct work *work;
  697. ar = (struct avalon_result *)&buf[i];
  698. work = avalon_valid_result(avalon, ar);
  699. if (work) {
  700. bool gettemp = false;
  701. found = true;
  702. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  703. mutex_lock(&info->lock);
  704. if (!info->nonces++)
  705. gettemp = true;
  706. info->auto_nonces++;
  707. mutex_unlock(&info->lock);
  708. } else if (opt_avalon_auto) {
  709. mutex_lock(&info->lock);
  710. info->auto_hw++;
  711. mutex_unlock(&info->lock);
  712. }
  713. free_work(work);
  714. if (gettemp)
  715. avalon_update_temps(avalon, info, ar);
  716. break;
  717. }
  718. }
  719. if (!found) {
  720. spare = *offset - AVALON_READ_SIZE;
  721. /* We are buffering and haven't accumulated one more corrupt
  722. * work result. */
  723. if (spare < (int)AVALON_READ_SIZE)
  724. return;
  725. avalon_inc_nvw(info, thr);
  726. } else {
  727. spare = AVALON_READ_SIZE + i;
  728. if (i) {
  729. if (i >= (int)AVALON_READ_SIZE)
  730. avalon_inc_nvw(info, thr);
  731. else
  732. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  733. }
  734. }
  735. *offset -= spare;
  736. memmove(buf, buf + spare, *offset);
  737. }
  738. static void avalon_running_reset(struct cgpu_info *avalon,
  739. struct avalon_info *info)
  740. {
  741. avalon_reset(avalon, false);
  742. avalon_idle(avalon, info);
  743. avalon->results = 0;
  744. info->reset = false;
  745. }
  746. static void *avalon_get_results(void *userdata)
  747. {
  748. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  749. struct avalon_info *info = avalon->device_data;
  750. const int rsize = AVALON_FTDI_READSIZE;
  751. char readbuf[AVALON_READBUF_SIZE];
  752. struct thr_info *thr = info->thr;
  753. cgtimer_t ts_start;
  754. int offset = 0, ret = 0;
  755. char threadname[24];
  756. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  757. RenameThread(threadname);
  758. cgsleep_prepare_r(&ts_start);
  759. while (likely(!avalon->shutdown)) {
  760. unsigned char buf[rsize];
  761. if (offset >= (int)AVALON_READ_SIZE)
  762. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  763. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  764. /* This should never happen */
  765. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  766. offset = 0;
  767. }
  768. if (unlikely(info->reset)) {
  769. avalon_running_reset(avalon, info);
  770. /* Discard anything in the buffer */
  771. offset = 0;
  772. }
  773. /* As the usb read returns after just 1ms, sleep long enough
  774. * to leave the interface idle for writes to occur, but do not
  775. * sleep if we have been receiving data, and we do not yet have
  776. * a full result as more may be coming. */
  777. if (ret < 1 || offset == 0)
  778. cgsleep_ms_r(&ts_start, AVALON_READ_TIMEOUT);
  779. cgsleep_prepare_r(&ts_start);
  780. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  781. C_AVALON_READ);
  782. if (ret < 1)
  783. continue;
  784. if (opt_debug) {
  785. applog(LOG_DEBUG, "Avalon: get:");
  786. hexdump((uint8_t *)buf, ret);
  787. }
  788. memcpy(&readbuf[offset], &buf, ret);
  789. offset += ret;
  790. }
  791. return NULL;
  792. }
  793. static void avalon_rotate_array(struct cgpu_info *avalon)
  794. {
  795. avalon->queued = 0;
  796. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  797. avalon->work_array = 0;
  798. }
  799. static void bitburner_rotate_array(struct cgpu_info *avalon)
  800. {
  801. avalon->queued = 0;
  802. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  803. avalon->work_array = 0;
  804. }
  805. static void avalon_set_timeout(struct avalon_info *info)
  806. {
  807. info->timeout = avalon_calc_timeout(info->frequency);
  808. }
  809. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  810. {
  811. struct avalon_info *info = avalon->device_data;
  812. info->frequency = frequency;
  813. if (info->frequency > opt_avalon_freq_max)
  814. info->frequency = opt_avalon_freq_max;
  815. if (info->frequency < opt_avalon_freq_min)
  816. info->frequency = opt_avalon_freq_min;
  817. avalon_set_timeout(info);
  818. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  819. avalon->drv->name, avalon->device_id,
  820. info->frequency, info->timeout);
  821. }
  822. static void avalon_inc_freq(struct avalon_info *info)
  823. {
  824. info->frequency += 2;
  825. if (info->frequency > opt_avalon_freq_max)
  826. info->frequency = opt_avalon_freq_max;
  827. avalon_set_timeout(info);
  828. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  829. info->frequency, info->timeout);
  830. }
  831. static void avalon_dec_freq(struct avalon_info *info)
  832. {
  833. info->frequency -= 1;
  834. if (info->frequency < opt_avalon_freq_min)
  835. info->frequency = opt_avalon_freq_min;
  836. avalon_set_timeout(info);
  837. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  838. info->frequency, info->timeout);
  839. }
  840. static void avalon_reset_auto(struct avalon_info *info)
  841. {
  842. info->auto_queued =
  843. info->auto_nonces =
  844. info->auto_hw = 0;
  845. }
  846. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  847. {
  848. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  849. mutex_lock(&info->lock);
  850. if (!info->optimal) {
  851. if (info->fan_pwm >= opt_avalon_fan_max) {
  852. applog(LOG_WARNING,
  853. "%s%i: Above optimal temperature, throttling",
  854. avalon->drv->name, avalon->device_id);
  855. avalon_dec_freq(info);
  856. }
  857. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  858. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  859. int total = info->auto_nonces + info->auto_hw;
  860. /* Try to keep hw errors < 2% */
  861. if (info->auto_hw * 100 < total)
  862. avalon_inc_freq(info);
  863. else if (info->auto_hw * 66 > total)
  864. avalon_dec_freq(info);
  865. }
  866. avalon_reset_auto(info);
  867. mutex_unlock(&info->lock);
  868. }
  869. }
  870. static void *avalon_send_tasks(void *userdata)
  871. {
  872. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  873. struct avalon_info *info = avalon->device_data;
  874. const int avalon_get_work_count = info->miner_count;
  875. char threadname[24];
  876. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  877. RenameThread(threadname);
  878. while (likely(!avalon->shutdown)) {
  879. int start_count, end_count, i, j, ret;
  880. cgtimer_t ts_start;
  881. struct avalon_task at;
  882. bool idled = false;
  883. int64_t us_timeout;
  884. while (avalon_buffer_full(avalon))
  885. cgsleep_ms(40);
  886. avalon_adjust_freq(info, avalon);
  887. /* A full nonce range */
  888. us_timeout = 0x100000000ll / info->asic_count / info->frequency;
  889. cgsleep_prepare_r(&ts_start);
  890. mutex_lock(&info->qlock);
  891. start_count = avalon->work_array * avalon_get_work_count;
  892. end_count = start_count + avalon_get_work_count;
  893. for (i = start_count, j = 0; i < end_count; i++, j++) {
  894. if (avalon_buffer_full(avalon)) {
  895. applog(LOG_INFO,
  896. "%s%i: Buffer full after only %d of %d work queued",
  897. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  898. break;
  899. }
  900. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  901. avalon_init_task(&at, 0, 0, info->fan_pwm,
  902. info->timeout, info->asic_count,
  903. info->miner_count, 1, 0, info->frequency);
  904. avalon_create_task(&at, avalon->works[i]);
  905. info->auto_queued++;
  906. } else {
  907. int idle_freq = info->frequency;
  908. if (!info->idle++)
  909. idled = true;
  910. if (unlikely(info->overheat && opt_avalon_auto))
  911. idle_freq = AVALON_MIN_FREQUENCY;
  912. avalon_init_task(&at, 0, 0, info->fan_pwm,
  913. info->timeout, info->asic_count,
  914. info->miner_count, 1, 1, idle_freq);
  915. /* Reset the auto_queued count if we end up
  916. * idling any miners. */
  917. avalon_reset_auto(info);
  918. }
  919. ret = avalon_send_task(&at, avalon);
  920. if (unlikely(ret == AVA_SEND_ERROR)) {
  921. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  922. avalon->drv->name, avalon->device_id);
  923. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  924. info->reset = true;
  925. break;
  926. }
  927. }
  928. avalon_rotate_array(avalon);
  929. pthread_cond_signal(&info->qcond);
  930. mutex_unlock(&info->qlock);
  931. if (unlikely(idled)) {
  932. applog(LOG_WARNING, "%s%i: Idled %d miners",
  933. avalon->drv->name, avalon->device_id, idled);
  934. }
  935. /* Sleep how long it would take to complete a full nonce range
  936. * at the current frequency using the clock_nanosleep function
  937. * timed from before we started loading new work so it will
  938. * fall short of the full duration. */
  939. cgsleep_us_r(&ts_start, us_timeout);
  940. }
  941. return NULL;
  942. }
  943. static void *bitburner_send_tasks(void *userdata)
  944. {
  945. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  946. struct avalon_info *info = avalon->device_data;
  947. const int avalon_get_work_count = info->miner_count;
  948. char threadname[24];
  949. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  950. RenameThread(threadname);
  951. while (likely(!avalon->shutdown)) {
  952. int start_count, end_count, i, j, ret;
  953. struct avalon_task at;
  954. bool idled = false;
  955. while (avalon_buffer_full(avalon))
  956. cgsleep_ms(40);
  957. avalon_adjust_freq(info, avalon);
  958. /* Give other threads a chance to acquire qlock. */
  959. i = 0;
  960. do {
  961. cgsleep_ms(40);
  962. } while (!avalon->shutdown && i++ < 15
  963. && avalon->queued < avalon_get_work_count);
  964. mutex_lock(&info->qlock);
  965. start_count = avalon->work_array * avalon_get_work_count;
  966. end_count = start_count + avalon_get_work_count;
  967. for (i = start_count, j = 0; i < end_count; i++, j++) {
  968. while (avalon_buffer_full(avalon))
  969. cgsleep_ms(40);
  970. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  971. avalon_init_task(&at, 0, 0, info->fan_pwm,
  972. info->timeout, info->asic_count,
  973. info->miner_count, 1, 0, info->frequency);
  974. avalon_create_task(&at, avalon->works[i]);
  975. info->auto_queued++;
  976. } else {
  977. int idle_freq = info->frequency;
  978. if (!info->idle++)
  979. idled = true;
  980. if (unlikely(info->overheat && opt_avalon_auto))
  981. idle_freq = AVALON_MIN_FREQUENCY;
  982. avalon_init_task(&at, 0, 0, info->fan_pwm,
  983. info->timeout, info->asic_count,
  984. info->miner_count, 1, 1, idle_freq);
  985. /* Reset the auto_queued count if we end up
  986. * idling any miners. */
  987. avalon_reset_auto(info);
  988. }
  989. ret = avalon_send_task(&at, avalon);
  990. if (unlikely(ret == AVA_SEND_ERROR)) {
  991. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  992. avalon->drv->name, avalon->device_id);
  993. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  994. info->reset = true;
  995. break;
  996. }
  997. }
  998. bitburner_rotate_array(avalon);
  999. pthread_cond_signal(&info->qcond);
  1000. mutex_unlock(&info->qlock);
  1001. if (unlikely(idled)) {
  1002. applog(LOG_WARNING, "%s%i: Idled %d miners",
  1003. avalon->drv->name, avalon->device_id, idled);
  1004. }
  1005. }
  1006. return NULL;
  1007. }
  1008. static bool avalon_prepare(struct thr_info *thr)
  1009. {
  1010. struct cgpu_info *avalon = thr->cgpu;
  1011. struct avalon_info *info = avalon->device_data;
  1012. int array_size = AVALON_ARRAY_SIZE;
  1013. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  1014. if (usb_ident(avalon) == IDENT_BTB) {
  1015. array_size = BITBURNER_ARRAY_SIZE;
  1016. write_thread_fn = bitburner_send_tasks;
  1017. }
  1018. free(avalon->works);
  1019. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  1020. array_size);
  1021. if (!avalon->works)
  1022. quit(1, "Failed to calloc avalon works in avalon_prepare");
  1023. info->thr = thr;
  1024. mutex_init(&info->lock);
  1025. mutex_init(&info->qlock);
  1026. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1027. quit(1, "Failed to pthread_cond_init avalon qcond");
  1028. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  1029. quit(1, "Failed to create avalon read_thr");
  1030. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  1031. quit(1, "Failed to create avalon write_thr");
  1032. avalon_init(avalon);
  1033. return true;
  1034. }
  1035. static void do_avalon_close(struct thr_info *thr)
  1036. {
  1037. struct cgpu_info *avalon = thr->cgpu;
  1038. struct avalon_info *info = avalon->device_data;
  1039. pthread_join(info->read_thr, NULL);
  1040. pthread_join(info->write_thr, NULL);
  1041. avalon_running_reset(avalon, info);
  1042. info->no_matching_work = 0;
  1043. }
  1044. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  1045. {
  1046. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1047. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1048. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1049. info->temp0 = ar->temp0;
  1050. info->temp1 = ar->temp1;
  1051. info->temp2 = ar->temp2;
  1052. if (ar->temp0 & 0x80) {
  1053. ar->temp0 &= 0x7f;
  1054. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1055. }
  1056. if (ar->temp1 & 0x80) {
  1057. ar->temp1 &= 0x7f;
  1058. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1059. }
  1060. if (ar->temp2 & 0x80) {
  1061. ar->temp2 &= 0x7f;
  1062. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1063. }
  1064. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  1065. if (info->temp0 > info->temp_max)
  1066. info->temp_max = info->temp0;
  1067. if (info->temp1 > info->temp_max)
  1068. info->temp_max = info->temp1;
  1069. if (info->temp2 > info->temp_max)
  1070. info->temp_max = info->temp2;
  1071. }
  1072. static void temp_rise(struct avalon_info *info, int temp)
  1073. {
  1074. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1075. info->fan_pwm = AVALON_PWM_MAX;
  1076. return;
  1077. }
  1078. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1079. info->fan_pwm += 10;
  1080. else if (temp > opt_avalon_temp)
  1081. info->fan_pwm += 5;
  1082. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1083. info->fan_pwm += 1;
  1084. else
  1085. return;
  1086. if (info->fan_pwm > opt_avalon_fan_max)
  1087. info->fan_pwm = opt_avalon_fan_max;
  1088. }
  1089. static void temp_drop(struct avalon_info *info, int temp)
  1090. {
  1091. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1092. info->fan_pwm = opt_avalon_fan_min;
  1093. return;
  1094. }
  1095. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1096. info->fan_pwm -= 10;
  1097. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1098. info->fan_pwm -= 5;
  1099. else if (temp < opt_avalon_temp)
  1100. info->fan_pwm -= 1;
  1101. if (info->fan_pwm < opt_avalon_fan_min)
  1102. info->fan_pwm = opt_avalon_fan_min;
  1103. }
  1104. static inline void adjust_fan(struct avalon_info *info)
  1105. {
  1106. int temp_new;
  1107. temp_new = info->temp_sum / info->temp_history_count;
  1108. if (temp_new > info->temp_old)
  1109. temp_rise(info, temp_new);
  1110. else if (temp_new < info->temp_old)
  1111. temp_drop(info, temp_new);
  1112. else {
  1113. /* temp_new == info->temp_old */
  1114. if (temp_new > opt_avalon_temp)
  1115. temp_rise(info, temp_new);
  1116. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1117. temp_drop(info, temp_new);
  1118. }
  1119. info->temp_old = temp_new;
  1120. if (info->temp_old <= opt_avalon_temp)
  1121. info->optimal = true;
  1122. else
  1123. info->optimal = false;
  1124. }
  1125. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1126. struct avalon_result *ar)
  1127. {
  1128. record_temp_fan(info, ar, &(avalon->temp));
  1129. applog(LOG_INFO,
  1130. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1131. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1132. info->fan0, info->fan1, info->fan2,
  1133. info->temp0, info->temp1, info->temp2, info->temp_max);
  1134. info->temp_history_index++;
  1135. info->temp_sum += avalon->temp;
  1136. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1137. info->temp_history_index, info->temp_history_count, info->temp_old);
  1138. if (usb_ident(avalon) == IDENT_BTB) {
  1139. info->core_voltage = bitburner_get_core_voltage(avalon);
  1140. }
  1141. if (info->temp_history_index == info->temp_history_count) {
  1142. adjust_fan(info);
  1143. info->temp_history_index = 0;
  1144. info->temp_sum = 0;
  1145. }
  1146. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1147. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1148. info->overheat = true;
  1149. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1150. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1151. info->overheat = false;
  1152. }
  1153. }
  1154. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1155. {
  1156. struct avalon_info *info = avalon->device_data;
  1157. int lowfan = 10000;
  1158. if (usb_ident(avalon) == IDENT_BTB) {
  1159. int temp = info->temp0;
  1160. if (info->temp2 > temp)
  1161. temp = info->temp2;
  1162. if (temp > 99)
  1163. temp = 99;
  1164. if (temp < 0)
  1165. temp = 0;
  1166. tailsprintf(buf, bufsiz, "%2dC %3d %4dmV | ", temp, info->frequency, info->core_voltage);
  1167. } else {
  1168. /* Find the lowest fan speed of the ASIC cooling fans. */
  1169. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1170. lowfan = info->fan1;
  1171. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1172. lowfan = info->fan2;
  1173. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1174. }
  1175. }
  1176. /* We use a replacement algorithm to only remove references to work done from
  1177. * the buffer when we need the extra space for new work. */
  1178. static bool avalon_fill(struct cgpu_info *avalon)
  1179. {
  1180. struct avalon_info *info = avalon->device_data;
  1181. int subid, slot, mc;
  1182. struct work *work;
  1183. bool ret = true;
  1184. mc = info->miner_count;
  1185. mutex_lock(&info->qlock);
  1186. if (avalon->queued >= mc)
  1187. goto out_unlock;
  1188. work = get_queued(avalon);
  1189. if (unlikely(!work)) {
  1190. ret = false;
  1191. goto out_unlock;
  1192. }
  1193. subid = avalon->queued++;
  1194. work->subid = subid;
  1195. slot = avalon->work_array * mc + subid;
  1196. if (likely(avalon->works[slot]))
  1197. work_completed(avalon, avalon->works[slot]);
  1198. avalon->works[slot] = work;
  1199. if (avalon->queued < mc)
  1200. ret = false;
  1201. out_unlock:
  1202. mutex_unlock(&info->qlock);
  1203. return ret;
  1204. }
  1205. static int64_t avalon_scanhash(struct thr_info *thr)
  1206. {
  1207. struct cgpu_info *avalon = thr->cgpu;
  1208. struct avalon_info *info = avalon->device_data;
  1209. const int miner_count = info->miner_count;
  1210. struct timeval now, then, tdiff;
  1211. int64_t hash_count, us_timeout;
  1212. struct timespec abstime;
  1213. /* Half nonce range */
  1214. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1215. us_to_timeval(&tdiff, us_timeout);
  1216. cgtime(&now);
  1217. timeradd(&now, &tdiff, &then);
  1218. timeval_to_spec(&abstime, &then);
  1219. /* Wait until avalon_send_tasks signals us that it has completed
  1220. * sending its work or a full nonce range timeout has occurred */
  1221. mutex_lock(&info->qlock);
  1222. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1223. mutex_unlock(&info->qlock);
  1224. mutex_lock(&info->lock);
  1225. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1226. avalon->results += info->nonces + info->idle;
  1227. if (avalon->results > miner_count)
  1228. avalon->results = miner_count;
  1229. if (!info->reset)
  1230. avalon->results--;
  1231. info->nonces = info->idle = 0;
  1232. mutex_unlock(&info->lock);
  1233. /* Check for nothing but consecutive bad results or consistently less
  1234. * results than we should be getting and reset the FPGA if necessary */
  1235. if (usb_ident(avalon) != IDENT_BTB) {
  1236. if (avalon->results < -miner_count && !info->reset) {
  1237. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1238. avalon->drv->name, avalon->device_id);
  1239. info->reset = true;
  1240. }
  1241. }
  1242. if (unlikely(avalon->usbinfo.nodev)) {
  1243. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1244. avalon->drv->name, avalon->device_id);
  1245. avalon->shutdown = true;
  1246. }
  1247. /* This hashmeter is just a utility counter based on returned shares */
  1248. return hash_count;
  1249. }
  1250. static void avalon_flush_work(struct cgpu_info *avalon)
  1251. {
  1252. struct avalon_info *info = avalon->device_data;
  1253. mutex_lock(&info->qlock);
  1254. /* Will overwrite any work queued */
  1255. avalon->queued = 0;
  1256. pthread_cond_signal(&info->qcond);
  1257. mutex_unlock(&info->qlock);
  1258. }
  1259. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1260. {
  1261. struct api_data *root = NULL;
  1262. struct avalon_info *info = cgpu->device_data;
  1263. char buf[64];
  1264. int i;
  1265. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1266. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1267. root = api_add_int(root, "baud", &(info->baud), false);
  1268. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1269. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1270. root = api_add_int(root, "timeout", &(info->timeout), false);
  1271. root = api_add_int(root, "frequency", &(info->frequency), false);
  1272. root = api_add_int(root, "fan1", &(info->fan0), false);
  1273. root = api_add_int(root, "fan2", &(info->fan1), false);
  1274. root = api_add_int(root, "fan3", &(info->fan2), false);
  1275. root = api_add_int(root, "temp1", &(info->temp0), false);
  1276. root = api_add_int(root, "temp2", &(info->temp1), false);
  1277. root = api_add_int(root, "temp3", &(info->temp2), false);
  1278. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1279. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1280. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1281. for (i = 0; i < info->miner_count; i++) {
  1282. char mcw[24];
  1283. sprintf(mcw, "match_work_count%d", i + 1);
  1284. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1285. }
  1286. if (usb_ident(cgpu) == IDENT_BTB) {
  1287. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1288. snprintf(buf, sizeof(buf), "%"PRIu8".%"PRIu8".%"PRIu8,
  1289. info->version1, info->version2, info->version3);
  1290. root = api_add_string(root, "version", buf, true);
  1291. }
  1292. root = api_add_int(root, "Controller Version", &(info->ctlr_ver), false);
  1293. return root;
  1294. }
  1295. static void avalon_shutdown(struct thr_info *thr)
  1296. {
  1297. do_avalon_close(thr);
  1298. }
  1299. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1300. {
  1301. int val;
  1302. if (strcasecmp(option, "help") == 0) {
  1303. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1304. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1305. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1306. return replybuf;
  1307. }
  1308. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1309. if (usb_ident(avalon) != IDENT_BTB) {
  1310. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1311. return replybuf;
  1312. }
  1313. if (!setting || !*setting) {
  1314. sprintf(replybuf, "missing millivolts setting");
  1315. return replybuf;
  1316. }
  1317. val = atoi(setting);
  1318. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1319. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1320. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1321. return replybuf;
  1322. }
  1323. if (bitburner_set_core_voltage(avalon, val))
  1324. return NULL;
  1325. else {
  1326. sprintf(replybuf, "Set millivolts failed");
  1327. return replybuf;
  1328. }
  1329. }
  1330. if (strcasecmp(option, "freq") == 0) {
  1331. if (!setting || !*setting) {
  1332. sprintf(replybuf, "missing freq setting");
  1333. return replybuf;
  1334. }
  1335. val = atoi(setting);
  1336. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1337. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1338. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1339. return replybuf;
  1340. }
  1341. avalon_set_freq(avalon, val);
  1342. return NULL;
  1343. }
  1344. sprintf(replybuf, "Unknown option: %s", option);
  1345. return replybuf;
  1346. }
  1347. struct device_drv avalon_drv = {
  1348. .drv_id = DRIVER_AVALON,
  1349. .dname = "avalon",
  1350. .name = "AVA",
  1351. .drv_detect = avalon_detect,
  1352. .thread_prepare = avalon_prepare,
  1353. .hash_work = hash_queued_work,
  1354. .queue_full = avalon_fill,
  1355. .scanwork = avalon_scanhash,
  1356. .flush_work = avalon_flush_work,
  1357. .get_api_stats = avalon_api_stats,
  1358. .get_statline_before = get_avalon_statline_before,
  1359. .set_device = avalon_set_device,
  1360. .reinit_device = avalon_init,
  1361. .thread_shutdown = avalon_shutdown,
  1362. };