driver-bitmain.c 72 KB

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  1. /*
  2. * Copyright 2012-2014 Lingchao Xu
  3. * Copyright 2015 Luke Dashjr
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <math.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <sys/select.h>
  21. #include <termios.h>
  22. #include <sys/stat.h>
  23. #include <fcntl.h>
  24. #ifndef O_CLOEXEC
  25. #define O_CLOEXEC 0
  26. #endif
  27. #else
  28. #include "compat.h"
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include <curl/curl.h>
  33. #include <uthash.h>
  34. #include "deviceapi.h"
  35. #include "miner.h"
  36. #include "driver-bitmain.h"
  37. #include "lowl-vcom.h"
  38. #include "util.h"
  39. const bool opt_bitmain_hwerror = true;
  40. BFG_REGISTER_DRIVER(bitmain_drv)
  41. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[];
  42. static inline unsigned int bfg_work_block(struct work * const work)
  43. {
  44. return *((unsigned int*)(&work->data[4]));
  45. }
  46. #define htole8(x) (x)
  47. #define BITMAIN_USING_CURL -2
  48. static
  49. struct cgpu_info *btm_alloc_cgpu(struct device_drv *drv, int threads)
  50. {
  51. struct cgpu_info *cgpu = calloc(1, sizeof(*cgpu));
  52. if (unlikely(!cgpu))
  53. quit(1, "Failed to calloc cgpu for %s in usb_alloc_cgpu", drv->dname);
  54. cgpu->drv = drv;
  55. cgpu->deven = DEV_ENABLED;
  56. cgpu->threads = threads;
  57. cgpu->device_fd = -1;
  58. struct bitmain_info *info = malloc(sizeof(*info));
  59. if (unlikely(!info))
  60. quit(1, "Failed to calloc bitmain_info data");
  61. cgpu->device_data = info;
  62. *info = (struct bitmain_info){
  63. .baud = BITMAIN_IO_SPEED,
  64. .chain_num = BITMAIN_DEFAULT_CHAIN_NUM,
  65. .asic_num = BITMAIN_DEFAULT_ASIC_NUM,
  66. .timeout = BITMAIN_DEFAULT_TIMEOUT,
  67. .frequency = BITMAIN_DEFAULT_FREQUENCY,
  68. .voltage[0] = BITMAIN_DEFAULT_VOLTAGE0,
  69. .voltage[1] = BITMAIN_DEFAULT_VOLTAGE1,
  70. };
  71. sprintf(info->frequency_t, "%d", BITMAIN_DEFAULT_FREQUENCY),
  72. strcpy(info->voltage_t, BITMAIN_DEFAULT_VOLTAGE_T);
  73. return cgpu;
  74. }
  75. static
  76. bool btm_init(struct cgpu_info *cgpu, const char * devpath)
  77. {
  78. applog(LOG_DEBUG, "btm_init cgpu->device_fd=%d", cgpu->device_fd);
  79. int fd = -1;
  80. if(cgpu->device_fd >= 0) {
  81. return false;
  82. }
  83. struct bitmain_info *info = cgpu->device_data;
  84. if (!strncmp(devpath, "ip:", 3)) {
  85. CURL *curl = curl_easy_init();
  86. if (!curl)
  87. applogr(false, LOG_ERR, "%s: curl_easy_init failed", cgpu->drv->dname);
  88. curl_easy_setopt(curl, CURLOPT_FRESH_CONNECT, 1);
  89. curl_easy_setopt(curl, CURLOPT_CONNECTTIMEOUT, 5);
  90. curl_easy_setopt(curl, CURLOPT_NOSIGNAL, 1);
  91. curl_easy_setopt(curl, CURLOPT_TCP_NODELAY, 1);
  92. curl_easy_setopt(curl, CURLOPT_CONNECT_ONLY, 1);
  93. curl_easy_setopt(curl, CURLOPT_URL, &devpath[3]);
  94. if (curl_easy_perform(curl)) {
  95. curl_easy_cleanup(curl);
  96. applogr(false, LOG_ERR, "%s: curl_easy_perform failed for %s", cgpu->drv->dname, &devpath[3]);
  97. }
  98. cgpu->device_path = strdup(devpath);
  99. cgpu->device_fd = BITMAIN_USING_CURL;
  100. info->device_curl = curl;
  101. return true;
  102. }
  103. fd = serial_open(devpath, info->baud, 1, true);
  104. if(fd == -1) {
  105. applog(LOG_DEBUG, "%s open %s error %d",
  106. cgpu->drv->dname, devpath, errno);
  107. return false;
  108. }
  109. cgpu->device_path = strdup(devpath);
  110. cgpu->device_fd = fd;
  111. applog(LOG_DEBUG, "btm_init open device fd = %d", cgpu->device_fd);
  112. return true;
  113. }
  114. static
  115. void btm_uninit(struct cgpu_info *cgpu)
  116. {
  117. struct bitmain_info * const info = cgpu->device_data;
  118. applog(LOG_DEBUG, "BTM uninit %s%i", cgpu->drv->name, cgpu->device_fd);
  119. // May have happened already during a failed initialisation
  120. // if release_cgpu() was called due to a USB NODEV(err)
  121. if (cgpu->device_fd >= 0) {
  122. serial_close(cgpu->device_fd);
  123. cgpu->device_fd = -1;
  124. }
  125. if (info->device_curl) {
  126. curl_easy_cleanup(info->device_curl);
  127. info->device_curl = NULL;
  128. }
  129. if(cgpu->device_path) {
  130. free((char*)cgpu->device_path);
  131. cgpu->device_path = NULL;
  132. }
  133. }
  134. bool bitmain_curl_all(void *func_p, CURL * const curl, void *p, size_t remsz)
  135. {
  136. CURLcode (*func)(CURL *, void *, size_t, size_t *) = func_p;
  137. CURLcode r;
  138. size_t sz;
  139. while (remsz) {
  140. r = func(curl, p, remsz, &sz);
  141. switch (r) {
  142. case CURLE_OK:
  143. remsz -= sz;
  144. p += sz;
  145. break;
  146. case CURLE_AGAIN:
  147. break;
  148. default:
  149. return false;
  150. }
  151. }
  152. return true;
  153. }
  154. static
  155. int btm_read(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  156. {
  157. int err = 0;
  158. //applog(LOG_DEBUG, "btm_read ----- %d -----", bufsize);
  159. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  160. struct bitmain_info * const info = cgpu->device_data;
  161. uint8_t headbuf[5];
  162. headbuf[0] = 0;
  163. pk_u32be(headbuf, 1, bufsize);
  164. if (!bitmain_curl_all(curl_easy_send, info->device_curl, headbuf, sizeof(headbuf)))
  165. return -1;
  166. if (!bitmain_curl_all(curl_easy_recv, info->device_curl, headbuf, 4))
  167. return -1;
  168. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  169. return -1;
  170. size_t sz = upk_u32be(headbuf, 0);
  171. if (!bitmain_curl_all(curl_easy_recv, info->device_curl, buf, sz))
  172. return -1;
  173. return sz;
  174. }
  175. err = read(cgpu->device_fd, buf, bufsize);
  176. return err;
  177. }
  178. static
  179. int btm_write(struct cgpu_info * const cgpu, void * const buf, const size_t bufsize)
  180. {
  181. int err = 0;
  182. //applog(LOG_DEBUG, "btm_write ----- %d -----", bufsize);
  183. if (unlikely(cgpu->device_fd == BITMAIN_USING_CURL)) {
  184. struct bitmain_info * const info = cgpu->device_data;
  185. uint8_t headbuf[5];
  186. headbuf[0] = 1;
  187. pk_u32be(headbuf, 1, bufsize);
  188. if (!bitmain_curl_all(curl_easy_send, info->device_curl, headbuf, sizeof(headbuf)))
  189. return -1;
  190. if (!bitmain_curl_all(curl_easy_send, info->device_curl, buf, bufsize))
  191. return -1;
  192. if (!bitmain_curl_all(curl_easy_recv, info->device_curl, headbuf, 4))
  193. return -1;
  194. if (headbuf[0] == 0xff && headbuf[1] == 0xff && headbuf[2] == 0xff && headbuf[3] == 0xff)
  195. return -1;
  196. return upk_u32be(headbuf, 0);
  197. }
  198. err = write(cgpu->device_fd, buf, bufsize);
  199. return err;
  200. }
  201. #define BITMAIN_CALC_DIFF1 1
  202. #ifdef WIN32
  203. #define BITMAIN_TEST
  204. #endif
  205. #define BITMAIN_TEST_PRINT_WORK 0
  206. #ifdef BITMAIN_TEST
  207. #define BITMAIN_TEST_NUM 19
  208. #define BITMAIN_TEST_USENUM 1
  209. int g_test_index = 0;
  210. const char btm_work_test_data[BITMAIN_TEST_NUM][256] = {
  211. "00000002ddc1ce5579dbec17f17fbb8f31ae218a814b2a0c1900f0d90000000100000000b58aa6ca86546b07a5a46698f736c7ca9c0eedc756d8f28ac33c20cc24d792675276f879190afc85b6888022000000800000000000000000000000000000000000000000000000000000000000000000",
  212. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000eb2d45233c5b02de50ddcb9049ba16040e0ba00e9750a474eec75891571d925b52dfda4a190266667145b02f000000800000000000000000000000000000000000000000000000000000000000000000",
  213. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000090c7d3743e0b0562e4f56d3dd35cece3c5e8275d0abb21bf7e503cb72bd7ed3b52dfda4a190266667bbb58d7000000800000000000000000000000000000000000000000000000000000000000000000",
  214. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000006e0561da06022bfbb42c5ecd74a46bfd91934f201b777e9155cc6c3674724ec652dfda4a19026666a0cd827b000000800000000000000000000000000000000000000000000000000000000000000000",
  215. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000000312f42ce4964cc23f2d8c039f106f25ddd58e10a1faed21b3bba4b0e621807b52dfda4a1902666629c9497d000000800000000000000000000000000000000000000000000000000000000000000000",
  216. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000033093a6540dbe8f7f3d19e3d2af05585ac58dafad890fa9a942e977334a23d6e52dfda4a190266665ae95079000000800000000000000000000000000000000000000000000000000000000000000000",
  217. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000bd7893057d06e69705bddf9a89c7bac6b40c5b32f15e2295fc8c5edf491ea24952dfda4a190266664b89b4d3000000800000000000000000000000000000000000000000000000000000000000000000",
  218. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000075e66f533e53837d14236a793ee4e493985642bc39e016b9e63adf14a584a2aa52dfda4a19026666ab5d638d000000800000000000000000000000000000000000000000000000000000000000000000",
  219. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d936f90c5db5f0fe1d017344443854fbf9e40a07a9b7e74fedc8661c23162bff52dfda4a19026666338e79cb000000800000000000000000000000000000000000000000000000000000000000000000",
  220. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000d2c1a7d279a4355b017bc0a4b0a9425707786729f21ee18add3fda4252a31a4152dfda4a190266669bc90806000000800000000000000000000000000000000000000000000000000000000000000000",
  221. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000ad36d19f33d04ca779942843890bc3b083cec83a4b60b6c45cf7d21fc187746552dfda4a1902666675d81ab7000000800000000000000000000000000000000000000000000000000000000000000000",
  222. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000093b809cf82b76082eacb55bc35b79f31882ed0976fd102ef54783cd24341319b52dfda4a1902666642ab4e42000000800000000000000000000000000000000000000000000000000000000000000000",
  223. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000007411ff315430a7bbf41de8a685d457e82d5177c05640d6a4436a40f39e99667852dfda4a190266662affa4b5000000800000000000000000000000000000000000000000000000000000000000000000",
  224. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000001ad0db5b9e1e2b57c8d3654c160f5a51067521eab7e340a270639d97f00a3fa252dfda4a1902666601a47bb6000000800000000000000000000000000000000000000000000000000000000000000000",
  225. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b19000000000000000022e055c442c46bbe16df68603a26891f6e4cf85b90102b39fd7cadb602b4e34552dfda4a1902666695d33cea000000800000000000000000000000000000000000000000000000000000000000000000",
  226. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b1900000000000000009c8baf5a8a1e16de2d6ae949d5fec3ed751f10dcd4c99810f2ce08040fb9e31d52dfda4a19026666fe78849d000000800000000000000000000000000000000000000000000000000000000000000000",
  227. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000e5655532b414887f35eb4652bc7b11ebac12891f65bc08cbe0ce5b277b9e795152dfda4a19026666fcc0d1d1000000800000000000000000000000000000000000000000000000000000000000000000",
  228. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000f272c5508704e2b62dd1c30ea970372c40bf00f9203f9bf69d456b4a7fbfffe352dfda4a19026666c03d4399000000800000000000000000000000000000000000000000000000000000000000000000",
  229. "0000000256ccc4c8aeae2b1e41490bc352893605f284e4be043f7b190000000000000000fca3b4531ba627ad9b0e23cdd84c888952c23810df196e9c6db0bcecba6a830952dfda4a19026666c14009cb000000800000000000000000000000000000000000000000000000000000000000000000"
  230. };
  231. const char btm_work_test_midstate[BITMAIN_TEST_NUM][256] = {
  232. "2d8738e7f5bcf76dcb8316fec772e20e240cd58c88d47f2d3f5a6a9547ed0a35",
  233. "d31b6ce09c0bfc2af6f3fe3a03475ebefa5aa191fa70a327a354b2c22f9692f1",
  234. "84a8c8224b80d36caeb42eff2a100f634e1ff873e83fd02ef1306a34abef9dbe",
  235. "059882159439b9b32968c79a93c5521e769dbea9d840f56c2a17b9ad87e530b8",
  236. "17fa435d05012574f8f1da26994cc87b6cb9660b5e82072dc6a0881cec150a0d",
  237. "92a28cc5ec4ba6a2688471dfe2032b5fe97c805ca286c503e447d6749796c6af",
  238. "1677a03516d6e9509ac37e273d2482da9af6e077abe8392cdca6a30e916a7ae9",
  239. "50bbe09f1b8ac18c97aeb745d5d2c3b5d669b6ac7803e646f65ac7b763a392d1",
  240. "e46a0022ebdc303a7fb1a0ebfa82b523946c312e745e5b8a116b17ae6b4ce981",
  241. "8f2f61e7f5b4d76d854e6d266acfff4d40347548216838ccc4ef3b9e43d3c9ea",
  242. "0a450588ae99f75d676a08d0326e1ea874a3497f696722c78a80c7b6ee961ea6",
  243. "3c4c0fc2cf040b806c51b46de9ec0dcc678a7cc5cf3eff11c6c03de3bc7818cc",
  244. "f6c7c785ab5daddb8f98e5f854f2cb41879fcaf47289eb2b4196fefc1b28316f",
  245. "005312351ccb0d0794779f5023e4335b5cad221accf0dfa3da7b881266fa9f5a",
  246. "7b26d189c6bba7add54143179aadbba7ccaeff6887bd8d5bec9597d5716126e6",
  247. "a4718f4c801e7ddf913a9474eb71774993525684ffea1915f767ab16e05e6889",
  248. "6b6226a8c18919d0e55684638d33a6892a00d22492cc2f5906ca7a4ac21c74a7",
  249. "383114dccd1cb824b869158aa2984d157fcb02f46234ceca65943e919329e697",
  250. "d4d478df3016852b27cb1ae9e1e98d98617f8d0943bf9dc1217f47f817236222"
  251. };
  252. #endif
  253. bool opt_bitmain_checkall = false;
  254. bool opt_bitmain_nobeeper = false;
  255. bool opt_bitmain_notempoverctrl = false;
  256. bool opt_bitmain_homemode = false;
  257. bool opt_bitmain_auto;
  258. // --------------------------------------------------------------
  259. // CRC16 check table
  260. // --------------------------------------------------------------
  261. static
  262. const uint8_t chCRCHTalbe[] = // CRC high byte table
  263. {
  264. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  265. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  266. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  267. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  268. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  269. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  270. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  271. 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  272. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  273. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  274. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  275. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  276. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  277. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  278. 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  279. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  280. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  281. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
  282. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  283. 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
  284. 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
  285. 0x00, 0xC1, 0x81, 0x40
  286. };
  287. static
  288. const uint8_t chCRCLTalbe[] = // CRC low byte table
  289. {
  290. 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
  291. 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
  292. 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
  293. 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
  294. 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
  295. 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
  296. 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
  297. 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
  298. 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
  299. 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
  300. 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
  301. 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
  302. 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
  303. 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
  304. 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
  305. 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
  306. 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
  307. 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
  308. 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
  309. 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
  310. 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
  311. 0x41, 0x81, 0x80, 0x40
  312. };
  313. static uint16_t CRC16(const uint8_t* p_data, uint16_t w_len)
  314. {
  315. uint8_t chCRCHi = 0xFF; // CRC high byte initialize
  316. uint8_t chCRCLo = 0xFF; // CRC low byte initialize
  317. uint16_t wIndex = 0; // CRC cycling index
  318. while (w_len--) {
  319. wIndex = chCRCLo ^ *p_data++;
  320. chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
  321. chCRCHi = chCRCLTalbe[wIndex];
  322. }
  323. return ((chCRCHi << 8) | chCRCLo);
  324. }
  325. static uint32_t num2bit(int num) {
  326. return 1L << (31 - num);
  327. }
  328. static int bitmain_set_txconfig(struct bitmain_txconfig_token *bm,
  329. uint8_t reset, uint8_t fan_eft, uint8_t timeout_eft, uint8_t frequency_eft,
  330. uint8_t voltage_eft, uint8_t chain_check_time_eft, uint8_t chip_config_eft, uint8_t hw_error_eft,
  331. uint8_t beeper_ctrl, uint8_t temp_over_ctrl,uint8_t fan_home_mode,
  332. uint8_t chain_num, uint8_t asic_num, uint8_t fan_pwm_data, uint8_t timeout_data,
  333. uint16_t frequency, uint8_t * voltage, uint8_t chain_check_time,
  334. uint8_t chip_address, uint8_t reg_address, uint8_t * reg_data)
  335. {
  336. uint16_t crc = 0;
  337. int datalen = 0;
  338. uint8_t version = 0;
  339. uint8_t * sendbuf = (uint8_t *)bm;
  340. if (unlikely(!bm)) {
  341. applog(LOG_WARNING, "bitmain_set_txconfig bitmain_txconfig_token is null");
  342. return -1;
  343. }
  344. if (unlikely(timeout_data <= 0 || asic_num <= 0 || chain_num <= 0)) {
  345. applog(LOG_WARNING, "bitmain_set_txconfig parameter invalid timeout_data(%d) asic_num(%d) chain_num(%d)",
  346. timeout_data, asic_num, chain_num);
  347. return -1;
  348. }
  349. datalen = sizeof(struct bitmain_txconfig_token);
  350. memset(bm, 0, datalen);
  351. bm->token_type = BITMAIN_TOKEN_TYPE_TXCONFIG;
  352. bm->version = version;
  353. bm->length = datalen-4;
  354. bm->length = htole16(bm->length);
  355. bm->reset = reset;
  356. bm->fan_eft = fan_eft;
  357. bm->timeout_eft = timeout_eft;
  358. bm->frequency_eft = frequency_eft;
  359. bm->voltage_eft = voltage_eft;
  360. bm->chain_check_time_eft = chain_check_time_eft;
  361. bm->chip_config_eft = chip_config_eft;
  362. bm->hw_error_eft = hw_error_eft;
  363. bm->beeper_ctrl = beeper_ctrl;
  364. bm->temp_over_ctrl = temp_over_ctrl;
  365. bm->fan_home_mode = fan_home_mode;
  366. sendbuf[4] = htole8(sendbuf[4]);
  367. sendbuf[5] = htole8(sendbuf[5]);
  368. bm->chain_num = chain_num;
  369. bm->asic_num = asic_num;
  370. bm->fan_pwm_data = fan_pwm_data;
  371. bm->timeout_data = timeout_data;
  372. bm->frequency = htole16(frequency);
  373. memcpy(bm->voltage, voltage, 2);
  374. bm->chain_check_time = chain_check_time;
  375. memcpy(bm->reg_data, reg_data, 4);
  376. bm->chip_address = chip_address;
  377. bm->reg_address = reg_address;
  378. crc = CRC16((uint8_t *)bm, datalen-2);
  379. bm->crc = htole16(crc);
  380. applog(LOG_ERR, "BTM TxConfigToken:v(%d) reset(%d) fan_e(%d) tout_e(%d) fq_e(%d) vt_e(%d) chainc_e(%d) chipc_e(%d) hw_e(%d) b_c(%d) t_c(%d) f_m(%d) mnum(%d) anum(%d) fanpwmdata(%d) toutdata(%d) freq(%d) volt(%02x%02x) chainctime(%d) regdata(%02x%02x%02x%02x) chipaddr(%02x) regaddr(%02x) crc(%04x)",
  381. version, reset, fan_eft, timeout_eft, frequency_eft, voltage_eft,
  382. chain_check_time_eft, chip_config_eft, hw_error_eft, beeper_ctrl, temp_over_ctrl,fan_home_mode,chain_num, asic_num,
  383. fan_pwm_data, timeout_data, frequency, voltage[0], voltage[1],
  384. chain_check_time, reg_data[0], reg_data[1], reg_data[2], reg_data[3], chip_address, reg_address, crc);
  385. return datalen;
  386. }
  387. static int bitmain_set_txtask(uint8_t * sendbuf,
  388. unsigned int * last_work_block, struct work **works, int work_array_size, int work_array, int sendworkcount, int * sendcount)
  389. {
  390. uint16_t crc = 0;
  391. uint32_t work_id = 0;
  392. uint8_t version = 0;
  393. int datalen = 0;
  394. int i = 0;
  395. int index = work_array;
  396. uint8_t new_block= 0;
  397. struct bitmain_txtask_token *bm = (struct bitmain_txtask_token *)sendbuf;
  398. *sendcount = 0;
  399. int cursendcount = 0;
  400. int diff = 0;
  401. unsigned int difftmp = 0;
  402. unsigned int pooldiff = 0;
  403. int netdiff = 0;
  404. if (unlikely(!bm)) {
  405. applog(LOG_WARNING, "bitmain_set_txtask bitmain_txtask_token is null");
  406. return -1;
  407. }
  408. if (unlikely(!works)) {
  409. applog(LOG_WARNING, "bitmain_set_txtask work is null");
  410. return -1;
  411. }
  412. memset(bm, 0, sizeof(struct bitmain_txtask_token));
  413. bm->token_type = BITMAIN_TOKEN_TYPE_TXTASK;
  414. bm->version = version;
  415. datalen = 10;
  416. applog(LOG_DEBUG, "BTM send work count %d -----", sendworkcount);
  417. pooldiff = 0x100;
  418. unsigned lowest_goal_diff = UINT_MAX;
  419. for (i = 0; i < sendworkcount; ++i) {
  420. if (index > work_array_size) {
  421. index = 0;
  422. }
  423. if (!works[index]) {
  424. continue;
  425. }
  426. struct work * const work = works[index];
  427. if (work->work_difficulty < pooldiff)
  428. pooldiff = work->work_difficulty;
  429. const struct pool * const pool = work->pool;
  430. const struct mining_goal_info * const goal = pool->goal;
  431. if (goal->current_diff < lowest_goal_diff)
  432. lowest_goal_diff = goal->current_diff;
  433. }
  434. {
  435. difftmp = pooldiff;
  436. while(1) {
  437. difftmp = difftmp >> 1;
  438. if(difftmp > 0) {
  439. diff++;
  440. if(diff >= 255) {
  441. break;
  442. }
  443. } else {
  444. break;
  445. }
  446. }
  447. for (uint64_t netdifftmp = lowest_goal_diff; netdifftmp > 0; netdifftmp >>= 1) {
  448. ++netdiff;
  449. }
  450. pooldiff = pow(2, diff);
  451. }
  452. applog(LOG_DEBUG, "bitmain_set_txtask using nonce_diff=%u (log2=%d) and goal_diff=%u (log2=%d)", pooldiff, diff, lowest_goal_diff, netdiff);
  453. for(i = 0; i < sendworkcount; i++) {
  454. if(index > work_array_size) {
  455. index = 0;
  456. }
  457. if(works[index]) {
  458. const unsigned int work_block = bfg_work_block(works[index]);
  459. if(work_block != *last_work_block) {
  460. applog(LOG_ERR, "BTM send task new block %d old(%d)", work_block, *last_work_block);
  461. new_block = 1;
  462. *last_work_block = work_block;
  463. }
  464. #ifdef BITMAIN_TEST
  465. if(!hex2bin(works[index]->data, btm_work_test_data[g_test_index], 128)) {
  466. applog(LOG_DEBUG, "BTM send task set test data error");
  467. }
  468. if(!hex2bin(works[index]->midstate, btm_work_test_midstate[g_test_index], 32)) {
  469. applog(LOG_DEBUG, "BTM send task set test midstate error");
  470. }
  471. g_test_index++;
  472. if(g_test_index >= BITMAIN_TEST_USENUM) {
  473. g_test_index = 0;
  474. }
  475. applog(LOG_DEBUG, "BTM test index = %d", g_test_index);
  476. #endif
  477. work_id = works[index]->id;
  478. bm->works[cursendcount].work_id = htole32(work_id);
  479. applog(LOG_DEBUG, "BTM send task work id:%d %d", bm->works[cursendcount].work_id, work_id);
  480. memcpy(bm->works[cursendcount].midstate, works[index]->midstate, 32);
  481. memcpy(bm->works[cursendcount].data2, works[index]->data + 64, 12);
  482. works[index]->nonce_diff = pooldiff;
  483. if(BITMAIN_TEST_PRINT_WORK) {
  484. char ob_hex[(76 * 2) + 1];
  485. bin2hex(ob_hex, works[index]->data, 76);
  486. applog(LOG_ERR, "work %d data: %s", works[index]->id, ob_hex);
  487. }
  488. cursendcount++;
  489. }
  490. index++;
  491. }
  492. if(cursendcount <= 0) {
  493. applog(LOG_ERR, "BTM send work count %d", cursendcount);
  494. return 0;
  495. }
  496. datalen += 48*cursendcount;
  497. bm->length = datalen-4;
  498. bm->length = htole16(bm->length);
  499. //len = datalen-3;
  500. //len = htole16(len);
  501. //memcpy(sendbuf+1, &len, 2);
  502. bm->new_block = new_block;
  503. bm->diff = diff;
  504. bm->net_diff = htole16(netdiff);
  505. sendbuf[4] = htole8(sendbuf[4]);
  506. applog(LOG_DEBUG, "BitMain TxTask Token: %d %d %02x%02x%02x%02x%02x%02x",
  507. datalen, bm->length, sendbuf[0],sendbuf[1],sendbuf[2],sendbuf[3],sendbuf[4],sendbuf[5]);
  508. *sendcount = cursendcount;
  509. crc = CRC16(sendbuf, datalen-2);
  510. crc = htole16(crc);
  511. memcpy(sendbuf+datalen-2, &crc, 2);
  512. applog(LOG_DEBUG, "BitMain TxTask Token: v(%d) new_block(%d) diff(%d pool:%d net:%d) work_num(%d) crc(%04x)",
  513. version, new_block, diff, pooldiff,netdiff, cursendcount, crc);
  514. applog(LOG_DEBUG, "BitMain TxTask Token: %d %d %02x%02x%02x%02x%02x%02x",
  515. datalen, bm->length, sendbuf[0],sendbuf[1],sendbuf[2],sendbuf[3],sendbuf[4],sendbuf[5]);
  516. return datalen;
  517. }
  518. static int bitmain_set_rxstatus(struct bitmain_rxstatus_token *bm,
  519. uint8_t chip_status_eft, uint8_t detect_get, uint8_t chip_address, uint8_t reg_address)
  520. {
  521. uint16_t crc = 0;
  522. uint8_t version = 0;
  523. int datalen = 0;
  524. uint8_t * sendbuf = (uint8_t *)bm;
  525. if (unlikely(!bm)) {
  526. applog(LOG_WARNING, "bitmain_set_rxstatus bitmain_rxstatus_token is null");
  527. return -1;
  528. }
  529. datalen = sizeof(struct bitmain_rxstatus_token);
  530. memset(bm, 0, datalen);
  531. bm->token_type = BITMAIN_TOKEN_TYPE_RXSTATUS;
  532. bm->version = version;
  533. bm->length = datalen-4;
  534. bm->length = htole16(bm->length);
  535. bm->chip_status_eft = chip_status_eft;
  536. bm->detect_get = detect_get;
  537. sendbuf[4] = htole8(sendbuf[4]);
  538. bm->chip_address = chip_address;
  539. bm->reg_address = reg_address;
  540. crc = CRC16((uint8_t *)bm, datalen-2);
  541. bm->crc = htole16(crc);
  542. applog(LOG_ERR, "BitMain RxStatus Token: v(%d) chip_status_eft(%d) detect_get(%d) chip_address(%02x) reg_address(%02x) crc(%04x)",
  543. version, chip_status_eft, detect_get, chip_address, reg_address, crc);
  544. return datalen;
  545. }
  546. static int bitmain_parse_rxstatus(const uint8_t * data, int datalen, struct bitmain_rxstatus_data *bm)
  547. {
  548. uint16_t crc = 0;
  549. uint8_t version = 0;
  550. int i = 0, j = 0;
  551. int asic_num = 0;
  552. int dataindex = 0;
  553. uint8_t tmp = 0x01;
  554. if (unlikely(!bm)) {
  555. applog(LOG_WARNING, "bitmain_parse_rxstatus bitmain_rxstatus_data is null");
  556. return -1;
  557. }
  558. if (unlikely(!data || datalen <= 0)) {
  559. applog(LOG_WARNING, "bitmain_parse_rxstatus parameter invalid data is null or datalen(%d) error", datalen);
  560. return -1;
  561. }
  562. memset(bm, 0, sizeof(struct bitmain_rxstatus_data));
  563. memcpy(bm, data, 28);
  564. if (bm->data_type != BITMAIN_DATA_TYPE_RXSTATUS) {
  565. applog(LOG_ERR, "bitmain_parse_rxstatus datatype(%02x) error", bm->data_type);
  566. return -1;
  567. }
  568. if (bm->version != version) {
  569. applog(LOG_ERR, "bitmain_parse_rxstatus version(%02x) error", bm->version);
  570. return -1;
  571. }
  572. bm->length = htole16(bm->length);
  573. if (bm->length+4 != datalen) {
  574. applog(LOG_ERR, "bitmain_parse_rxstatus length(%d) datalen(%d) error", bm->length, datalen);
  575. return -1;
  576. }
  577. crc = CRC16(data, datalen-2);
  578. memcpy(&(bm->crc), data+datalen-2, 2);
  579. bm->crc = htole16(bm->crc);
  580. if(crc != bm->crc) {
  581. applog(LOG_ERR, "bitmain_parse_rxstatus check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  582. return -1;
  583. }
  584. bm->fifo_space = htole16(bm->fifo_space);
  585. bm->fan_exist = htole16(bm->fan_exist);
  586. bm->temp_exist = htole32(bm->temp_exist);
  587. bm->nonce_error = htole32(bm->nonce_error);
  588. if(bm->chain_num > BITMAIN_MAX_CHAIN_NUM) {
  589. applog(LOG_ERR, "bitmain_parse_rxstatus chain_num=%d error", bm->chain_num);
  590. return -1;
  591. }
  592. dataindex = 28;
  593. if(bm->chain_num > 0) {
  594. memcpy(bm->chain_asic_num, data+datalen-2-bm->chain_num-bm->temp_num-bm->fan_num, bm->chain_num);
  595. }
  596. for(i = 0; i < bm->chain_num; i++) {
  597. asic_num = bm->chain_asic_num[i];
  598. if(asic_num <= 0) {
  599. asic_num = 1;
  600. } else {
  601. if(asic_num % 32 == 0) {
  602. asic_num = asic_num / 32;
  603. } else {
  604. asic_num = asic_num / 32 + 1;
  605. }
  606. }
  607. memcpy((uint8_t *)bm->chain_asic_exist+i*32, data+dataindex, asic_num*4);
  608. dataindex += asic_num*4;
  609. }
  610. for(i = 0; i < bm->chain_num; i++) {
  611. asic_num = bm->chain_asic_num[i];
  612. if(asic_num <= 0) {
  613. asic_num = 1;
  614. } else {
  615. if(asic_num % 32 == 0) {
  616. asic_num = asic_num / 32;
  617. } else {
  618. asic_num = asic_num / 32 + 1;
  619. }
  620. }
  621. memcpy((uint8_t *)bm->chain_asic_status+i*32, data+dataindex, asic_num*4);
  622. dataindex += asic_num*4;
  623. }
  624. dataindex += bm->chain_num;
  625. if(dataindex + bm->temp_num + bm->fan_num + 2 != datalen) {
  626. applog(LOG_ERR, "bitmain_parse_rxstatus dataindex(%d) chain_num(%d) temp_num(%d) fan_num(%d) not match datalen(%d)",
  627. dataindex, bm->chain_num, bm->temp_num, bm->fan_num, datalen);
  628. return -1;
  629. }
  630. for(i = 0; i < bm->chain_num; i++) {
  631. //bm->chain_asic_status[i] = swab32(bm->chain_asic_status[i]);
  632. for(j = 0; j < 8; j++) {
  633. bm->chain_asic_exist[i*8+j] = htole32(bm->chain_asic_exist[i*8+j]);
  634. bm->chain_asic_status[i*8+j] = htole32(bm->chain_asic_status[i*8+j]);
  635. }
  636. }
  637. if(bm->temp_num > 0) {
  638. memcpy(bm->temp, data+dataindex, bm->temp_num);
  639. dataindex += bm->temp_num;
  640. }
  641. if(bm->fan_num > 0) {
  642. memcpy(bm->fan, data+dataindex, bm->fan_num);
  643. dataindex += bm->fan_num;
  644. }
  645. if(!opt_bitmain_checkall){
  646. if(tmp != htole8(tmp)){
  647. applog(LOG_ERR, "BitMain RxStatus byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  648. memcpy(&tmp,data+4,1);
  649. bm->chip_value_eft = tmp >>7;
  650. bm->get_blk_num = tmp >> 4;
  651. bm->reserved1 = ((tmp << 4) & 0xff) >> 5;
  652. }
  653. found_blocks = bm->get_blk_num;
  654. applog(LOG_ERR, "BitMain RxStatus tmp :0x%02x byte4 0x%02x chip_value_eft %d reserved %d get_blk_num %d ",tmp,*((uint8_t* )bm +4),bm->chip_value_eft,bm->reserved1,bm->get_blk_num);
  655. }
  656. applog(LOG_DEBUG, "BitMain RxStatusData: chipv_e(%d) chainnum(%d) fifos(%d) v1(%d) v2(%d) v3(%d) v4(%d) fann(%d) tempn(%d) fanet(%04x) tempet(%08x) ne(%d) regvalue(%d) crc(%04x)",
  657. bm->chip_value_eft, bm->chain_num, bm->fifo_space, bm->hw_version[0], bm->hw_version[1], bm->hw_version[2], bm->hw_version[3], bm->fan_num, bm->temp_num, bm->fan_exist, bm->temp_exist, bm->nonce_error, bm->reg_value, bm->crc);
  658. applog(LOG_DEBUG, "BitMain RxStatus Data chain info:");
  659. for(i = 0; i < bm->chain_num; i++) {
  660. applog(LOG_DEBUG, "BitMain RxStatus Data chain(%d) asic num=%d asic_exist=%08x asic_status=%08x", i+1, bm->chain_asic_num[i], bm->chain_asic_exist[i*8], bm->chain_asic_status[i*8]);
  661. }
  662. applog(LOG_DEBUG, "BitMain RxStatus Data temp info:");
  663. for(i = 0; i < bm->temp_num; i++) {
  664. applog(LOG_DEBUG, "BitMain RxStatus Data temp(%d) temp=%d", i+1, bm->temp[i]);
  665. }
  666. applog(LOG_DEBUG, "BitMain RxStatus Data fan info:");
  667. for(i = 0; i < bm->fan_num; i++) {
  668. applog(LOG_DEBUG, "BitMain RxStatus Data fan(%d) fan=%d", i+1, bm->fan[i]);
  669. }
  670. return 0;
  671. }
  672. static int bitmain_parse_rxnonce(const uint8_t * data, int datalen, struct bitmain_rxnonce_data *bm, int * nonce_num)
  673. {
  674. int i = 0;
  675. uint16_t crc = 0;
  676. uint8_t version = 0;
  677. int curnoncenum = 0;
  678. if (unlikely(!bm)) {
  679. applog(LOG_ERR, "bitmain_parse_rxnonce bitmain_rxstatus_data null");
  680. return -1;
  681. }
  682. if (unlikely(!data || datalen <= 0)) {
  683. applog(LOG_ERR, "bitmain_parse_rxnonce data null or datalen(%d) error", datalen);
  684. return -1;
  685. }
  686. memcpy(bm, data, sizeof(struct bitmain_rxnonce_data));
  687. if (bm->data_type != BITMAIN_DATA_TYPE_RXNONCE) {
  688. applog(LOG_ERR, "bitmain_parse_rxnonce datatype(%02x) error", bm->data_type);
  689. return -1;
  690. }
  691. if (bm->version != version) {
  692. applog(LOG_ERR, "bitmain_parse_rxnonce version(%02x) error", bm->version);
  693. return -1;
  694. }
  695. bm->length = htole16(bm->length);
  696. if (bm->length+4 != datalen) {
  697. applog(LOG_ERR, "bitmain_parse_rxnonce length(%d) error", bm->length);
  698. return -1;
  699. }
  700. crc = CRC16(data, datalen-2);
  701. memcpy(&(bm->crc), data+datalen-2, 2);
  702. bm->crc = htole16(bm->crc);
  703. if(crc != bm->crc) {
  704. applog(LOG_ERR, "bitmain_parse_rxnonce check crc(%d) != bm crc(%d) datalen(%d)", crc, bm->crc, datalen);
  705. return -1;
  706. }
  707. bm->fifo_space = htole16(bm->fifo_space);
  708. bm->diff = htole16(bm->diff);
  709. bm->total_nonce_num = htole64(bm->total_nonce_num);
  710. curnoncenum = (datalen-14)/8;
  711. applog(LOG_DEBUG, "BitMain RxNonce Data: nonce_num(%d) fifo_space(%d) diff(%d) tnn(%"PRIu64")", curnoncenum, bm->fifo_space, bm->diff, bm->total_nonce_num);
  712. for(i = 0; i < curnoncenum; i++) {
  713. bm->nonces[i].work_id = htole32(bm->nonces[i].work_id);
  714. bm->nonces[i].nonce = htole32(bm->nonces[i].nonce);
  715. applog(LOG_DEBUG, "BitMain RxNonce Data %d: work_id(%d) nonce(%08x)(%d)",
  716. i, bm->nonces[i].work_id, bm->nonces[i].nonce, bm->nonces[i].nonce);
  717. }
  718. *nonce_num = curnoncenum;
  719. return 0;
  720. }
  721. static int bitmain_read(struct cgpu_info *bitmain, unsigned char *buf,
  722. size_t bufsize, int timeout)
  723. {
  724. int err = 0;
  725. size_t total = 0;
  726. if(bitmain == NULL || buf == NULL || bufsize <= 0) {
  727. applog(LOG_WARNING, "bitmain_read parameter error bufsize(%llu)", (unsigned long long)bufsize);
  728. return -1;
  729. }
  730. {
  731. err = btm_read(bitmain, buf, bufsize);
  732. total = err;
  733. }
  734. return total;
  735. }
  736. static int bitmain_write(struct cgpu_info *bitmain, char *buf, ssize_t len)
  737. {
  738. int err;
  739. {
  740. int havelen = 0;
  741. while(havelen < len) {
  742. err = btm_write(bitmain, buf+havelen, len-havelen);
  743. if(err < 0) {
  744. applog(LOG_DEBUG, "%s%i: btm_write got err %d", bitmain->drv->name,
  745. bitmain->device_id, err);
  746. applog(LOG_WARNING, "usb_write error on bitmain_write");
  747. return BTM_SEND_ERROR;
  748. } else {
  749. havelen += err;
  750. }
  751. }
  752. }
  753. return BTM_SEND_OK;
  754. }
  755. static int bitmain_send_data(const uint8_t * data, int datalen, struct cgpu_info *bitmain)
  756. {
  757. int ret;
  758. if(datalen <= 0) {
  759. return 0;
  760. }
  761. //struct bitmain_info *info = bitmain->device_data;
  762. //int delay;
  763. //delay = datalen * 10 * 1000000;
  764. //delay = delay / info->baud;
  765. //delay += 4000;
  766. if(opt_debug) {
  767. char hex[(datalen * 2) + 1];
  768. bin2hex(hex, data, datalen);
  769. applog(LOG_DEBUG, "BitMain: Sent(%d): %s", datalen, hex);
  770. }
  771. //cgtimer_t ts_start;
  772. //cgsleep_prepare_r(&ts_start);
  773. //applog(LOG_DEBUG, "----bitmain_send_data start");
  774. ret = bitmain_write(bitmain, (char *)data, datalen);
  775. applog(LOG_DEBUG, "----bitmain_send_data stop ret=%d datalen=%d", ret, datalen);
  776. //cgsleep_us_r(&ts_start, delay);
  777. //applog(LOG_DEBUG, "BitMain: Sent: Buffer delay: %dus", delay);
  778. return ret;
  779. }
  780. static void bitmain_inc_nvw(struct bitmain_info *info, struct thr_info *thr)
  781. {
  782. applog(LOG_INFO, "%s%d: No matching work - HW error",
  783. thr->cgpu->drv->name, thr->cgpu->device_id);
  784. inc_hw_errors_only(thr);
  785. info->no_matching_work++;
  786. }
  787. static inline void record_temp_fan(struct bitmain_info *info, struct bitmain_rxstatus_data *bm, float *temp)
  788. {
  789. int i = 0;
  790. int maxfan = 0, maxtemp = 0;
  791. int temp_avg = 0;
  792. info->fan_num = bm->fan_num;
  793. for(i = 0; i < bm->fan_num; i++) {
  794. info->fan[i] = bm->fan[i] * BITMAIN_FAN_FACTOR;
  795. if(info->fan[i] > maxfan)
  796. maxfan = info->fan[i];
  797. }
  798. info->temp_num = bm->temp_num;
  799. for(i = 0; i < bm->temp_num; i++) {
  800. info->temp[i] = bm->temp[i];
  801. /*
  802. if(bm->temp[i] & 0x80) {
  803. bm->temp[i] &= 0x7f;
  804. info->temp[i] = 0 - ((~bm->temp[i] & 0x7f) + 1);
  805. }*/
  806. temp_avg += info->temp[i];
  807. if(info->temp[i] > info->temp_max) {
  808. info->temp_max = info->temp[i];
  809. }
  810. if(info->temp[i] > maxtemp)
  811. maxtemp = info->temp[i];
  812. }
  813. if(bm->temp_num > 0) {
  814. temp_avg /= bm->temp_num;
  815. info->temp_avg = temp_avg;
  816. }
  817. *temp = maxtemp;
  818. }
  819. static void bitmain_update_temps(struct cgpu_info *bitmain, struct bitmain_info *info,
  820. struct bitmain_rxstatus_data *bm)
  821. {
  822. char tmp[64] = {0};
  823. char msg[10240] = {0};
  824. int i = 0;
  825. record_temp_fan(info, bm, &(bitmain->temp));
  826. strcpy(msg, "BitMain: ");
  827. for(i = 0; i < bm->fan_num; i++) {
  828. if(i != 0) {
  829. strcat(msg, ", ");
  830. }
  831. sprintf(tmp, "Fan%d: %d/m", i+1, info->fan[i]);
  832. strcat(msg, tmp);
  833. }
  834. strcat(msg, "\t");
  835. for(i = 0; i < bm->temp_num; i++) {
  836. if(i != 0) {
  837. strcat(msg, ", ");
  838. }
  839. sprintf(tmp, "Temp%d: %dC", i+1, info->temp[i]);
  840. strcat(msg, tmp);
  841. }
  842. sprintf(tmp, ", TempMAX: %dC", info->temp_max);
  843. strcat(msg, tmp);
  844. applog(LOG_INFO, "%s", msg);
  845. info->temp_history_index++;
  846. info->temp_sum += bitmain->temp;
  847. applog(LOG_DEBUG, "BitMain: temp_index: %d, temp_count: %d, temp_old: %d",
  848. info->temp_history_index, info->temp_history_count, info->temp_old);
  849. if (info->temp_history_index == info->temp_history_count) {
  850. info->temp_history_index = 0;
  851. info->temp_sum = 0;
  852. }
  853. }
  854. static void bitmain_parse_results(struct cgpu_info *bitmain, struct bitmain_info *info,
  855. struct thr_info *thr, uint8_t *buf, int *offset)
  856. {
  857. int i, j, n, m, r, errordiff, spare = BITMAIN_READ_SIZE;
  858. uint32_t checkbit = 0x00000000;
  859. bool found = false;
  860. struct work *work = NULL;
  861. struct bitmain_packet_head packethead;
  862. int asicnum = 0;
  863. int idiff = 0;
  864. int mod = 0,tmp = 0;
  865. for (i = 0; i <= spare; i++) {
  866. if(buf[i] == 0xa1) {
  867. struct bitmain_rxstatus_data rxstatusdata;
  868. applog(LOG_DEBUG, "bitmain_parse_results RxStatus Data");
  869. if(*offset < 4) {
  870. return;
  871. }
  872. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  873. packethead.length = htole16(packethead.length);
  874. if(packethead.length > 1130) {
  875. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus datalen=%d error", packethead.length+4);
  876. continue;
  877. }
  878. if(*offset < packethead.length + 4) {
  879. return;
  880. }
  881. if(bitmain_parse_rxstatus(buf+i, packethead.length+4, &rxstatusdata) != 0) {
  882. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxstatus error len=%d", packethead.length+4);
  883. } else {
  884. mutex_lock(&info->qlock);
  885. info->chain_num = rxstatusdata.chain_num;
  886. info->fifo_space = rxstatusdata.fifo_space;
  887. info->hw_version[0] = rxstatusdata.hw_version[0];
  888. info->hw_version[1] = rxstatusdata.hw_version[1];
  889. info->hw_version[2] = rxstatusdata.hw_version[2];
  890. info->hw_version[3] = rxstatusdata.hw_version[3];
  891. info->nonce_error = rxstatusdata.nonce_error;
  892. errordiff = info->nonce_error-info->last_nonce_error;
  893. //sprintf(g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  894. applog(LOG_ERR, "bitmain_parse_results v=%d chain=%d fifo=%d hwv1=%d hwv2=%d hwv3=%d hwv4=%d nerr=%d-%d freq=%d chain info:",
  895. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  896. info->last_nonce_error, info->nonce_error, info->frequency);
  897. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  898. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  899. for(n = 0; n < rxstatusdata.chain_num; n++) {
  900. info->chain_asic_num[n] = rxstatusdata.chain_asic_num[n];
  901. memset(info->chain_asic_status_t[n], 0, 320);
  902. j = 0;
  903. mod = 0;
  904. if(info->chain_asic_num[n] <= 0) {
  905. asicnum = 0;
  906. } else {
  907. mod = info->chain_asic_num[n] % 32;
  908. if(mod == 0) {
  909. asicnum = info->chain_asic_num[n] / 32;
  910. } else {
  911. asicnum = info->chain_asic_num[n] / 32 + 1;
  912. }
  913. }
  914. if(asicnum > 0) {
  915. for(m = asicnum-1; m >= 0; m--) {
  916. tmp = mod ? (32-mod): 0;
  917. for(r = tmp;r < 32;r++){
  918. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  919. info->chain_asic_status_t[n][j] = ' ';
  920. j++;
  921. }
  922. checkbit = num2bit(r);
  923. if(rxstatusdata.chain_asic_exist[n*8+m] & checkbit) {
  924. if(rxstatusdata.chain_asic_status[n*8+m] & checkbit) {
  925. info->chain_asic_status_t[n][j] = 'o';
  926. } else {
  927. info->chain_asic_status_t[n][j] = 'x';
  928. }
  929. } else {
  930. info->chain_asic_status_t[n][j] = '-';
  931. }
  932. j++;
  933. }
  934. info->chain_asic_status_t[n][j] = ' ';
  935. j++;
  936. mod = 0;
  937. }
  938. }
  939. applog(LOG_DEBUG, "bitmain_parse_results chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  940. n, info->chain_asic_num[n],
  941. info->chain_asic_exist[n*8+0], info->chain_asic_exist[n*8+1], info->chain_asic_exist[n*8+2], info->chain_asic_exist[n*8+3], info->chain_asic_exist[n*8+4], info->chain_asic_exist[n*8+5], info->chain_asic_exist[n*8+6], info->chain_asic_exist[n*8+7],
  942. info->chain_asic_status[n*8+0], info->chain_asic_status[n*8+1], info->chain_asic_status[n*8+2], info->chain_asic_status[n*8+3], info->chain_asic_status[n*8+4], info->chain_asic_status[n*8+5], info->chain_asic_status[n*8+6], info->chain_asic_status[n*8+7]);
  943. applog(LOG_ERR, "bitmain_parse_results chain(%d) asic_num=%d asic_status=%s", n, info->chain_asic_num[n], info->chain_asic_status_t[n]);
  944. }
  945. mutex_unlock(&info->qlock);
  946. if(errordiff > 0) {
  947. for(j = 0; j < errordiff; j++) {
  948. bitmain_inc_nvw(info, thr);
  949. }
  950. mutex_lock(&info->qlock);
  951. info->last_nonce_error += errordiff;
  952. mutex_unlock(&info->qlock);
  953. }
  954. bitmain_update_temps(bitmain, info, &rxstatusdata);
  955. }
  956. found = true;
  957. spare = packethead.length + 4 + i;
  958. if(spare > *offset) {
  959. applog(LOG_ERR, "bitmain_parse_rxresults space(%d) > offset(%d)", spare, *offset);
  960. spare = *offset;
  961. }
  962. break;
  963. } else if(buf[i] == 0xa2) {
  964. struct bitmain_rxnonce_data rxnoncedata;
  965. int nonce_num = 0;
  966. applog(LOG_DEBUG, "bitmain_parse_results RxNonce Data");
  967. if(*offset < 4) {
  968. return;
  969. }
  970. memcpy(&packethead, buf+i, sizeof(struct bitmain_packet_head));
  971. packethead.length = htole16(packethead.length);
  972. if(packethead.length > 1030) {
  973. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce datalen=%d error", packethead.length+4);
  974. continue;
  975. }
  976. if(*offset < packethead.length + 4) {
  977. return;
  978. }
  979. if(bitmain_parse_rxnonce(buf+i, packethead.length+4, &rxnoncedata, &nonce_num) != 0) {
  980. applog(LOG_ERR, "bitmain_parse_results bitmain_parse_rxnonce error len=%d", packethead.length+4);
  981. } else {
  982. for(j = 0; j < nonce_num; j++) {
  983. const int work_id = rxnoncedata.nonces[j].work_id;
  984. HASH_FIND_INT(bitmain->queued_work, &work_id, work);
  985. if(work) {
  986. if(BITMAIN_TEST_PRINT_WORK) {
  987. applog(LOG_ERR, "bitmain_parse_results nonce find work(%d-%d)(%08x)", work->id, rxnoncedata.nonces[j].work_id, rxnoncedata.nonces[j].nonce);
  988. char ob_hex[(32 * 2) + 1];
  989. bin2hex(ob_hex, work->midstate, 32);
  990. applog(LOG_ERR, "work %d midstate: %s", work->id, ob_hex);
  991. bin2hex(ob_hex, &work->data[64], 12);
  992. applog(LOG_ERR, "work %d data2: %s", work->id, ob_hex);
  993. }
  994. {
  995. const uint32_t nonce = rxnoncedata.nonces[j].nonce;
  996. applog(LOG_DEBUG, "BitMain: submit nonce = %08lx", (unsigned long)nonce);
  997. if (submit_nonce(thr, work, nonce)) {
  998. mutex_lock(&info->qlock);
  999. info->nonces++;
  1000. info->auto_nonces++;
  1001. mutex_unlock(&info->qlock);
  1002. } else {
  1003. //bitmain_inc_nvw(info, thr);
  1004. applog(LOG_ERR, "BitMain: bitmain_decode_nonce error work(%d)", rxnoncedata.nonces[j].work_id);
  1005. }
  1006. }
  1007. } else {
  1008. //bitmain_inc_nvw(info, thr);
  1009. applog(LOG_ERR, "BitMain: Nonce not find work(%d)", rxnoncedata.nonces[j].work_id);
  1010. }
  1011. }
  1012. #ifdef BITMAIN_CALC_DIFF1
  1013. if(opt_bitmain_hwerror) {
  1014. int difftmp = 0;
  1015. difftmp = rxnoncedata.diff;
  1016. idiff = 1;
  1017. while(difftmp > 0) {
  1018. difftmp--;
  1019. idiff = idiff << 1;
  1020. }
  1021. mutex_lock(&info->qlock);
  1022. difftmp = idiff*(rxnoncedata.total_nonce_num-info->total_nonce_num);
  1023. if(difftmp < 0)
  1024. difftmp = 0;
  1025. info->nonces = info->nonces+difftmp;
  1026. info->auto_nonces = info->auto_nonces+difftmp;
  1027. info->total_nonce_num = rxnoncedata.total_nonce_num;
  1028. info->fifo_space = rxnoncedata.fifo_space;
  1029. mutex_unlock(&info->qlock);
  1030. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d diff=%d rxtnn=%"PRIu64" tnn=%"PRIu64, info->fifo_space, idiff, rxnoncedata.total_nonce_num, info->total_nonce_num);
  1031. } else {
  1032. mutex_lock(&info->qlock);
  1033. info->fifo_space = rxnoncedata.fifo_space;
  1034. mutex_unlock(&info->qlock);
  1035. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  1036. }
  1037. #else
  1038. mutex_lock(&info->qlock);
  1039. info->fifo_space = rxnoncedata.fifo_space;
  1040. mutex_unlock(&info->qlock);
  1041. applog(LOG_DEBUG, "bitmain_parse_rxnonce fifo space=%d", info->fifo_space);
  1042. #endif
  1043. #ifndef WIN32
  1044. if(nonce_num < BITMAIN_MAX_NONCE_NUM)
  1045. cgsleep_ms(5);
  1046. #endif
  1047. }
  1048. found = true;
  1049. spare = packethead.length + 4 + i;
  1050. if(spare > *offset) {
  1051. applog(LOG_ERR, "bitmain_parse_rxnonce space(%d) > offset(%d)", spare, *offset);
  1052. spare = *offset;
  1053. }
  1054. break;
  1055. } else {
  1056. applog(LOG_ERR, "bitmain_parse_results data type error=%02x", buf[i]);
  1057. }
  1058. }
  1059. if (!found) {
  1060. spare = *offset - BITMAIN_READ_SIZE;
  1061. /* We are buffering and haven't accumulated one more corrupt
  1062. * work result. */
  1063. if (spare < (int)BITMAIN_READ_SIZE)
  1064. return;
  1065. bitmain_inc_nvw(info, thr);
  1066. }
  1067. *offset -= spare;
  1068. memmove(buf, buf + spare, *offset);
  1069. }
  1070. static void bitmain_running_reset(struct cgpu_info *bitmain, struct bitmain_info *info)
  1071. {
  1072. bitmain->results = 0;
  1073. info->reset = false;
  1074. }
  1075. static void *bitmain_get_results(void *userdata)
  1076. {
  1077. struct cgpu_info *bitmain = (struct cgpu_info *)userdata;
  1078. struct bitmain_info *info = bitmain->device_data;
  1079. int offset = 0, ret = 0;
  1080. const int rsize = BITMAIN_FTDI_READSIZE;
  1081. uint8_t readbuf[BITMAIN_READBUF_SIZE];
  1082. struct thr_info *thr = info->thr;
  1083. char threadname[24];
  1084. int errorcount = 0;
  1085. snprintf(threadname, 24, "btm_recv/%d", bitmain->device_id);
  1086. RenameThread(threadname);
  1087. while (likely(!bitmain->shutdown)) {
  1088. unsigned char buf[rsize];
  1089. //applog(LOG_DEBUG, "+++++++bitmain_get_results offset=%d", offset);
  1090. if (offset >= (int)BITMAIN_READ_SIZE) {
  1091. //applog(LOG_DEBUG, "======start bitmain_get_results ");
  1092. bitmain_parse_results(bitmain, info, thr, readbuf, &offset);
  1093. //applog(LOG_DEBUG, "======stop bitmain_get_results ");
  1094. }
  1095. if (unlikely(offset + rsize >= BITMAIN_READBUF_SIZE)) {
  1096. /* This should never happen */
  1097. applog(LOG_DEBUG, "BitMain readbuf overflow, resetting buffer");
  1098. offset = 0;
  1099. }
  1100. if (unlikely(info->reset)) {
  1101. bitmain_running_reset(bitmain, info);
  1102. /* Discard anything in the buffer */
  1103. offset = 0;
  1104. }
  1105. /* As the usb read returns after just 1ms, sleep long enough
  1106. * to leave the interface idle for writes to occur, but do not
  1107. * sleep if we have been receiving data as more may be coming. */
  1108. //if (offset == 0) {
  1109. // cgsleep_ms_r(&ts_start, BITMAIN_READ_TIMEOUT);
  1110. //}
  1111. //cgsleep_prepare_r(&ts_start);
  1112. //applog(LOG_DEBUG, "======start bitmain_get_results bitmain_read");
  1113. ret = bitmain_read(bitmain, buf, rsize, BITMAIN_READ_TIMEOUT);
  1114. //applog(LOG_DEBUG, "======stop bitmain_get_results bitmain_read=%d", ret);
  1115. if ((ret < 1) || (ret == 18)) {
  1116. errorcount++;
  1117. #ifdef WIN32
  1118. if(errorcount > 200) {
  1119. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  1120. cgsleep_ms(20);
  1121. errorcount = 0;
  1122. }
  1123. #else
  1124. if(errorcount > 3) {
  1125. //applog(LOG_ERR, "bitmain_read errorcount ret=%d", ret);
  1126. cgsleep_ms(20);
  1127. errorcount = 0;
  1128. }
  1129. #endif
  1130. if(ret < 1)
  1131. continue;
  1132. }
  1133. if (opt_debug) {
  1134. char hex[(ret * 2) + 1];
  1135. bin2hex(hex, buf, ret);
  1136. applog(LOG_DEBUG, "BitMain: get: %s", hex);
  1137. }
  1138. memcpy(readbuf+offset, buf, ret);
  1139. offset += ret;
  1140. }
  1141. return NULL;
  1142. }
  1143. static void bitmain_init(struct cgpu_info *bitmain)
  1144. {
  1145. applog(LOG_INFO, "BitMain: Opened on %s", bitmain->device_path);
  1146. }
  1147. static bool bitmain_prepare(struct thr_info *thr)
  1148. {
  1149. struct cgpu_info *bitmain = thr->cgpu;
  1150. struct bitmain_info *info = bitmain->device_data;
  1151. free(bitmain->works);
  1152. bitmain->works = calloc(BITMAIN_MAX_WORK_NUM * sizeof(struct work *),
  1153. BITMAIN_ARRAY_SIZE);
  1154. if (!bitmain->works)
  1155. quit(1, "Failed to calloc bitmain works in bitmain_prepare");
  1156. info->thr = thr;
  1157. mutex_init(&info->lock);
  1158. mutex_init(&info->qlock);
  1159. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1160. quit(1, "Failed to pthread_cond_init bitmain qcond");
  1161. if (pthread_create(&info->read_thr, NULL, bitmain_get_results, (void *)bitmain))
  1162. quit(1, "Failed to create bitmain read_thr");
  1163. bitmain_init(bitmain);
  1164. return true;
  1165. }
  1166. static int bitmain_initialize(struct cgpu_info *bitmain)
  1167. {
  1168. uint8_t data[BITMAIN_READBUF_SIZE];
  1169. struct bitmain_info *info = NULL;
  1170. int ret = 0;
  1171. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1172. int readlen = 0;
  1173. int sendlen = 0;
  1174. int trycount = 3;
  1175. struct timespec p;
  1176. struct bitmain_rxstatus_data rxstatusdata;
  1177. int i = 0, j = 0, m = 0, r = 0, statusok = 0;
  1178. uint32_t checkbit = 0x00000000;
  1179. int hwerror_eft = 0;
  1180. int beeper_ctrl = 1;
  1181. int tempover_ctrl = 1;
  1182. int home_mode = 0;
  1183. struct bitmain_packet_head packethead;
  1184. int asicnum = 0;
  1185. int mod = 0,tmp = 0;
  1186. /* Send reset, then check for result */
  1187. if(!bitmain) {
  1188. applog(LOG_WARNING, "bitmain_initialize cgpu_info is null");
  1189. return -1;
  1190. }
  1191. info = bitmain->device_data;
  1192. /* clear read buf */
  1193. ret = bitmain_read(bitmain, data, BITMAIN_READBUF_SIZE,
  1194. BITMAIN_RESET_TIMEOUT);
  1195. if(ret > 0) {
  1196. if (opt_debug) {
  1197. char hex[(ret * 2) + 1];
  1198. bin2hex(hex, data, ret);
  1199. applog(LOG_DEBUG, "BTM%d Clear Read(%d): %s", bitmain->device_id, ret, hex);
  1200. }
  1201. }
  1202. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *)sendbuf, 0, 1, 0, 0);
  1203. if(sendlen <= 0) {
  1204. applog(LOG_ERR, "bitmain_initialize bitmain_set_rxstatus error(%d)", sendlen);
  1205. return -1;
  1206. }
  1207. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1208. if (unlikely(ret == BTM_SEND_ERROR)) {
  1209. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1210. return -1;
  1211. }
  1212. while(trycount >= 0) {
  1213. ret = bitmain_read(bitmain, data+readlen, BITMAIN_READBUF_SIZE, BITMAIN_RESET_TIMEOUT);
  1214. if(ret > 0) {
  1215. readlen += ret;
  1216. if(readlen > BITMAIN_READ_SIZE) {
  1217. for(i = 0; i < readlen; i++) {
  1218. if(data[i] == 0xa1) {
  1219. if (opt_debug) {
  1220. char hex[(readlen * 2) + 1];
  1221. bin2hex(hex, data, readlen);
  1222. applog(LOG_DEBUG, "%s%d initset: get: %s", bitmain->drv->name, bitmain->device_id, hex);
  1223. }
  1224. memcpy(&packethead, data+i, sizeof(struct bitmain_packet_head));
  1225. packethead.length = htole16(packethead.length);
  1226. if(packethead.length > 1130) {
  1227. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d error", packethead.length+4);
  1228. continue;
  1229. }
  1230. if(readlen-i < packethead.length+4) {
  1231. applog(LOG_ERR, "bitmain_initialize rxstatus datalen=%d<%d low", readlen-i, packethead.length+4);
  1232. continue;
  1233. }
  1234. if (bitmain_parse_rxstatus(data+i, packethead.length+4, &rxstatusdata) != 0) {
  1235. applog(LOG_ERR, "bitmain_initialize bitmain_parse_rxstatus error");
  1236. continue;
  1237. }
  1238. info->chain_num = rxstatusdata.chain_num;
  1239. info->fifo_space = rxstatusdata.fifo_space;
  1240. info->hw_version[0] = rxstatusdata.hw_version[0];
  1241. info->hw_version[1] = rxstatusdata.hw_version[1];
  1242. info->hw_version[2] = rxstatusdata.hw_version[2];
  1243. info->hw_version[3] = rxstatusdata.hw_version[3];
  1244. info->nonce_error = 0;
  1245. info->last_nonce_error = 0;
  1246. sprintf(info->g_miner_version, "%d.%d.%d.%d", info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3]);
  1247. applog(LOG_ERR, "bitmain_initialize rxstatus v(%d) chain(%d) fifo(%d) hwv1(%d) hwv2(%d) hwv3(%d) hwv4(%d) nerr(%d) freq=%d",
  1248. rxstatusdata.version, info->chain_num, info->fifo_space, info->hw_version[0], info->hw_version[1], info->hw_version[2], info->hw_version[3],
  1249. rxstatusdata.nonce_error, info->frequency);
  1250. memcpy(info->chain_asic_exist, rxstatusdata.chain_asic_exist, BITMAIN_MAX_CHAIN_NUM*32);
  1251. memcpy(info->chain_asic_status, rxstatusdata.chain_asic_status, BITMAIN_MAX_CHAIN_NUM*32);
  1252. for(i = 0; i < rxstatusdata.chain_num; i++) {
  1253. info->chain_asic_num[i] = rxstatusdata.chain_asic_num[i];
  1254. memset(info->chain_asic_status_t[i], 0, 320);
  1255. j = 0;
  1256. mod = 0;
  1257. if(info->chain_asic_num[i] <= 0) {
  1258. asicnum = 0;
  1259. } else {
  1260. mod = info->chain_asic_num[i] % 32;
  1261. if(mod == 0) {
  1262. asicnum = info->chain_asic_num[i] / 32;
  1263. } else {
  1264. asicnum = info->chain_asic_num[i] / 32 + 1;
  1265. }
  1266. }
  1267. if(asicnum > 0) {
  1268. for(m = asicnum-1; m >= 0; m--) {
  1269. tmp = mod ? (32-mod):0;
  1270. for(r = tmp;r < 32;r++){
  1271. if((r-tmp)%8 == 0 && (r-tmp) !=0){
  1272. info->chain_asic_status_t[i][j] = ' ';
  1273. j++;
  1274. }
  1275. checkbit = num2bit(r);
  1276. if(rxstatusdata.chain_asic_exist[i*8+m] & checkbit) {
  1277. if(rxstatusdata.chain_asic_status[i*8+m] & checkbit) {
  1278. info->chain_asic_status_t[i][j] = 'o';
  1279. } else {
  1280. info->chain_asic_status_t[i][j] = 'x';
  1281. }
  1282. } else {
  1283. info->chain_asic_status_t[i][j] = '-';
  1284. }
  1285. j++;
  1286. }
  1287. info->chain_asic_status_t[i][j] = ' ';
  1288. j++;
  1289. mod = 0;
  1290. }
  1291. }
  1292. applog(LOG_DEBUG, "bitmain_initialize chain(%d) asic_num=%d asic_exist=%08x%08x%08x%08x%08x%08x%08x%08x asic_status=%08x%08x%08x%08x%08x%08x%08x%08x",
  1293. i, info->chain_asic_num[i],
  1294. info->chain_asic_exist[i*8+0], info->chain_asic_exist[i*8+1], info->chain_asic_exist[i*8+2], info->chain_asic_exist[i*8+3], info->chain_asic_exist[i*8+4], info->chain_asic_exist[i*8+5], info->chain_asic_exist[i*8+6], info->chain_asic_exist[i*8+7],
  1295. info->chain_asic_status[i*8+0], info->chain_asic_status[i*8+1], info->chain_asic_status[i*8+2], info->chain_asic_status[i*8+3], info->chain_asic_status[i*8+4], info->chain_asic_status[i*8+5], info->chain_asic_status[i*8+6], info->chain_asic_status[i*8+7]);
  1296. applog(LOG_ERR, "bitmain_initialize chain(%d) asic_num=%d asic_status=%s", i, info->chain_asic_num[i], info->chain_asic_status_t[i]);
  1297. }
  1298. bitmain_update_temps(bitmain, info, &rxstatusdata);
  1299. statusok = 1;
  1300. break;
  1301. }
  1302. }
  1303. if(statusok) {
  1304. break;
  1305. }
  1306. }
  1307. }
  1308. trycount--;
  1309. p.tv_sec = 0;
  1310. p.tv_nsec = BITMAIN_RESET_PITCH;
  1311. nanosleep(&p, NULL);
  1312. }
  1313. p.tv_sec = 0;
  1314. p.tv_nsec = BITMAIN_RESET_PITCH;
  1315. nanosleep(&p, NULL);
  1316. cgtime(&info->last_status_time);
  1317. if(statusok) {
  1318. applog(LOG_ERR, "bitmain_initialize start send txconfig");
  1319. if(opt_bitmain_hwerror)
  1320. hwerror_eft = 1;
  1321. else
  1322. hwerror_eft = 0;
  1323. if(opt_bitmain_nobeeper)
  1324. beeper_ctrl = 0;
  1325. else
  1326. beeper_ctrl = 1;
  1327. if(opt_bitmain_notempoverctrl)
  1328. tempover_ctrl = 0;
  1329. else
  1330. tempover_ctrl = 1;
  1331. if(opt_bitmain_homemode)
  1332. home_mode= 1;
  1333. else
  1334. home_mode= 0;
  1335. sendlen = bitmain_set_txconfig((struct bitmain_txconfig_token *)sendbuf, 1, 1, 1, 1, 1, 0, 1, hwerror_eft, beeper_ctrl, tempover_ctrl,home_mode,
  1336. info->chain_num, info->asic_num, BITMAIN_DEFAULT_FAN_MAX_PWM, info->timeout,
  1337. info->frequency, info->voltage, 0, 0, 0x04, info->reg_data);
  1338. if(sendlen <= 0) {
  1339. applog(LOG_ERR, "bitmain_initialize bitmain_set_txconfig error(%d)", sendlen);
  1340. return -1;
  1341. }
  1342. ret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1343. if (unlikely(ret == BTM_SEND_ERROR)) {
  1344. applog(LOG_ERR, "bitmain_initialize bitmain_send_data error");
  1345. return -1;
  1346. }
  1347. applog(LOG_WARNING, "BMM%d: InitSet succeeded", bitmain->device_id);
  1348. } else {
  1349. applog(LOG_WARNING, "BMS%d: InitSet error", bitmain->device_id);
  1350. return -1;
  1351. }
  1352. return 0;
  1353. }
  1354. static bool bitmain_detect_one(const char * devpath)
  1355. {
  1356. struct bitmain_info *info;
  1357. struct cgpu_info *bitmain;
  1358. int ret;
  1359. bitmain = btm_alloc_cgpu(&bitmain_drv, BITMAIN_MINER_THREADS);
  1360. info = bitmain->device_data;
  1361. drv_set_defaults(&bitmain_drv, bitmain_set_device_funcs_init, info, devpath, NULL, 1);
  1362. if (!btm_init(bitmain, devpath))
  1363. goto shin;
  1364. applog(LOG_ERR, "bitmain_detect_one btm init ok");
  1365. info->fan_pwm = BITMAIN_DEFAULT_FAN_MIN_PWM;
  1366. info->temp_max = 0;
  1367. /* This is for check the temp/fan every 3~4s */
  1368. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  1369. if (info->temp_history_count <= 0)
  1370. info->temp_history_count = 1;
  1371. info->temp_history_index = 0;
  1372. info->temp_sum = 0;
  1373. info->temp_old = 0;
  1374. if (!add_cgpu(bitmain))
  1375. goto unshin;
  1376. ret = bitmain_initialize(bitmain);
  1377. applog(LOG_ERR, "bitmain_detect_one stop bitmain_initialize %d", ret);
  1378. if (ret)
  1379. goto unshin;
  1380. info->errorcount = 0;
  1381. applog(LOG_ERR, "BitMain Detected: %s "
  1382. "(chain_num=%d asic_num=%d timeout=%d freq=%d-%s volt=%02x%02x-%s)",
  1383. bitmain->device_path, info->chain_num, info->asic_num, info->timeout,
  1384. info->frequency, info->frequency_t, info->voltage[0], info->voltage[1], info->voltage_t);
  1385. return true;
  1386. unshin:
  1387. btm_uninit(bitmain);
  1388. shin:
  1389. free(bitmain->device_data);
  1390. bitmain->device_data = NULL;
  1391. free(bitmain);
  1392. return false;
  1393. }
  1394. static int bitmain_detect_auto(void)
  1395. {
  1396. const char * const auto_bitmain_dev = "/dev/bitmain-asic";
  1397. applog(LOG_DEBUG, "BTM detect dev: %s", auto_bitmain_dev);
  1398. return bitmain_detect_one(auto_bitmain_dev) ? 1 : 0;
  1399. }
  1400. static void bitmain_detect()
  1401. {
  1402. generic_detect(&bitmain_drv, bitmain_detect_one, bitmain_detect_auto, GDF_REQUIRE_DNAME | GDF_DEFAULT_NOAUTO);
  1403. }
  1404. static void do_bitmain_close(struct thr_info *thr)
  1405. {
  1406. struct cgpu_info *bitmain = thr->cgpu;
  1407. struct bitmain_info *info = bitmain->device_data;
  1408. pthread_join(info->read_thr, NULL);
  1409. bitmain_running_reset(bitmain, info);
  1410. info->no_matching_work = 0;
  1411. }
  1412. /* We use a replacement algorithm to only remove references to work done from
  1413. * the buffer when we need the extra space for new work. */
  1414. static bool bitmain_fill(struct cgpu_info *bitmain)
  1415. {
  1416. struct bitmain_info *info = bitmain->device_data;
  1417. int subid, slot;
  1418. struct work *work;
  1419. bool ret = true;
  1420. int sendret = 0, sendcount = 0, neednum = 0, queuednum = 0, sendnum = 0, sendlen = 0;
  1421. uint8_t sendbuf[BITMAIN_SENDBUF_SIZE];
  1422. int senderror = 0;
  1423. struct timeval now;
  1424. int timediff = 0;
  1425. //applog(LOG_DEBUG, "BTM bitmain_fill start--------");
  1426. mutex_lock(&info->qlock);
  1427. if(info->fifo_space <= 0) {
  1428. //applog(LOG_DEBUG, "BTM bitmain_fill fifo space empty--------");
  1429. ret = true;
  1430. goto out_unlock;
  1431. }
  1432. if (bitmain->queued >= BITMAIN_MAX_WORK_QUEUE_NUM) {
  1433. ret = true;
  1434. } else {
  1435. ret = false;
  1436. }
  1437. while(info->fifo_space > 0) {
  1438. neednum = info->fifo_space<BITMAIN_MAX_WORK_NUM?info->fifo_space:BITMAIN_MAX_WORK_NUM;
  1439. queuednum = bitmain->queued;
  1440. applog(LOG_DEBUG, "BTM: Work task queued(%d) fifo space(%d) needsend(%d)", queuednum, info->fifo_space, neednum);
  1441. if(queuednum < neednum) {
  1442. while(true) {
  1443. work = get_queued(bitmain);
  1444. if (unlikely(!work)) {
  1445. break;
  1446. } else {
  1447. applog(LOG_DEBUG, "BTM get work queued number:%d neednum:%d", queuednum, neednum);
  1448. subid = bitmain->queued++;
  1449. work->subid = subid;
  1450. slot = bitmain->work_array + subid;
  1451. if (slot > BITMAIN_ARRAY_SIZE) {
  1452. applog(LOG_DEBUG, "bitmain_fill array cyc %d", BITMAIN_ARRAY_SIZE);
  1453. slot = 0;
  1454. }
  1455. if (likely(bitmain->works[slot])) {
  1456. applog(LOG_DEBUG, "bitmain_fill work_completed %d", slot);
  1457. work_completed(bitmain, bitmain->works[slot]);
  1458. }
  1459. bitmain->works[slot] = work;
  1460. queuednum++;
  1461. if(queuednum >= neednum) {
  1462. break;
  1463. }
  1464. }
  1465. }
  1466. }
  1467. if(queuednum < BITMAIN_MAX_DEAL_QUEUE_NUM) {
  1468. if(queuednum < neednum) {
  1469. applog(LOG_DEBUG, "BTM: No enough work to send, queue num=%d", queuednum);
  1470. break;
  1471. }
  1472. }
  1473. sendnum = queuednum < neednum ? queuednum : neednum;
  1474. sendlen = bitmain_set_txtask(sendbuf, &(info->last_work_block), bitmain->works, BITMAIN_ARRAY_SIZE, bitmain->work_array, sendnum, &sendcount);
  1475. bitmain->queued -= sendnum;
  1476. info->send_full_space += sendnum;
  1477. if (bitmain->queued < 0)
  1478. bitmain->queued = 0;
  1479. if (bitmain->work_array + sendnum > BITMAIN_ARRAY_SIZE) {
  1480. bitmain->work_array = bitmain->work_array + sendnum-BITMAIN_ARRAY_SIZE;
  1481. } else {
  1482. bitmain->work_array += sendnum;
  1483. }
  1484. applog(LOG_DEBUG, "BTM: Send work array %d", bitmain->work_array);
  1485. if (sendlen > 0) {
  1486. info->fifo_space -= sendcount;
  1487. if (info->fifo_space < 0)
  1488. info->fifo_space = 0;
  1489. sendret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1490. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1491. applog(LOG_ERR, "BTM%i: Comms error(buffer)", bitmain->device_id);
  1492. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1493. info->reset = true;
  1494. info->errorcount++;
  1495. senderror = 1;
  1496. if (info->errorcount > 1000) {
  1497. info->errorcount = 0;
  1498. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread", bitmain->drv->name, bitmain->device_id);
  1499. bitmain->shutdown = true;
  1500. }
  1501. break;
  1502. } else {
  1503. applog(LOG_DEBUG, "bitmain_send_data send ret=%d", sendret);
  1504. info->errorcount = 0;
  1505. }
  1506. } else {
  1507. applog(LOG_DEBUG, "BTM: Send work bitmain_set_txtask error: %d", sendlen);
  1508. break;
  1509. }
  1510. }
  1511. out_unlock:
  1512. cgtime(&now);
  1513. timediff = now.tv_sec - info->last_status_time.tv_sec;
  1514. if(timediff < 0) timediff = -timediff;
  1515. if (timediff > BITMAIN_SEND_STATUS_TIME) {
  1516. applog(LOG_DEBUG, "BTM: Send RX Status Token fifo_space(%d) timediff(%d)", info->fifo_space, timediff);
  1517. copy_time(&(info->last_status_time), &now);
  1518. sendlen = bitmain_set_rxstatus((struct bitmain_rxstatus_token *) sendbuf, 0, 0, 0, 0);
  1519. if (sendlen > 0) {
  1520. sendret = bitmain_send_data(sendbuf, sendlen, bitmain);
  1521. if (unlikely(sendret == BTM_SEND_ERROR)) {
  1522. applog(LOG_ERR, "BTM%i: Comms error(buffer)", bitmain->device_id);
  1523. //dev_error(bitmain, REASON_DEV_COMMS_ERROR);
  1524. info->reset = true;
  1525. info->errorcount++;
  1526. senderror = 1;
  1527. if (info->errorcount > 1000) {
  1528. info->errorcount = 0;
  1529. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread", bitmain->drv->name, bitmain->device_id);
  1530. bitmain->shutdown = true;
  1531. }
  1532. } else {
  1533. info->errorcount = 0;
  1534. if (info->fifo_space <= 0) {
  1535. senderror = 1;
  1536. }
  1537. }
  1538. }
  1539. }
  1540. if(info->send_full_space > BITMAIN_SEND_FULL_SPACE) {
  1541. info->send_full_space = 0;
  1542. ret = true;
  1543. cgsleep_ms(1);
  1544. }
  1545. mutex_unlock(&info->qlock);
  1546. if(senderror) {
  1547. ret = true;
  1548. applog(LOG_DEBUG, "bitmain_fill send task sleep");
  1549. //cgsleep_ms(1);
  1550. }
  1551. return ret;
  1552. }
  1553. static int64_t bitmain_scanhash(struct thr_info *thr)
  1554. {
  1555. struct cgpu_info *bitmain = thr->cgpu;
  1556. struct bitmain_info *info = bitmain->device_data;
  1557. const int chain_num = info->chain_num;
  1558. int64_t hash_count;
  1559. //applog(LOG_DEBUG, "bitmain_scanhash info->qlock start");
  1560. mutex_lock(&info->qlock);
  1561. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1562. bitmain->results += info->nonces + info->idle;
  1563. if (bitmain->results > chain_num)
  1564. bitmain->results = chain_num;
  1565. if (!info->reset)
  1566. bitmain->results--;
  1567. info->nonces = info->idle = 0;
  1568. mutex_unlock(&info->qlock);
  1569. //applog(LOG_DEBUG, "bitmain_scanhash info->qlock stop");
  1570. /* Check for nothing but consecutive bad results or consistently less
  1571. * results than we should be getting and reset the FPGA if necessary */
  1572. //if (bitmain->results < -chain_num && !info->reset) {
  1573. // applog(LOG_ERR, "BTM%d: Result return rate low, resetting!",
  1574. // bitmain->device_id);
  1575. // info->reset = true;
  1576. //}
  1577. /* This hashmeter is just a utility counter based on returned shares */
  1578. return hash_count;
  1579. }
  1580. static void bitmain_flush_work(struct cgpu_info *bitmain)
  1581. {
  1582. struct bitmain_info *info = bitmain->device_data;
  1583. mutex_lock(&info->qlock);
  1584. /* Will overwrite any work queued */
  1585. applog(LOG_ERR, "bitmain_flush_work queued=%d array=%d", bitmain->queued, bitmain->work_array);
  1586. if(bitmain->queued > 0) {
  1587. if (bitmain->work_array + bitmain->queued > BITMAIN_ARRAY_SIZE) {
  1588. bitmain->work_array = bitmain->work_array + bitmain->queued-BITMAIN_ARRAY_SIZE;
  1589. } else {
  1590. bitmain->work_array += bitmain->queued;
  1591. }
  1592. }
  1593. bitmain->queued = 0;
  1594. //bitmain->work_array = 0;
  1595. //for (int i = 0; i < BITMAIN_ARRAY_SIZE; ++i) {
  1596. // bitmain->works[i] = NULL;
  1597. //}
  1598. //pthread_cond_signal(&info->qcond);
  1599. mutex_unlock(&info->qlock);
  1600. }
  1601. static struct api_data *bitmain_api_stats(struct cgpu_info *cgpu)
  1602. {
  1603. struct api_data *root = NULL;
  1604. struct bitmain_info *info = cgpu->device_data;
  1605. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1606. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1607. root = api_add_int(root, "baud", &(info->baud), false);
  1608. root = api_add_int(root, "miner_count", &(info->chain_num), false);
  1609. root = api_add_int(root, "asic_count", &(info->asic_num), false);
  1610. root = api_add_int(root, "timeout", &(info->timeout), false);
  1611. root = api_add_string(root, "frequency", info->frequency_t, false);
  1612. root = api_add_string(root, "voltage", info->voltage_t, false);
  1613. root = api_add_int(root, "hwv1", &(info->hw_version[0]), false);
  1614. root = api_add_int(root, "hwv2", &(info->hw_version[1]), false);
  1615. root = api_add_int(root, "hwv3", &(info->hw_version[2]), false);
  1616. root = api_add_int(root, "hwv4", &(info->hw_version[3]), false);
  1617. root = api_add_int(root, "fan_num", &(info->fan_num), false);
  1618. root = api_add_int(root, "fan1", &(info->fan[0]), false);
  1619. root = api_add_int(root, "fan2", &(info->fan[1]), false);
  1620. root = api_add_int(root, "fan3", &(info->fan[2]), false);
  1621. root = api_add_int(root, "fan4", &(info->fan[3]), false);
  1622. root = api_add_int(root, "fan5", &(info->fan[4]), false);
  1623. root = api_add_int(root, "fan6", &(info->fan[5]), false);
  1624. root = api_add_int(root, "fan7", &(info->fan[6]), false);
  1625. root = api_add_int(root, "fan8", &(info->fan[7]), false);
  1626. root = api_add_int(root, "fan9", &(info->fan[8]), false);
  1627. root = api_add_int(root, "fan10", &(info->fan[9]), false);
  1628. root = api_add_int(root, "fan11", &(info->fan[10]), false);
  1629. root = api_add_int(root, "fan12", &(info->fan[11]), false);
  1630. root = api_add_int(root, "fan13", &(info->fan[12]), false);
  1631. root = api_add_int(root, "fan14", &(info->fan[13]), false);
  1632. root = api_add_int(root, "fan15", &(info->fan[14]), false);
  1633. root = api_add_int(root, "fan16", &(info->fan[15]), false);
  1634. root = api_add_int(root, "temp_num", &(info->temp_num), false);
  1635. root = api_add_int(root, "temp1", &(info->temp[0]), false);
  1636. root = api_add_int(root, "temp2", &(info->temp[1]), false);
  1637. root = api_add_int(root, "temp3", &(info->temp[2]), false);
  1638. root = api_add_int(root, "temp4", &(info->temp[3]), false);
  1639. root = api_add_int(root, "temp5", &(info->temp[4]), false);
  1640. root = api_add_int(root, "temp6", &(info->temp[5]), false);
  1641. root = api_add_int(root, "temp7", &(info->temp[6]), false);
  1642. root = api_add_int(root, "temp8", &(info->temp[7]), false);
  1643. root = api_add_int(root, "temp9", &(info->temp[8]), false);
  1644. root = api_add_int(root, "temp10", &(info->temp[9]), false);
  1645. root = api_add_int(root, "temp11", &(info->temp[10]), false);
  1646. root = api_add_int(root, "temp12", &(info->temp[11]), false);
  1647. root = api_add_int(root, "temp13", &(info->temp[12]), false);
  1648. root = api_add_int(root, "temp14", &(info->temp[13]), false);
  1649. root = api_add_int(root, "temp15", &(info->temp[14]), false);
  1650. root = api_add_int(root, "temp16", &(info->temp[15]), false);
  1651. root = api_add_int(root, "temp_avg", &(info->temp_avg), false);
  1652. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1653. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1654. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1655. /*
  1656. for (int i = 0; i < info->chain_num; ++i) {
  1657. char mcw[24];
  1658. sprintf(mcw, "match_work_count%d", i + 1);
  1659. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1660. }*/
  1661. root = api_add_int(root, "chain_acn1", &(info->chain_asic_num[0]), false);
  1662. root = api_add_int(root, "chain_acn2", &(info->chain_asic_num[1]), false);
  1663. root = api_add_int(root, "chain_acn3", &(info->chain_asic_num[2]), false);
  1664. root = api_add_int(root, "chain_acn4", &(info->chain_asic_num[3]), false);
  1665. root = api_add_int(root, "chain_acn5", &(info->chain_asic_num[4]), false);
  1666. root = api_add_int(root, "chain_acn6", &(info->chain_asic_num[5]), false);
  1667. root = api_add_int(root, "chain_acn7", &(info->chain_asic_num[6]), false);
  1668. root = api_add_int(root, "chain_acn8", &(info->chain_asic_num[7]), false);
  1669. root = api_add_int(root, "chain_acn9", &(info->chain_asic_num[8]), false);
  1670. root = api_add_int(root, "chain_acn10", &(info->chain_asic_num[9]), false);
  1671. root = api_add_int(root, "chain_acn11", &(info->chain_asic_num[10]), false);
  1672. root = api_add_int(root, "chain_acn12", &(info->chain_asic_num[11]), false);
  1673. root = api_add_int(root, "chain_acn13", &(info->chain_asic_num[12]), false);
  1674. root = api_add_int(root, "chain_acn14", &(info->chain_asic_num[13]), false);
  1675. root = api_add_int(root, "chain_acn15", &(info->chain_asic_num[14]), false);
  1676. root = api_add_int(root, "chain_acn16", &(info->chain_asic_num[15]), false);
  1677. //applog(LOG_ERR, "chain asic status:%s", info->chain_asic_status_t[0]);
  1678. root = api_add_string(root, "chain_acs1", info->chain_asic_status_t[0], false);
  1679. root = api_add_string(root, "chain_acs2", info->chain_asic_status_t[1], false);
  1680. root = api_add_string(root, "chain_acs3", info->chain_asic_status_t[2], false);
  1681. root = api_add_string(root, "chain_acs4", info->chain_asic_status_t[3], false);
  1682. root = api_add_string(root, "chain_acs5", info->chain_asic_status_t[4], false);
  1683. root = api_add_string(root, "chain_acs6", info->chain_asic_status_t[5], false);
  1684. root = api_add_string(root, "chain_acs7", info->chain_asic_status_t[6], false);
  1685. root = api_add_string(root, "chain_acs8", info->chain_asic_status_t[7], false);
  1686. root = api_add_string(root, "chain_acs9", info->chain_asic_status_t[8], false);
  1687. root = api_add_string(root, "chain_acs10", info->chain_asic_status_t[9], false);
  1688. root = api_add_string(root, "chain_acs11", info->chain_asic_status_t[10], false);
  1689. root = api_add_string(root, "chain_acs12", info->chain_asic_status_t[11], false);
  1690. root = api_add_string(root, "chain_acs13", info->chain_asic_status_t[12], false);
  1691. root = api_add_string(root, "chain_acs14", info->chain_asic_status_t[13], false);
  1692. root = api_add_string(root, "chain_acs15", info->chain_asic_status_t[14], false);
  1693. root = api_add_string(root, "chain_acs16", info->chain_asic_status_t[15], false);
  1694. //root = api_add_int(root, "chain_acs1", &(info->chain_asic_status[0]), false);
  1695. //root = api_add_int(root, "chain_acs2", &(info->chain_asic_status[1]), false);
  1696. //root = api_add_int(root, "chain_acs3", &(info->chain_asic_status[2]), false);
  1697. //root = api_add_int(root, "chain_acs4", &(info->chain_asic_status[3]), false);
  1698. return root;
  1699. }
  1700. static void bitmain_shutdown(struct thr_info *thr)
  1701. {
  1702. do_bitmain_close(thr);
  1703. }
  1704. static
  1705. const char *bitmain_set_baud(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1706. {
  1707. struct bitmain_info *info = proc->device_data;
  1708. const int baud = atoi(newvalue);
  1709. if (!valid_baud(baud))
  1710. return "Invalid baud setting";
  1711. info->baud = baud;
  1712. return NULL;
  1713. }
  1714. static
  1715. const char *bitmain_set_layout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1716. {
  1717. struct bitmain_info *info = proc->device_data;
  1718. char *endptr, *next_field;
  1719. const long int n_chains = strtol(newvalue, &endptr, 0);
  1720. if (endptr == newvalue || n_chains < 1)
  1721. return "Missing chain count";
  1722. long int n_asics = 0;
  1723. if (endptr[0] == ':' || endptr[1] == ',')
  1724. {
  1725. next_field = &endptr[1];
  1726. n_asics = strtol(next_field, &endptr, 0);
  1727. }
  1728. if (n_asics < 1)
  1729. return "Missing ASIC count";
  1730. if (n_asics > BITMAIN_DEFAULT_ASIC_NUM)
  1731. return "ASIC count too high";
  1732. info->chain_num = n_chains;
  1733. info->asic_num = n_asics;
  1734. return NULL;
  1735. }
  1736. static
  1737. const char *bitmain_set_timeout(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1738. {
  1739. struct bitmain_info *info = proc->device_data;
  1740. const int timeout = atoi(newvalue);
  1741. if (timeout < 0 || timeout > 0xff)
  1742. return "Invalid timeout setting";
  1743. info->timeout = timeout;
  1744. return NULL;
  1745. }
  1746. static
  1747. const char *bitmain_set_clock(struct cgpu_info * const proc, const char * const optname, const char * const newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1748. {
  1749. struct bitmain_info *info = proc->device_data;
  1750. const int freq = atoi(newvalue);
  1751. if (freq < BITMAIN_MIN_FREQUENCY || freq > BITMAIN_MAX_FREQUENCY)
  1752. return "Invalid clock frequency";
  1753. info->frequency = freq;
  1754. sprintf(info->frequency_t, "%d", freq);
  1755. return NULL;
  1756. }
  1757. static
  1758. const char *bitmain_set_reg_data(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1759. {
  1760. struct bitmain_info *info = proc->device_data;
  1761. uint8_t reg_data[4] = {0};
  1762. if (newvalue[0] == 'x')
  1763. ++newvalue;
  1764. size_t nvlen = strlen(newvalue);
  1765. if (nvlen > (sizeof(reg_data) * 2) || !nvlen || nvlen % 2)
  1766. return "reg_data must be a hex string of 2-8 digits (1-4 bytes)";
  1767. if (!hex2bin(reg_data, newvalue, nvlen / 2))
  1768. return "Invalid reg data hex";
  1769. memcpy(info->reg_data, reg_data, sizeof(reg_data));
  1770. return NULL;
  1771. }
  1772. static
  1773. const char *bitmain_set_voltage(struct cgpu_info * const proc, const char * const optname, const char *newvalue, char * const replybuf, enum bfg_set_device_replytype * const out_success)
  1774. {
  1775. struct bitmain_info *info = proc->device_data;
  1776. uint8_t voltage_data[2] = {0};
  1777. if (newvalue[0] == 'x')
  1778. ++newvalue;
  1779. else
  1780. voltage_usage:
  1781. return "voltage must be 'x' followed by a hex string of 1-4 digits (1-2 bytes)";
  1782. size_t nvlen = strlen(newvalue);
  1783. if (nvlen > (sizeof(voltage_data) * 2) || !nvlen || nvlen % 2)
  1784. goto voltage_usage;
  1785. if (!hex2bin(voltage_data, newvalue, nvlen / 2))
  1786. return "Invalid voltage data hex";
  1787. memcpy(info->voltage, voltage_data, sizeof(voltage_data));
  1788. bin2hex(info->voltage_t, voltage_data, 2);
  1789. info->voltage_t[5] = 0;
  1790. info->voltage_t[4] = info->voltage_t[3];
  1791. info->voltage_t[3] = info->voltage_t[2];
  1792. info->voltage_t[2] = info->voltage_t[1];
  1793. info->voltage_t[1] = '.';
  1794. return NULL;
  1795. }
  1796. static const struct bfg_set_device_definition bitmain_set_device_funcs_init[] = {
  1797. {"baud", bitmain_set_baud, "serial baud rate"},
  1798. {"layout", bitmain_set_layout, "number of chains ':' number of ASICs per chain (eg: 32:8)"},
  1799. {"timeout", bitmain_set_timeout, "timeout"},
  1800. {"clock", bitmain_set_clock, "clock frequency"},
  1801. {"reg_data", bitmain_set_reg_data, "reg_data (eg: x0d82)"},
  1802. {"voltage", bitmain_set_voltage, "voltage (must be specified as 'x' and hex data; eg: x0725)"},
  1803. {NULL},
  1804. };
  1805. struct device_drv bitmain_drv = {
  1806. .dname = "bitmain",
  1807. .name = "BTM",
  1808. .drv_detect = bitmain_detect,
  1809. .thread_prepare = bitmain_prepare,
  1810. .minerloop = hash_queued_work,
  1811. .queue_full = bitmain_fill,
  1812. .scanwork = bitmain_scanhash,
  1813. .flush_work = bitmain_flush_work,
  1814. .get_api_stats = bitmain_api_stats,
  1815. .reinit_device = bitmain_init,
  1816. .thread_shutdown = bitmain_shutdown,
  1817. };