driver-avalon.c 22 KB

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  1. /*
  2. * Copyright 2013 Xiangfu
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int option_offset = -1;
  34. struct avalon_info **avalon_info;
  35. struct device_api avalon_api;
  36. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  37. uint8_t reset, uint8_t ff, uint8_t fan,
  38. uint8_t timeout_p, uint8_t asic_num_p,
  39. uint8_t miner_num_p, uint8_t nonce_elf_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (unlikely(!at))
  48. return -1;
  49. if (unlikely(!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0)))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (likely(thr)) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (unlikely(reset)) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (unlikely(first && !at->reset)) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = nonce_elf_p;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at,
  89. struct thr_info *thr)
  90. {
  91. size_t ret;
  92. int full;
  93. struct timespec p;
  94. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  95. size_t nr_len;
  96. struct cgpu_info *avalon;
  97. struct avalon_info *info;
  98. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  99. uint32_t nonce_range;
  100. int i;
  101. if (at->nonce_elf)
  102. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  103. else
  104. nr_len = AVALON_WRITE_SIZE;
  105. memcpy(buf, at, AVALON_WRITE_SIZE);
  106. if (at->nonce_elf) {
  107. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  108. for (i = 0; i < at->asic_num; i++) {
  109. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  110. (i * nonce_range & 0xff000000) >> 24;
  111. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  112. (i * nonce_range & 0x00ff0000) >> 16;
  113. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  114. (i * nonce_range & 0x0000ff00) >> 8;
  115. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  116. (i * nonce_range & 0x000000ff) >> 0;
  117. }
  118. }
  119. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  120. uint8_t tt = 0;
  121. tt = (buf[0] & 0x0f) << 4;
  122. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  123. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  124. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  125. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  126. buf[0] = tt;
  127. buf[4] = rev8(buf[4]);
  128. #endif
  129. if (opt_debug) {
  130. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  131. hexdump((uint8_t *)buf, nr_len);
  132. }
  133. ret = write(fd, buf, nr_len);
  134. if (unlikely(ret != nr_len))
  135. return AVA_SEND_ERROR;
  136. if (likely(thr)) {
  137. avalon = thr->cgpu;
  138. info = avalon_info[avalon->device_id];
  139. delay = nr_len * 10 * 1000000000ULL;
  140. delay = delay / info->baud;
  141. }
  142. p.tv_sec = 0;
  143. p.tv_nsec = (long)delay + 4000000;
  144. nanosleep(&p, NULL);
  145. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  146. full = avalon_buffer_full(fd);
  147. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  148. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  149. if (unlikely(full == AVA_BUFFER_FULL))
  150. return AVA_SEND_BUFFER_FULL;
  151. return AVA_SEND_BUFFER_EMPTY;
  152. }
  153. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  154. struct thr_info *thr, struct timeval *tv_finish)
  155. {
  156. ssize_t ret = 0;
  157. int rc = 0;
  158. int read_amount = AVALON_READ_SIZE;
  159. bool first = true;
  160. /* Read reply 1 byte at a time to get earliest tv_finish */
  161. while (true) {
  162. ret = read(fd, buf, 1);
  163. if (ret < 0)
  164. return AVA_GETS_ERROR;
  165. if (first && tv_finish != NULL)
  166. gettimeofday(tv_finish, NULL);
  167. if (ret >= read_amount)
  168. return AVA_GETS_OK;
  169. if (ret > 0) {
  170. buf += ret;
  171. read_amount -= ret;
  172. first = false;
  173. continue;
  174. }
  175. rc++;
  176. if (rc >= read_count) {
  177. if (opt_debug) {
  178. applog(LOG_ERR,
  179. "Avalon: No data in %.2f seconds",
  180. (float)rc/(float)TIME_FACTOR);
  181. }
  182. return AVA_GETS_TIMEOUT;
  183. }
  184. if (thr && thr->work_restart) {
  185. if (opt_debug) {
  186. applog(LOG_ERR,
  187. "Avalon: Work restart at %.2f seconds",
  188. (float)(rc)/(float)TIME_FACTOR);
  189. }
  190. return AVA_GETS_RESTART;
  191. }
  192. }
  193. }
  194. static int avalon_get_result(int fd, struct avalon_result *ar,
  195. struct thr_info *thr, struct timeval *tv_finish)
  196. {
  197. struct cgpu_info *avalon;
  198. struct avalon_info *info;
  199. uint8_t result[AVALON_READ_SIZE];
  200. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  201. if (likely(thr)) {
  202. avalon = thr->cgpu;
  203. info = avalon_info[avalon->device_id];
  204. read_count = info->read_count;
  205. }
  206. memset(result, 0, AVALON_READ_SIZE);
  207. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  208. if (ret == AVA_GETS_OK) {
  209. if (opt_debug) {
  210. applog(LOG_DEBUG, "Avalon: get:");
  211. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  212. }
  213. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  214. }
  215. return ret;
  216. }
  217. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  218. struct avalon_result *ar, uint32_t *nonce)
  219. {
  220. struct cgpu_info *avalon;
  221. struct avalon_info *info;
  222. int avalon_get_work_count, i;
  223. if (unlikely(!work))
  224. return -1;
  225. avalon = thr->cgpu;
  226. info = avalon_info[avalon->device_id];
  227. avalon_get_work_count = info->miner_count;
  228. for (i = 0; i < avalon_get_work_count; i++) {
  229. if (work[i] &&
  230. !memcmp(ar->data, work[i]->data + 64, 12) &&
  231. !memcmp(ar->midstate, work[i]->midstate, 32))
  232. break;
  233. }
  234. if (i == avalon_get_work_count)
  235. return -1;
  236. ++info->matching_work[i];
  237. *nonce = ar->nonce;
  238. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  239. *nonce = swab32(*nonce);
  240. #endif
  241. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  242. info->matching_work[i]);
  243. return i;
  244. }
  245. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  246. uint8_t miner_num_p, struct avalon_result *ar)
  247. {
  248. struct avalon_task at;
  249. uint8_t *buf;
  250. int ret, i = 0;
  251. struct timespec p;
  252. avalon_init_task(NULL,
  253. &at, 1, 0,
  254. AVALON_DEFAULT_FAN_PWM,
  255. timeout_p, asic_num_p, miner_num_p, 1);
  256. ret = avalon_send_task(fd, &at, NULL);
  257. if (ret == AVA_SEND_ERROR)
  258. return 1;
  259. avalon_get_result(fd, ar, NULL, NULL);
  260. buf = (uint8_t *)ar;
  261. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  262. buf[2] == 0xAA && buf[3] == 0x55) {
  263. for (i = 4; i < 11; i++)
  264. if (buf[i] != 0)
  265. break;
  266. }
  267. if (i != 11) {
  268. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  269. " (%d: %02x %02x %02x %02x)",
  270. i, buf[0], buf[1], buf[2], buf[3]);
  271. /* FIXME: return 1; */
  272. }
  273. p.tv_sec = 1;
  274. p.tv_nsec = AVALON_RESET_PITCH;
  275. nanosleep(&p, NULL);
  276. applog(LOG_ERR,
  277. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  278. "Temp1: %d, Temp2: %d, Temp3: %d",
  279. ar->fan0, ar->fan1, ar->fan2, ar->temp0, ar->temp1, ar->temp2);
  280. applog(LOG_ERR, "Avalon: Reset succeeded");
  281. return 0;
  282. }
  283. static void set_timing_mode(struct cgpu_info *avalon, struct avalon_result *ar)
  284. {
  285. struct avalon_info *info = avalon_info[avalon->device_id];
  286. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  287. TIME_FACTOR) / (float)info->miner_count;
  288. info->fan0 = ar->fan0;
  289. info->fan1 = ar->fan1;
  290. info->fan2 = ar->fan2;
  291. info->temp0 = ar->temp0;
  292. info->temp1 = ar->temp1;
  293. info->temp2 = ar->temp2;
  294. if (info->temp0 > info->temp_max)
  295. info->temp_max = info->temp0;
  296. if (info->temp1 > info->temp_max)
  297. info->temp_max = info->temp1;
  298. if (info->temp2 > info->temp_max)
  299. info->temp_max = info->temp2;
  300. }
  301. static void get_options(int this_option_offset, int *baud, int *miner_count,
  302. int *asic_count, int *timeout)
  303. {
  304. char err_buf[BUFSIZ+1];
  305. char buf[BUFSIZ+1];
  306. char *ptr, *comma, *colon, *colon2, *colon3;
  307. size_t max;
  308. int i, tmp;
  309. if (opt_avalon_options == NULL)
  310. buf[0] = '\0';
  311. else {
  312. ptr = opt_avalon_options;
  313. for (i = 0; i < this_option_offset; i++) {
  314. comma = strchr(ptr, ',');
  315. if (comma == NULL)
  316. break;
  317. ptr = comma + 1;
  318. }
  319. comma = strchr(ptr, ',');
  320. if (comma == NULL)
  321. max = strlen(ptr);
  322. else
  323. max = comma - ptr;
  324. if (max > BUFSIZ)
  325. max = BUFSIZ;
  326. strncpy(buf, ptr, max);
  327. buf[max] = '\0';
  328. }
  329. *baud = AVALON_IO_SPEED;
  330. *miner_count = AVALON_DEFAULT_MINER_NUM;
  331. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  332. *timeout = AVALON_DEFAULT_TIMEOUT;
  333. if (!(*buf))
  334. return;
  335. colon = strchr(buf, ':');
  336. if (colon)
  337. *(colon++) = '\0';
  338. tmp = atoi(buf);
  339. switch (tmp) {
  340. case 115200:
  341. *baud = 115200;
  342. break;
  343. case 57600:
  344. *baud = 57600;
  345. break;
  346. case 38400:
  347. *baud = 38400;
  348. break;
  349. case 19200:
  350. *baud = 19200;
  351. break;
  352. default:
  353. sprintf(err_buf,
  354. "Invalid avalon-options for baud (%s) "
  355. "must be 115200, 57600, 38400 or 19200", buf);
  356. quit(1, err_buf);
  357. }
  358. if (colon && *colon) {
  359. colon2 = strchr(colon, ':');
  360. if (colon2)
  361. *(colon2++) = '\0';
  362. if (*colon) {
  363. tmp = atoi(colon);
  364. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  365. *miner_count = tmp;
  366. } else {
  367. sprintf(err_buf,
  368. "Invalid avalon-options for "
  369. "miner_count (%s) must be 1 ~ %d",
  370. colon, AVALON_DEFAULT_MINER_NUM);
  371. quit(1, err_buf);
  372. }
  373. }
  374. if (colon2 && *colon2) {
  375. colon3 = strchr(colon2, ':');
  376. if (colon3)
  377. *(colon3++) = '\0';
  378. tmp = atoi(colon2);
  379. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  380. *asic_count = tmp;
  381. else {
  382. sprintf(err_buf,
  383. "Invalid avalon-options for "
  384. "asic_count (%s) must be 1 ~ %d",
  385. colon2, AVALON_DEFAULT_ASIC_NUM);
  386. quit(1, err_buf);
  387. }
  388. if (colon3 && *colon3) {
  389. tmp = atoi(colon3);
  390. if (tmp > 0 && tmp <= 0xff)
  391. *timeout = tmp;
  392. else {
  393. sprintf(err_buf,
  394. "Invalid avalon-options for "
  395. "timeout (%s) must be 1 ~ %d",
  396. colon3, 0xff);
  397. quit(1, err_buf);
  398. }
  399. }
  400. }
  401. }
  402. }
  403. static bool avalon_detect_one(const char *devpath)
  404. {
  405. struct avalon_info *info;
  406. struct avalon_result ar;
  407. int fd, ret;
  408. int baud, miner_count, asic_count, timeout;
  409. int this_option_offset = ++option_offset;
  410. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  411. &timeout);
  412. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  413. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  414. devpath, baud, miner_count, asic_count, timeout);
  415. fd = avalon_open2(devpath, baud, true);
  416. if (unlikely(fd == -1)) {
  417. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  418. return false;
  419. }
  420. ret = avalon_reset(fd, timeout, asic_count, miner_count, &ar);
  421. avalon_close(fd);
  422. if (ret) {
  423. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  424. }
  425. /* We have a real Avalon! */
  426. struct cgpu_info *avalon;
  427. avalon = calloc(1, sizeof(struct cgpu_info));
  428. avalon->api = &avalon_api;
  429. avalon->device_path = strdup(devpath);
  430. avalon->device_fd = -1;
  431. avalon->threads = AVALON_MINER_THREADS;
  432. add_cgpu(avalon);
  433. avalon_info = realloc(avalon_info,
  434. sizeof(struct avalon_info *) *
  435. (total_devices + 1));
  436. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  437. devpath, avalon->device_id);
  438. avalon_info[avalon->device_id] = (struct avalon_info *)
  439. malloc(sizeof(struct avalon_info));
  440. if (unlikely(!(avalon_info[avalon->device_id])))
  441. quit(1, "Failed to malloc avalon_info");
  442. info = avalon_info[avalon->device_id];
  443. memset(info, 0, sizeof(struct avalon_info));
  444. info->baud = baud;
  445. info->miner_count = miner_count;
  446. info->asic_count = asic_count;
  447. info->timeout = timeout;
  448. set_timing_mode(avalon, &ar);
  449. return true;
  450. }
  451. static inline void avalon_detect()
  452. {
  453. serial_detect(&avalon_api, avalon_detect_one);
  454. }
  455. static bool avalon_prepare(struct thr_info *thr)
  456. {
  457. struct avalon_result ar;
  458. struct cgpu_info *avalon = thr->cgpu;
  459. struct timeval now;
  460. int fd, ret;
  461. struct avalon_info *info = avalon_info[avalon->device_id];
  462. avalon->device_fd = -1;
  463. fd = avalon_open(avalon->device_path,
  464. avalon_info[avalon->device_id]->baud);
  465. if (unlikely(fd == -1)) {
  466. applog(LOG_ERR, "Avalon: Failed to open on %s",
  467. avalon->device_path);
  468. return false;
  469. }
  470. ret = avalon_reset(fd, info->timeout, info->asic_count,
  471. info->miner_count, &ar);
  472. if (ret)
  473. return false;
  474. avalon->device_fd = fd;
  475. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  476. gettimeofday(&now, NULL);
  477. get_datestamp(avalon->init, &now);
  478. return true;
  479. }
  480. static void avalon_free_work(struct thr_info *thr, struct work **work)
  481. {
  482. struct cgpu_info *avalon;
  483. struct avalon_info *info;
  484. int i;
  485. if (unlikely(!work))
  486. return;
  487. avalon = thr->cgpu;
  488. info = avalon_info[avalon->device_id];
  489. for (i = 0; i < info->miner_count; i++)
  490. if (likely(work[i])) {
  491. free_work(work[i]);
  492. work[i] = NULL;
  493. }
  494. }
  495. static void do_avalon_close(struct thr_info *thr)
  496. {
  497. struct cgpu_info *avalon = thr->cgpu;
  498. struct avalon_info *info = avalon_info[avalon->device_id];
  499. avalon_close(avalon->device_fd);
  500. avalon->device_fd = -1;
  501. info->no_matching_work = 0;
  502. avalon_free_work(thr, info->bulk0);
  503. avalon_free_work(thr, info->bulk1);
  504. avalon_free_work(thr, info->bulk2);
  505. }
  506. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  507. __maybe_unused int64_t max_nonce)
  508. {
  509. struct cgpu_info *avalon;
  510. int fd, ret, full;
  511. struct avalon_info *info;
  512. struct avalon_task at;
  513. struct avalon_result ar;
  514. int i, work_i0, work_i1, work_i2;
  515. int avalon_get_work_count;
  516. struct timeval tv_start, tv_finish, elapsed;
  517. uint32_t nonce;
  518. int64_t hash_count;
  519. avalon = thr->cgpu;
  520. info = avalon_info[avalon->device_id];
  521. avalon_get_work_count = info->miner_count;
  522. if (unlikely(avalon->device_fd == -1))
  523. if (!avalon_prepare(thr)) {
  524. applog(LOG_ERR, "AVA%i: Comms error",
  525. avalon->device_id);
  526. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  527. /* fail the device if the reopen attempt fails */
  528. return -1;
  529. }
  530. fd = avalon->device_fd;
  531. #ifndef WIN32
  532. tcflush(fd, TCOFLUSH);
  533. #endif
  534. for (i = 0; i < avalon_get_work_count; i++) {
  535. info->bulk0[i] = info->bulk1[i];
  536. info->bulk1[i] = info->bulk2[i];
  537. info->bulk2[i] = work[i];
  538. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  539. i, info->bulk0[i], info->bulk1[i], info->bulk2[i]);
  540. }
  541. i = 0;
  542. while (true) {
  543. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0, 1);
  544. avalon_create_task(&at, work[i]);
  545. ret = avalon_send_task(fd, &at, thr);
  546. if (unlikely(ret == AVA_SEND_ERROR ||
  547. (ret == AVA_SEND_BUFFER_EMPTY &&
  548. (i + 1 == avalon_get_work_count)))) {
  549. avalon_free_work(thr, info->bulk0);
  550. avalon_free_work(thr, info->bulk1);
  551. avalon_free_work(thr, info->bulk2);
  552. do_avalon_close(thr);
  553. applog(LOG_ERR, "AVA%i: Comms error",
  554. avalon->device_id);
  555. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  556. sleep(1);
  557. return 0; /* This should never happen */
  558. }
  559. work[i]->blk.nonce = 0xffffffff;
  560. if (ret == AVA_SEND_BUFFER_FULL)
  561. break;
  562. i++;
  563. }
  564. elapsed.tv_sec = elapsed.tv_usec = 0;
  565. gettimeofday(&tv_start, NULL);
  566. hash_count = 0;
  567. while(true) {
  568. work_i0 = work_i1 = work_i2 = -1;
  569. full = avalon_buffer_full(fd);
  570. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  571. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  572. if (unlikely(full == AVA_BUFFER_EMPTY))
  573. break;
  574. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  575. if (unlikely(ret == AVA_GETS_ERROR)) {
  576. avalon_free_work(thr, info->bulk0);
  577. avalon_free_work(thr, info->bulk1);
  578. avalon_free_work(thr, info->bulk2);
  579. do_avalon_close(thr);
  580. applog(LOG_ERR,
  581. "AVA%i: Comms error", avalon->device_id);
  582. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  583. return 0;
  584. }
  585. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  586. timersub(&tv_finish, &tv_start, &elapsed);
  587. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  588. elapsed.tv_sec, elapsed.tv_usec);
  589. continue;
  590. }
  591. if (unlikely(ret == AVA_GETS_RESTART)) {
  592. avalon_free_work(thr, info->bulk0);
  593. avalon_free_work(thr, info->bulk1);
  594. avalon_free_work(thr, info->bulk2);
  595. continue;
  596. }
  597. avalon->temp = (ar.temp0 + ar.temp1 + ar.temp2) / 3;
  598. info->fan0 = ar.fan0;
  599. info->fan1 = ar.fan1;
  600. info->fan2 = ar.fan2;
  601. info->temp0 = ar.temp0;
  602. info->temp1 = ar.temp1;
  603. info->temp2 = ar.temp2;
  604. if (info->temp0 > info->temp_max)
  605. info->temp_max = info->temp0;
  606. if (info->temp1 > info->temp_max)
  607. info->temp_max = info->temp1;
  608. if (info->temp2 > info->temp_max)
  609. info->temp_max = info->temp2;
  610. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  611. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  612. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  613. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0)) {
  614. if (opt_debug) {
  615. timersub(&tv_finish, &tv_start, &elapsed);
  616. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  617. " (%ld.%06lds)", ++info->no_matching_work,
  618. elapsed.tv_sec, elapsed.tv_usec);
  619. }
  620. continue;
  621. }
  622. if (work_i0 >= 0)
  623. submit_nonce(thr, info->bulk0[work_i0], nonce);
  624. if (work_i1 >= 0)
  625. submit_nonce(thr, info->bulk1[work_i1], nonce);
  626. if (work_i2 >= 0)
  627. submit_nonce(thr, info->bulk2[work_i2], nonce);
  628. hash_count += nonce;
  629. if (opt_debug) {
  630. timersub(&tv_finish, &tv_start, &elapsed);
  631. applog(LOG_DEBUG,
  632. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  633. "(%ld.%06lds)", nonce, hash_count,
  634. elapsed.tv_sec, elapsed.tv_usec);
  635. }
  636. }
  637. avalon_free_work(thr, info->bulk0);
  638. applog(LOG_ERR,
  639. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  640. "Temp1: %d, Temp2: %d, Temp3: %d, TempMAX: %d",
  641. info->fan0, info->fan1, info->fan2,
  642. info->temp0, info->temp1, info->temp2, info->temp_max);
  643. /*
  644. * FIXME: Each work split to 10 pieces, each piece send to a
  645. * asic(256MHs). one work can be mulit-nonce back. it is not
  646. * easy calculate correct hash on such situation. so I simplely
  647. * add each nonce to hash_count. base on Utility/m hash_count*2
  648. * give a very good result.
  649. *
  650. * Any patch will be great.
  651. */
  652. return (hash_count ? (hash_count * 2) :
  653. ((int64_t)256*1024*1024)*info->miner_count*info->asic_count);
  654. }
  655. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  656. {
  657. struct api_data *root = NULL;
  658. struct avalon_info *info = avalon_info[cgpu->device_id];
  659. root = api_add_int(root, "read_count", &(info->read_count), false);
  660. root = api_add_int(root, "baud", &(info->baud), false);
  661. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  662. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  663. root = api_add_int(root, "fan1", &(info->fan0), false);
  664. root = api_add_int(root, "fan2", &(info->fan1), false);
  665. root = api_add_int(root, "fan3", &(info->fan2), false);
  666. root = api_add_int(root, "temp1", &(info->temp0), false);
  667. root = api_add_int(root, "temp2", &(info->temp1), false);
  668. root = api_add_int(root, "temp3", &(info->temp2), false);
  669. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  670. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  671. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  672. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  673. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  674. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  675. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  676. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  677. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  678. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  679. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  680. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  681. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  682. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  683. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  684. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  685. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  686. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  687. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  688. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  689. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  690. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  691. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  692. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  693. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  694. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  695. return root;
  696. }
  697. static void avalon_shutdown(struct thr_info *thr)
  698. {
  699. do_avalon_close(thr);
  700. }
  701. struct device_api avalon_api = {
  702. .dname = "avalon",
  703. .name = "AVA",
  704. .api_detect = avalon_detect,
  705. .thread_prepare = avalon_prepare,
  706. .scanhash_queue = avalon_scanhash,
  707. .get_api_stats = avalon_api_stats,
  708. .thread_shutdown = avalon_shutdown,
  709. };