driver-avalon.c 42 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #include <time.h>
  22. #ifndef WIN32
  23. #include <sys/select.h>
  24. #include <termios.h>
  25. #include <sys/stat.h>
  26. #include <fcntl.h>
  27. #ifndef O_CLOEXEC
  28. #define O_CLOEXEC 0
  29. #endif
  30. #else
  31. #include "compat.h"
  32. #include <windows.h>
  33. #include <io.h>
  34. #endif
  35. #include "elist.h"
  36. #include "miner.h"
  37. #include "usbutils.h"
  38. #include "driver-avalon.h"
  39. #include "hexdump.c"
  40. #include "util.h"
  41. int opt_avalon_temp = AVALON_TEMP_TARGET;
  42. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  43. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  44. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  45. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  46. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  47. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  48. bool opt_avalon_auto;
  49. static int option_offset = -1;
  50. struct device_drv avalon_drv;
  51. static int avalon_init_task(struct avalon_task *at,
  52. uint8_t reset, uint8_t ff, uint8_t fan,
  53. uint8_t timeout, uint8_t asic_num,
  54. uint8_t miner_num, uint8_t nonce_elf,
  55. uint8_t gate_miner, int frequency)
  56. {
  57. uint16_t *lefreq16;
  58. uint8_t *buf;
  59. static bool first = true;
  60. if (unlikely(!at))
  61. return -1;
  62. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  63. return -1;
  64. memset(at, 0, sizeof(struct avalon_task));
  65. if (unlikely(reset)) {
  66. at->reset = 1;
  67. at->fan_eft = 1;
  68. at->timer_eft = 1;
  69. first = true;
  70. }
  71. at->flush_fifo = (ff ? 1 : 0);
  72. at->fan_eft = (fan ? 1 : 0);
  73. if (unlikely(first && !at->reset)) {
  74. at->fan_eft = 1;
  75. at->timer_eft = 1;
  76. first = false;
  77. }
  78. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  79. at->timeout_data = timeout;
  80. at->asic_num = asic_num;
  81. at->miner_num = miner_num;
  82. at->nonce_elf = nonce_elf;
  83. at->gate_miner_elf = 1;
  84. at->asic_pll = 1;
  85. if (unlikely(gate_miner)) {
  86. at-> gate_miner = 1;
  87. at->asic_pll = 0;
  88. }
  89. buf = (uint8_t *)at;
  90. buf[5] = 0x00;
  91. buf[8] = 0x74;
  92. buf[9] = 0x01;
  93. buf[10] = 0x00;
  94. buf[11] = 0x00;
  95. lefreq16 = (uint16_t *)&buf[6];
  96. *lefreq16 = htole16(frequency * 8);
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  106. {
  107. int err, amount;
  108. err = usb_write(avalon, buf, len, &amount, ep);
  109. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  110. avalon->device_id, err);
  111. if (unlikely(err != 0)) {
  112. applog(LOG_WARNING, "usb_write error on avalon_write");
  113. return AVA_SEND_ERROR;
  114. }
  115. if (amount != len) {
  116. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  117. return AVA_SEND_ERROR;
  118. }
  119. return AVA_SEND_OK;
  120. }
  121. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  122. {
  123. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  124. int delay, ret, i, ep = C_AVALON_TASK;
  125. struct avalon_info *info;
  126. cgtimer_t ts_start;
  127. uint32_t nonce_range;
  128. size_t nr_len;
  129. if (at->nonce_elf)
  130. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  131. else
  132. nr_len = AVALON_WRITE_SIZE;
  133. memcpy(buf, at, AVALON_WRITE_SIZE);
  134. if (at->nonce_elf) {
  135. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  136. for (i = 0; i < at->asic_num; i++) {
  137. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  138. (i * nonce_range & 0xff000000) >> 24;
  139. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  140. (i * nonce_range & 0x00ff0000) >> 16;
  141. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  142. (i * nonce_range & 0x0000ff00) >> 8;
  143. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  144. (i * nonce_range & 0x000000ff) >> 0;
  145. }
  146. }
  147. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  148. uint8_t tt = 0;
  149. tt = (buf[0] & 0x0f) << 4;
  150. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  151. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  152. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  153. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  154. buf[0] = tt;
  155. tt = (buf[4] & 0x0f) << 4;
  156. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  157. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  158. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  159. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  160. buf[4] = tt;
  161. #endif
  162. info = avalon->device_data;
  163. delay = nr_len * 10 * 1000000;
  164. delay = delay / info->baud;
  165. delay += 4000;
  166. if (at->reset) {
  167. ep = C_AVALON_RESET;
  168. nr_len = 1;
  169. }
  170. if (opt_debug) {
  171. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  172. hexdump(buf, nr_len);
  173. }
  174. cgsleep_prepare_r(&ts_start);
  175. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  176. cgsleep_us_r(&ts_start, delay);
  177. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  178. return ret;
  179. }
  180. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  181. struct avalon_info *info, struct avalon_result *ar,
  182. struct work *work)
  183. {
  184. uint32_t nonce;
  185. info = avalon->device_data;
  186. info->matching_work[work->subid]++;
  187. nonce = htole32(ar->nonce);
  188. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  189. return submit_nonce(thr, work, nonce);
  190. }
  191. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  192. static void wait_avalon_ready(struct cgpu_info *avalon)
  193. {
  194. while (avalon_buffer_full(avalon)) {
  195. cgsleep_ms(40);
  196. }
  197. }
  198. #define AVALON_CTS (1 << 4)
  199. static inline bool avalon_cts(char c)
  200. {
  201. return (c & AVALON_CTS);
  202. }
  203. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  204. size_t bufsize, int timeout, int ep)
  205. {
  206. size_t total = 0, readsize = bufsize + 2;
  207. char readbuf[AVALON_READBUF_SIZE];
  208. int err, amount, ofs = 2, cp;
  209. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  210. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  211. avalon->drv->name, avalon->device_id, err);
  212. if (amount < 2)
  213. goto out;
  214. /* The first 2 of every 64 bytes are status on FTDIRL */
  215. while (amount > 2) {
  216. cp = amount - 2;
  217. if (cp > 62)
  218. cp = 62;
  219. memcpy(&buf[total], &readbuf[ofs], cp);
  220. total += cp;
  221. amount -= cp + 2;
  222. ofs += 64;
  223. }
  224. out:
  225. return total;
  226. }
  227. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  228. {
  229. struct avalon_result ar;
  230. int ret, i, spare;
  231. struct avalon_task at;
  232. uint8_t *buf, *tmp;
  233. struct timespec p;
  234. /* Send reset, then check for result */
  235. avalon_init_task(&at, 1, 0,
  236. AVALON_DEFAULT_FAN_MAX_PWM,
  237. AVALON_DEFAULT_TIMEOUT,
  238. AVALON_DEFAULT_ASIC_NUM,
  239. AVALON_DEFAULT_MINER_NUM,
  240. 0, 0,
  241. AVALON_DEFAULT_FREQUENCY);
  242. wait_avalon_ready(avalon);
  243. ret = avalon_send_task(&at, avalon);
  244. if (unlikely(ret == AVA_SEND_ERROR))
  245. return -1;
  246. if (!initial) {
  247. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  248. return 0;
  249. }
  250. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  251. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  252. /* What do these sleeps do?? */
  253. p.tv_sec = 0;
  254. p.tv_nsec = AVALON_RESET_PITCH;
  255. nanosleep(&p, NULL);
  256. /* Look for the first occurrence of 0xAA, the reset response should be:
  257. * AA 55 AA 55 00 00 00 00 00 00 */
  258. spare = ret - 10;
  259. buf = tmp = (uint8_t *)&ar;
  260. if (opt_debug) {
  261. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  262. hexdump(tmp, AVALON_READ_SIZE);
  263. }
  264. for (i = 0; i <= spare; i++) {
  265. buf = &tmp[i];
  266. if (buf[0] == 0xAA)
  267. break;
  268. }
  269. i = 0;
  270. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  271. buf[2] == 0xAA && buf[3] == 0x55) {
  272. for (i = 4; i < 11; i++)
  273. if (buf[i] != 0)
  274. break;
  275. }
  276. if (i != 11) {
  277. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  278. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  279. i, buf[0], buf[1], buf[2], buf[3]);
  280. /* FIXME: return 1; */
  281. } else
  282. applog(LOG_WARNING, "%s%d: Reset succeeded",
  283. avalon->drv->name, avalon->device_id);
  284. return 0;
  285. }
  286. static int avalon_calc_timeout(int frequency)
  287. {
  288. return AVALON_TIMEOUT_FACTOR / frequency;
  289. }
  290. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  291. int *asic_count, int *timeout, int *frequency)
  292. {
  293. char buf[BUFSIZ+1];
  294. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  295. bool timeout_default;
  296. size_t max;
  297. int i, tmp;
  298. if (opt_avalon_options == NULL)
  299. buf[0] = '\0';
  300. else {
  301. ptr = opt_avalon_options;
  302. for (i = 0; i < this_option_offset; i++) {
  303. comma = strchr(ptr, ',');
  304. if (comma == NULL)
  305. break;
  306. ptr = comma + 1;
  307. }
  308. comma = strchr(ptr, ',');
  309. if (comma == NULL)
  310. max = strlen(ptr);
  311. else
  312. max = comma - ptr;
  313. if (max > BUFSIZ)
  314. max = BUFSIZ;
  315. strncpy(buf, ptr, max);
  316. buf[max] = '\0';
  317. }
  318. if (!(*buf))
  319. return false;
  320. colon = strchr(buf, ':');
  321. if (colon)
  322. *(colon++) = '\0';
  323. tmp = atoi(buf);
  324. switch (tmp) {
  325. case 115200:
  326. *baud = 115200;
  327. break;
  328. case 57600:
  329. *baud = 57600;
  330. break;
  331. case 38400:
  332. *baud = 38400;
  333. break;
  334. case 19200:
  335. *baud = 19200;
  336. break;
  337. default:
  338. quit(1, "Invalid avalon-options for baud (%s) "
  339. "must be 115200, 57600, 38400 or 19200", buf);
  340. }
  341. if (colon && *colon) {
  342. colon2 = strchr(colon, ':');
  343. if (colon2)
  344. *(colon2++) = '\0';
  345. if (*colon) {
  346. tmp = atoi(colon);
  347. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  348. *miner_count = tmp;
  349. } else {
  350. quit(1, "Invalid avalon-options for "
  351. "miner_count (%s) must be 1 ~ %d",
  352. colon, AVALON_DEFAULT_MINER_NUM);
  353. }
  354. }
  355. if (colon2 && *colon2) {
  356. colon3 = strchr(colon2, ':');
  357. if (colon3)
  358. *(colon3++) = '\0';
  359. tmp = atoi(colon2);
  360. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  361. *asic_count = tmp;
  362. else {
  363. quit(1, "Invalid avalon-options for "
  364. "asic_count (%s) must be 1 ~ %d",
  365. colon2, AVALON_DEFAULT_ASIC_NUM);
  366. }
  367. timeout_default = false;
  368. if (colon3 && *colon3) {
  369. colon4 = strchr(colon3, ':');
  370. if (colon4)
  371. *(colon4++) = '\0';
  372. if (tolower(*colon3) == 'd')
  373. timeout_default = true;
  374. else {
  375. tmp = atoi(colon3);
  376. if (tmp > 0 && tmp <= 0xff)
  377. *timeout = tmp;
  378. else {
  379. quit(1, "Invalid avalon-options for "
  380. "timeout (%s) must be 1 ~ %d",
  381. colon3, 0xff);
  382. }
  383. }
  384. if (colon4 && *colon4) {
  385. tmp = atoi(colon4);
  386. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  387. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  388. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  389. }
  390. *frequency = tmp;
  391. if (timeout_default)
  392. *timeout = avalon_calc_timeout(*frequency);
  393. }
  394. }
  395. }
  396. }
  397. return true;
  398. }
  399. char *set_avalon_fan(char *arg)
  400. {
  401. int val1, val2, ret;
  402. ret = sscanf(arg, "%d-%d", &val1, &val2);
  403. if (ret < 1)
  404. return "No values passed to avalon-fan";
  405. if (ret == 1)
  406. val2 = val1;
  407. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  408. return "Invalid value passed to avalon-fan";
  409. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  410. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  411. return NULL;
  412. }
  413. char *set_avalon_freq(char *arg)
  414. {
  415. int val1, val2, ret;
  416. ret = sscanf(arg, "%d-%d", &val1, &val2);
  417. if (ret < 1)
  418. return "No values passed to avalon-freq";
  419. if (ret == 1)
  420. val2 = val1;
  421. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  422. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  423. val2 < val1)
  424. return "Invalid value passed to avalon-freq";
  425. opt_avalon_freq_min = val1;
  426. opt_avalon_freq_max = val2;
  427. return NULL;
  428. }
  429. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  430. {
  431. int i;
  432. wait_avalon_ready(avalon);
  433. /* Send idle to all miners */
  434. for (i = 0; i < info->miner_count; i++) {
  435. struct avalon_task at;
  436. if (unlikely(avalon_buffer_full(avalon)))
  437. break;
  438. info->idle++;
  439. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  440. info->asic_count, info->miner_count, 1, 1,
  441. info->frequency);
  442. avalon_send_task(&at, avalon);
  443. }
  444. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  445. wait_avalon_ready(avalon);
  446. }
  447. static void avalon_initialise(struct cgpu_info *avalon)
  448. {
  449. int err, interface;
  450. if (avalon->usbinfo.nodev)
  451. return;
  452. interface = avalon->usbdev->found->interface;
  453. // Reset
  454. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  455. FTDI_VALUE_RESET, interface, C_RESET);
  456. applog(LOG_DEBUG, "%s%i: reset got err %d",
  457. avalon->drv->name, avalon->device_id, err);
  458. if (avalon->usbinfo.nodev)
  459. return;
  460. // Set latency
  461. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  462. AVALON_LATENCY, interface, C_LATENCY);
  463. applog(LOG_DEBUG, "%s%i: latency got err %d",
  464. avalon->drv->name, avalon->device_id, err);
  465. if (avalon->usbinfo.nodev)
  466. return;
  467. // Set data
  468. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  469. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  470. applog(LOG_DEBUG, "%s%i: data got err %d",
  471. avalon->drv->name, avalon->device_id, err);
  472. if (avalon->usbinfo.nodev)
  473. return;
  474. // Set the baud
  475. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  476. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  477. C_SETBAUD);
  478. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  479. avalon->drv->name, avalon->device_id, err);
  480. if (avalon->usbinfo.nodev)
  481. return;
  482. // Set Modem Control
  483. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  484. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  485. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  486. avalon->drv->name, avalon->device_id, err);
  487. if (avalon->usbinfo.nodev)
  488. return;
  489. // Set Flow Control
  490. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  491. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  492. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  493. avalon->drv->name, avalon->device_id, err);
  494. if (avalon->usbinfo.nodev)
  495. return;
  496. /* Avalon repeats the following */
  497. // Set Modem Control
  498. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  499. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  500. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  501. avalon->drv->name, avalon->device_id, err);
  502. if (avalon->usbinfo.nodev)
  503. return;
  504. // Set Flow Control
  505. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  506. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  507. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  508. avalon->drv->name, avalon->device_id, err);
  509. }
  510. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  511. {
  512. uint8_t buf[2];
  513. int err;
  514. if (usb_ident(avalon) == IDENT_BTB) {
  515. buf[0] = (uint8_t)core_voltage;
  516. buf[1] = (uint8_t)(core_voltage >> 8);
  517. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  518. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  519. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  520. if (unlikely(err < 0)) {
  521. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  522. avalon->drv->name, avalon->device_id, err);
  523. return false;
  524. } else {
  525. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  526. avalon->drv->name, avalon->device_id,
  527. core_voltage);
  528. }
  529. return true;
  530. }
  531. return false;
  532. }
  533. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  534. {
  535. uint8_t buf[2];
  536. int err;
  537. int amount;
  538. if (usb_ident(avalon) == IDENT_BTB) {
  539. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  540. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  541. (char *)buf, sizeof(buf), &amount,
  542. C_BB_GET_VOLTAGE);
  543. if (unlikely(err != 0 || amount != 2)) {
  544. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  545. avalon->drv->name, avalon->device_id, err, amount);
  546. return 0;
  547. } else {
  548. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  549. }
  550. } else {
  551. return 0;
  552. }
  553. }
  554. static void bitburner_get_version(struct cgpu_info *avalon)
  555. {
  556. struct avalon_info *info = avalon->device_data;
  557. uint8_t buf[3];
  558. int err;
  559. int amount;
  560. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  561. BITBURNER_VALUE, BITBURNER_INDEX_GET_VERSION,
  562. (char *)buf, sizeof(buf), &amount,
  563. C_GETVERSION);
  564. if (unlikely(err != 0 || amount != sizeof(buf))) {
  565. applog(LOG_DEBUG, "%s%i: GetVersion failed: err=%d, amt=%d assuming %d.%d.%d",
  566. avalon->drv->name, avalon->device_id, err, amount,
  567. BITBURNER_VERSION1, BITBURNER_VERSION2, BITBURNER_VERSION3);
  568. info->version1 = BITBURNER_VERSION1;
  569. info->version2 = BITBURNER_VERSION2;
  570. info->version3 = BITBURNER_VERSION3;
  571. } else {
  572. info->version1 = buf[0];
  573. info->version2 = buf[1];
  574. info->version3 = buf[2];
  575. }
  576. }
  577. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  578. {
  579. int baud, miner_count, asic_count, timeout, frequency;
  580. int this_option_offset = ++option_offset;
  581. struct avalon_info *info;
  582. struct cgpu_info *avalon;
  583. bool configured;
  584. int ret;
  585. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  586. baud = AVALON_IO_SPEED;
  587. miner_count = AVALON_DEFAULT_MINER_NUM;
  588. asic_count = AVALON_DEFAULT_ASIC_NUM;
  589. timeout = AVALON_DEFAULT_TIMEOUT;
  590. frequency = AVALON_DEFAULT_FREQUENCY;
  591. configured = get_options(this_option_offset, &baud, &miner_count,
  592. &asic_count, &timeout, &frequency);
  593. if (!usb_init(avalon, dev, found))
  594. goto shin;
  595. /* Even though this is an FTDI type chip, we want to do the parsing
  596. * all ourselves so set it to std usb type */
  597. avalon->usbdev->usb_type = USB_TYPE_STD;
  598. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  599. /* We have a real Avalon! */
  600. avalon_initialise(avalon);
  601. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  602. if (unlikely(!(avalon->device_data)))
  603. quit(1, "Failed to calloc avalon_info data");
  604. info = avalon->device_data;
  605. if (configured) {
  606. info->baud = baud;
  607. info->miner_count = miner_count;
  608. info->asic_count = asic_count;
  609. info->timeout = timeout;
  610. info->frequency = frequency;
  611. } else {
  612. info->baud = AVALON_IO_SPEED;
  613. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  614. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  615. info->timeout = AVALON_DEFAULT_TIMEOUT;
  616. info->frequency = AVALON_DEFAULT_FREQUENCY;
  617. }
  618. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  619. info->temp_max = 0;
  620. /* This is for check the temp/fan every 3~4s */
  621. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  622. if (info->temp_history_count <= 0)
  623. info->temp_history_count = 1;
  624. info->temp_history_index = 0;
  625. info->temp_sum = 0;
  626. info->temp_old = 0;
  627. if (!add_cgpu(avalon))
  628. goto unshin;
  629. ret = avalon_reset(avalon, true);
  630. if (ret && !configured)
  631. goto unshin;
  632. update_usb_stats(avalon);
  633. avalon_idle(avalon, info);
  634. applog(LOG_DEBUG, "Avalon Detected: %s "
  635. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  636. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  637. info->frequency);
  638. if (usb_ident(avalon) == IDENT_BTB) {
  639. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  640. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  641. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  642. opt_bitburner_core_voltage,
  643. BITBURNER_MIN_COREMV,
  644. BITBURNER_MAX_COREMV);
  645. } else
  646. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  647. bitburner_get_version(avalon);
  648. }
  649. return true;
  650. unshin:
  651. usb_uninit(avalon);
  652. shin:
  653. free(avalon->device_data);
  654. avalon->device_data = NULL;
  655. avalon = usb_free_cgpu(avalon);
  656. return false;
  657. }
  658. static void avalon_detect(void)
  659. {
  660. usb_detect(&avalon_drv, avalon_detect_one);
  661. }
  662. static void avalon_init(struct cgpu_info *avalon)
  663. {
  664. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  665. }
  666. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  667. {
  668. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  669. (char *)ar->data, 64, 12);
  670. }
  671. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  672. struct avalon_result *ar);
  673. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  674. {
  675. applog(LOG_INFO, "%s%d: No matching work - HW error",
  676. thr->cgpu->drv->name, thr->cgpu->device_id);
  677. inc_hw_errors(thr);
  678. info->no_matching_work++;
  679. }
  680. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  681. struct thr_info *thr, char *buf, int *offset)
  682. {
  683. int i, spare = *offset - AVALON_READ_SIZE;
  684. bool found = false;
  685. for (i = 0; i <= spare; i++) {
  686. struct avalon_result *ar;
  687. struct work *work;
  688. ar = (struct avalon_result *)&buf[i];
  689. work = avalon_valid_result(avalon, ar);
  690. if (work) {
  691. bool gettemp = false;
  692. found = true;
  693. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  694. mutex_lock(&info->lock);
  695. if (!info->nonces++)
  696. gettemp = true;
  697. info->auto_nonces++;
  698. mutex_unlock(&info->lock);
  699. } else if (opt_avalon_auto) {
  700. mutex_lock(&info->lock);
  701. info->auto_hw++;
  702. mutex_unlock(&info->lock);
  703. }
  704. free_work(work);
  705. if (gettemp)
  706. avalon_update_temps(avalon, info, ar);
  707. break;
  708. }
  709. }
  710. if (!found) {
  711. spare = *offset - AVALON_READ_SIZE;
  712. /* We are buffering and haven't accumulated one more corrupt
  713. * work result. */
  714. if (spare < (int)AVALON_READ_SIZE)
  715. return;
  716. avalon_inc_nvw(info, thr);
  717. } else {
  718. spare = AVALON_READ_SIZE + i;
  719. if (i) {
  720. if (i >= (int)AVALON_READ_SIZE)
  721. avalon_inc_nvw(info, thr);
  722. else
  723. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  724. }
  725. }
  726. *offset -= spare;
  727. memmove(buf, buf + spare, *offset);
  728. }
  729. static void avalon_running_reset(struct cgpu_info *avalon,
  730. struct avalon_info *info)
  731. {
  732. avalon_reset(avalon, false);
  733. avalon_idle(avalon, info);
  734. avalon->results = 0;
  735. info->reset = false;
  736. }
  737. static void *avalon_get_results(void *userdata)
  738. {
  739. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  740. struct avalon_info *info = avalon->device_data;
  741. const int rsize = AVALON_FTDI_READSIZE;
  742. char readbuf[AVALON_READBUF_SIZE];
  743. struct thr_info *thr = info->thr;
  744. cgtimer_t ts_start;
  745. int offset = 0, ret = 0;
  746. char threadname[24];
  747. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  748. RenameThread(threadname);
  749. cgsleep_prepare_r(&ts_start);
  750. while (likely(!avalon->shutdown)) {
  751. unsigned char buf[rsize];
  752. if (offset >= (int)AVALON_READ_SIZE)
  753. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  754. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  755. /* This should never happen */
  756. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  757. offset = 0;
  758. }
  759. if (unlikely(info->reset)) {
  760. avalon_running_reset(avalon, info);
  761. /* Discard anything in the buffer */
  762. offset = 0;
  763. }
  764. /* As the usb read returns after just 1ms, sleep long enough
  765. * to leave the interface idle for writes to occur, but do not
  766. * sleep if we have been receiving data, and we do not yet have
  767. * a full result as more may be coming. */
  768. if (ret < 1 || offset == 0)
  769. cgsleep_ms_r(&ts_start, AVALON_READ_TIMEOUT);
  770. cgsleep_prepare_r(&ts_start);
  771. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  772. C_AVALON_READ);
  773. if (ret < 1)
  774. continue;
  775. if (opt_debug) {
  776. applog(LOG_DEBUG, "Avalon: get:");
  777. hexdump((uint8_t *)buf, ret);
  778. }
  779. memcpy(&readbuf[offset], &buf, ret);
  780. offset += ret;
  781. }
  782. return NULL;
  783. }
  784. static void avalon_rotate_array(struct cgpu_info *avalon)
  785. {
  786. avalon->queued = 0;
  787. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  788. avalon->work_array = 0;
  789. }
  790. static void bitburner_rotate_array(struct cgpu_info *avalon)
  791. {
  792. avalon->queued = 0;
  793. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  794. avalon->work_array = 0;
  795. }
  796. static void avalon_set_timeout(struct avalon_info *info)
  797. {
  798. info->timeout = avalon_calc_timeout(info->frequency);
  799. }
  800. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  801. {
  802. struct avalon_info *info = avalon->device_data;
  803. info->frequency = frequency;
  804. if (info->frequency > opt_avalon_freq_max)
  805. info->frequency = opt_avalon_freq_max;
  806. if (info->frequency < opt_avalon_freq_min)
  807. info->frequency = opt_avalon_freq_min;
  808. avalon_set_timeout(info);
  809. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  810. avalon->drv->name, avalon->device_id,
  811. info->frequency, info->timeout);
  812. }
  813. static void avalon_inc_freq(struct avalon_info *info)
  814. {
  815. info->frequency += 2;
  816. if (info->frequency > opt_avalon_freq_max)
  817. info->frequency = opt_avalon_freq_max;
  818. avalon_set_timeout(info);
  819. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  820. info->frequency, info->timeout);
  821. }
  822. static void avalon_dec_freq(struct avalon_info *info)
  823. {
  824. info->frequency -= 1;
  825. if (info->frequency < opt_avalon_freq_min)
  826. info->frequency = opt_avalon_freq_min;
  827. avalon_set_timeout(info);
  828. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  829. info->frequency, info->timeout);
  830. }
  831. static void avalon_reset_auto(struct avalon_info *info)
  832. {
  833. info->auto_queued =
  834. info->auto_nonces =
  835. info->auto_hw = 0;
  836. }
  837. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  838. {
  839. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  840. mutex_lock(&info->lock);
  841. if (!info->optimal) {
  842. if (info->fan_pwm >= opt_avalon_fan_max) {
  843. applog(LOG_WARNING,
  844. "%s%i: Above optimal temperature, throttling",
  845. avalon->drv->name, avalon->device_id);
  846. avalon_dec_freq(info);
  847. }
  848. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  849. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  850. int total = info->auto_nonces + info->auto_hw;
  851. /* Try to keep hw errors < 2% */
  852. if (info->auto_hw * 100 < total)
  853. avalon_inc_freq(info);
  854. else if (info->auto_hw * 66 > total)
  855. avalon_dec_freq(info);
  856. }
  857. avalon_reset_auto(info);
  858. mutex_unlock(&info->lock);
  859. }
  860. }
  861. static void *avalon_send_tasks(void *userdata)
  862. {
  863. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  864. struct avalon_info *info = avalon->device_data;
  865. const int avalon_get_work_count = info->miner_count;
  866. char threadname[24];
  867. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  868. RenameThread(threadname);
  869. while (likely(!avalon->shutdown)) {
  870. int start_count, end_count, i, j, ret;
  871. cgtimer_t ts_start;
  872. struct avalon_task at;
  873. bool idled = false;
  874. int64_t us_timeout;
  875. while (avalon_buffer_full(avalon))
  876. cgsleep_ms(40);
  877. avalon_adjust_freq(info, avalon);
  878. /* A full nonce range */
  879. us_timeout = 0x100000000ll / info->asic_count / info->frequency;
  880. cgsleep_prepare_r(&ts_start);
  881. mutex_lock(&info->qlock);
  882. start_count = avalon->work_array * avalon_get_work_count;
  883. end_count = start_count + avalon_get_work_count;
  884. for (i = start_count, j = 0; i < end_count; i++, j++) {
  885. if (avalon_buffer_full(avalon)) {
  886. applog(LOG_INFO,
  887. "%s%i: Buffer full after only %d of %d work queued",
  888. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  889. break;
  890. }
  891. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  892. avalon_init_task(&at, 0, 0, info->fan_pwm,
  893. info->timeout, info->asic_count,
  894. info->miner_count, 1, 0, info->frequency);
  895. avalon_create_task(&at, avalon->works[i]);
  896. info->auto_queued++;
  897. } else {
  898. int idle_freq = info->frequency;
  899. if (!info->idle++)
  900. idled = true;
  901. if (unlikely(info->overheat && opt_avalon_auto))
  902. idle_freq = AVALON_MIN_FREQUENCY;
  903. avalon_init_task(&at, 0, 0, info->fan_pwm,
  904. info->timeout, info->asic_count,
  905. info->miner_count, 1, 1, idle_freq);
  906. /* Reset the auto_queued count if we end up
  907. * idling any miners. */
  908. avalon_reset_auto(info);
  909. }
  910. ret = avalon_send_task(&at, avalon);
  911. if (unlikely(ret == AVA_SEND_ERROR)) {
  912. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  913. avalon->drv->name, avalon->device_id);
  914. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  915. info->reset = true;
  916. break;
  917. }
  918. }
  919. avalon_rotate_array(avalon);
  920. pthread_cond_signal(&info->qcond);
  921. mutex_unlock(&info->qlock);
  922. if (unlikely(idled)) {
  923. applog(LOG_WARNING, "%s%i: Idled %d miners",
  924. avalon->drv->name, avalon->device_id, idled);
  925. }
  926. /* Sleep how long it would take to complete a full nonce range
  927. * at the current frequency using the clock_nanosleep function
  928. * timed from before we started loading new work so it will
  929. * fall short of the full duration. */
  930. cgsleep_us_r(&ts_start, us_timeout);
  931. }
  932. return NULL;
  933. }
  934. static void *bitburner_send_tasks(void *userdata)
  935. {
  936. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  937. struct avalon_info *info = avalon->device_data;
  938. const int avalon_get_work_count = info->miner_count;
  939. char threadname[24];
  940. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  941. RenameThread(threadname);
  942. while (likely(!avalon->shutdown)) {
  943. int start_count, end_count, i, j, ret;
  944. struct avalon_task at;
  945. bool idled = false;
  946. while (avalon_buffer_full(avalon))
  947. cgsleep_ms(40);
  948. avalon_adjust_freq(info, avalon);
  949. /* Give other threads a chance to acquire qlock. */
  950. i = 0;
  951. do {
  952. cgsleep_ms(40);
  953. } while (!avalon->shutdown && i++ < 15
  954. && avalon->queued < avalon_get_work_count);
  955. mutex_lock(&info->qlock);
  956. start_count = avalon->work_array * avalon_get_work_count;
  957. end_count = start_count + avalon_get_work_count;
  958. for (i = start_count, j = 0; i < end_count; i++, j++) {
  959. while (avalon_buffer_full(avalon))
  960. cgsleep_ms(40);
  961. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  962. avalon_init_task(&at, 0, 0, info->fan_pwm,
  963. info->timeout, info->asic_count,
  964. info->miner_count, 1, 0, info->frequency);
  965. avalon_create_task(&at, avalon->works[i]);
  966. info->auto_queued++;
  967. } else {
  968. int idle_freq = info->frequency;
  969. if (!info->idle++)
  970. idled = true;
  971. if (unlikely(info->overheat && opt_avalon_auto))
  972. idle_freq = AVALON_MIN_FREQUENCY;
  973. avalon_init_task(&at, 0, 0, info->fan_pwm,
  974. info->timeout, info->asic_count,
  975. info->miner_count, 1, 1, idle_freq);
  976. /* Reset the auto_queued count if we end up
  977. * idling any miners. */
  978. avalon_reset_auto(info);
  979. }
  980. ret = avalon_send_task(&at, avalon);
  981. if (unlikely(ret == AVA_SEND_ERROR)) {
  982. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  983. avalon->drv->name, avalon->device_id);
  984. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  985. info->reset = true;
  986. break;
  987. }
  988. }
  989. bitburner_rotate_array(avalon);
  990. pthread_cond_signal(&info->qcond);
  991. mutex_unlock(&info->qlock);
  992. if (unlikely(idled)) {
  993. applog(LOG_WARNING, "%s%i: Idled %d miners",
  994. avalon->drv->name, avalon->device_id, idled);
  995. }
  996. }
  997. return NULL;
  998. }
  999. static bool avalon_prepare(struct thr_info *thr)
  1000. {
  1001. struct cgpu_info *avalon = thr->cgpu;
  1002. struct avalon_info *info = avalon->device_data;
  1003. int array_size = AVALON_ARRAY_SIZE;
  1004. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  1005. if (usb_ident(avalon) == IDENT_BTB) {
  1006. array_size = BITBURNER_ARRAY_SIZE;
  1007. write_thread_fn = bitburner_send_tasks;
  1008. }
  1009. free(avalon->works);
  1010. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  1011. array_size);
  1012. if (!avalon->works)
  1013. quit(1, "Failed to calloc avalon works in avalon_prepare");
  1014. info->thr = thr;
  1015. mutex_init(&info->lock);
  1016. mutex_init(&info->qlock);
  1017. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1018. quit(1, "Failed to pthread_cond_init avalon qcond");
  1019. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  1020. quit(1, "Failed to create avalon read_thr");
  1021. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  1022. quit(1, "Failed to create avalon write_thr");
  1023. avalon_init(avalon);
  1024. return true;
  1025. }
  1026. static void do_avalon_close(struct thr_info *thr)
  1027. {
  1028. struct cgpu_info *avalon = thr->cgpu;
  1029. struct avalon_info *info = avalon->device_data;
  1030. pthread_join(info->read_thr, NULL);
  1031. pthread_join(info->write_thr, NULL);
  1032. avalon_running_reset(avalon, info);
  1033. info->no_matching_work = 0;
  1034. }
  1035. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  1036. {
  1037. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1038. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1039. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1040. info->temp0 = ar->temp0;
  1041. info->temp1 = ar->temp1;
  1042. info->temp2 = ar->temp2;
  1043. if (ar->temp0 & 0x80) {
  1044. ar->temp0 &= 0x7f;
  1045. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1046. }
  1047. if (ar->temp1 & 0x80) {
  1048. ar->temp1 &= 0x7f;
  1049. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1050. }
  1051. if (ar->temp2 & 0x80) {
  1052. ar->temp2 &= 0x7f;
  1053. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1054. }
  1055. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  1056. if (info->temp0 > info->temp_max)
  1057. info->temp_max = info->temp0;
  1058. if (info->temp1 > info->temp_max)
  1059. info->temp_max = info->temp1;
  1060. if (info->temp2 > info->temp_max)
  1061. info->temp_max = info->temp2;
  1062. }
  1063. static void temp_rise(struct avalon_info *info, int temp)
  1064. {
  1065. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1066. info->fan_pwm = AVALON_PWM_MAX;
  1067. return;
  1068. }
  1069. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1070. info->fan_pwm += 10;
  1071. else if (temp > opt_avalon_temp)
  1072. info->fan_pwm += 5;
  1073. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1074. info->fan_pwm += 1;
  1075. else
  1076. return;
  1077. if (info->fan_pwm > opt_avalon_fan_max)
  1078. info->fan_pwm = opt_avalon_fan_max;
  1079. }
  1080. static void temp_drop(struct avalon_info *info, int temp)
  1081. {
  1082. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1083. info->fan_pwm = opt_avalon_fan_min;
  1084. return;
  1085. }
  1086. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1087. info->fan_pwm -= 10;
  1088. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1089. info->fan_pwm -= 5;
  1090. else if (temp < opt_avalon_temp)
  1091. info->fan_pwm -= 1;
  1092. if (info->fan_pwm < opt_avalon_fan_min)
  1093. info->fan_pwm = opt_avalon_fan_min;
  1094. }
  1095. static inline void adjust_fan(struct avalon_info *info)
  1096. {
  1097. int temp_new;
  1098. temp_new = info->temp_sum / info->temp_history_count;
  1099. if (temp_new > info->temp_old)
  1100. temp_rise(info, temp_new);
  1101. else if (temp_new < info->temp_old)
  1102. temp_drop(info, temp_new);
  1103. else {
  1104. /* temp_new == info->temp_old */
  1105. if (temp_new > opt_avalon_temp)
  1106. temp_rise(info, temp_new);
  1107. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1108. temp_drop(info, temp_new);
  1109. }
  1110. info->temp_old = temp_new;
  1111. if (info->temp_old <= opt_avalon_temp)
  1112. info->optimal = true;
  1113. else
  1114. info->optimal = false;
  1115. }
  1116. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1117. struct avalon_result *ar)
  1118. {
  1119. record_temp_fan(info, ar, &(avalon->temp));
  1120. applog(LOG_INFO,
  1121. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1122. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1123. info->fan0, info->fan1, info->fan2,
  1124. info->temp0, info->temp1, info->temp2, info->temp_max);
  1125. info->temp_history_index++;
  1126. info->temp_sum += avalon->temp;
  1127. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1128. info->temp_history_index, info->temp_history_count, info->temp_old);
  1129. if (usb_ident(avalon) == IDENT_BTB) {
  1130. info->core_voltage = bitburner_get_core_voltage(avalon);
  1131. }
  1132. if (info->temp_history_index == info->temp_history_count) {
  1133. adjust_fan(info);
  1134. info->temp_history_index = 0;
  1135. info->temp_sum = 0;
  1136. }
  1137. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1138. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1139. info->overheat = true;
  1140. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1141. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1142. info->overheat = false;
  1143. }
  1144. }
  1145. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1146. {
  1147. struct avalon_info *info = avalon->device_data;
  1148. int lowfan = 10000;
  1149. if (usb_ident(avalon) == IDENT_BTB) {
  1150. int temp = info->temp0;
  1151. if (info->temp2 > temp)
  1152. temp = info->temp2;
  1153. if (temp > 99)
  1154. temp = 99;
  1155. if (temp < 0)
  1156. temp = 0;
  1157. tailsprintf(buf, bufsiz, "%2dC %3d %4dmV | ", temp, info->frequency, info->core_voltage);
  1158. } else {
  1159. /* Find the lowest fan speed of the ASIC cooling fans. */
  1160. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1161. lowfan = info->fan1;
  1162. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1163. lowfan = info->fan2;
  1164. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1165. }
  1166. }
  1167. /* We use a replacement algorithm to only remove references to work done from
  1168. * the buffer when we need the extra space for new work. */
  1169. static bool avalon_fill(struct cgpu_info *avalon)
  1170. {
  1171. struct avalon_info *info = avalon->device_data;
  1172. int subid, slot, mc;
  1173. struct work *work;
  1174. bool ret = true;
  1175. mc = info->miner_count;
  1176. mutex_lock(&info->qlock);
  1177. if (avalon->queued >= mc)
  1178. goto out_unlock;
  1179. work = get_queued(avalon);
  1180. if (unlikely(!work)) {
  1181. ret = false;
  1182. goto out_unlock;
  1183. }
  1184. subid = avalon->queued++;
  1185. work->subid = subid;
  1186. slot = avalon->work_array * mc + subid;
  1187. if (likely(avalon->works[slot]))
  1188. work_completed(avalon, avalon->works[slot]);
  1189. avalon->works[slot] = work;
  1190. if (avalon->queued < mc)
  1191. ret = false;
  1192. out_unlock:
  1193. mutex_unlock(&info->qlock);
  1194. return ret;
  1195. }
  1196. static int64_t avalon_scanhash(struct thr_info *thr)
  1197. {
  1198. struct cgpu_info *avalon = thr->cgpu;
  1199. struct avalon_info *info = avalon->device_data;
  1200. const int miner_count = info->miner_count;
  1201. struct timeval now, then, tdiff;
  1202. int64_t hash_count, us_timeout;
  1203. struct timespec abstime;
  1204. /* Half nonce range */
  1205. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1206. us_to_timeval(&tdiff, us_timeout);
  1207. cgtime(&now);
  1208. timeradd(&now, &tdiff, &then);
  1209. timeval_to_spec(&abstime, &then);
  1210. /* Wait until avalon_send_tasks signals us that it has completed
  1211. * sending its work or a full nonce range timeout has occurred */
  1212. mutex_lock(&info->qlock);
  1213. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1214. mutex_unlock(&info->qlock);
  1215. mutex_lock(&info->lock);
  1216. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1217. avalon->results += info->nonces + info->idle;
  1218. if (avalon->results > miner_count)
  1219. avalon->results = miner_count;
  1220. if (!info->reset)
  1221. avalon->results--;
  1222. info->nonces = info->idle = 0;
  1223. mutex_unlock(&info->lock);
  1224. /* Check for nothing but consecutive bad results or consistently less
  1225. * results than we should be getting and reset the FPGA if necessary */
  1226. if (usb_ident(avalon) != IDENT_BTB) {
  1227. if (avalon->results < -miner_count && !info->reset) {
  1228. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1229. avalon->drv->name, avalon->device_id);
  1230. info->reset = true;
  1231. }
  1232. }
  1233. if (unlikely(avalon->usbinfo.nodev)) {
  1234. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1235. avalon->drv->name, avalon->device_id);
  1236. avalon->shutdown = true;
  1237. }
  1238. /* This hashmeter is just a utility counter based on returned shares */
  1239. return hash_count;
  1240. }
  1241. static void avalon_flush_work(struct cgpu_info *avalon)
  1242. {
  1243. struct avalon_info *info = avalon->device_data;
  1244. mutex_lock(&info->qlock);
  1245. /* Will overwrite any work queued */
  1246. avalon->queued = 0;
  1247. pthread_cond_signal(&info->qcond);
  1248. mutex_unlock(&info->qlock);
  1249. }
  1250. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1251. {
  1252. struct api_data *root = NULL;
  1253. struct avalon_info *info = cgpu->device_data;
  1254. char buf[64];
  1255. int i;
  1256. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1257. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1258. root = api_add_int(root, "baud", &(info->baud), false);
  1259. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1260. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1261. root = api_add_int(root, "timeout", &(info->timeout), false);
  1262. root = api_add_int(root, "frequency", &(info->frequency), false);
  1263. root = api_add_int(root, "fan1", &(info->fan0), false);
  1264. root = api_add_int(root, "fan2", &(info->fan1), false);
  1265. root = api_add_int(root, "fan3", &(info->fan2), false);
  1266. root = api_add_int(root, "temp1", &(info->temp0), false);
  1267. root = api_add_int(root, "temp2", &(info->temp1), false);
  1268. root = api_add_int(root, "temp3", &(info->temp2), false);
  1269. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1270. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1271. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1272. for (i = 0; i < info->miner_count; i++) {
  1273. char mcw[24];
  1274. sprintf(mcw, "match_work_count%d", i + 1);
  1275. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1276. }
  1277. if (usb_ident(cgpu) == IDENT_BTB) {
  1278. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1279. snprintf(buf, sizeof(buf), "%"PRIu8".%"PRIu8".%"PRIu8,
  1280. info->version1, info->version2, info->version3);
  1281. root = api_add_string(root, "version", buf, true);
  1282. }
  1283. return root;
  1284. }
  1285. static void avalon_shutdown(struct thr_info *thr)
  1286. {
  1287. do_avalon_close(thr);
  1288. }
  1289. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1290. {
  1291. int val;
  1292. if (strcasecmp(option, "help") == 0) {
  1293. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1294. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1295. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1296. return replybuf;
  1297. }
  1298. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1299. if (usb_ident(avalon) != IDENT_BTB) {
  1300. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1301. return replybuf;
  1302. }
  1303. if (!setting || !*setting) {
  1304. sprintf(replybuf, "missing millivolts setting");
  1305. return replybuf;
  1306. }
  1307. val = atoi(setting);
  1308. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1309. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1310. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1311. return replybuf;
  1312. }
  1313. if (bitburner_set_core_voltage(avalon, val))
  1314. return NULL;
  1315. else {
  1316. sprintf(replybuf, "Set millivolts failed");
  1317. return replybuf;
  1318. }
  1319. }
  1320. if (strcasecmp(option, "freq") == 0) {
  1321. if (!setting || !*setting) {
  1322. sprintf(replybuf, "missing freq setting");
  1323. return replybuf;
  1324. }
  1325. val = atoi(setting);
  1326. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1327. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1328. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1329. return replybuf;
  1330. }
  1331. avalon_set_freq(avalon, val);
  1332. return NULL;
  1333. }
  1334. sprintf(replybuf, "Unknown option: %s", option);
  1335. return replybuf;
  1336. }
  1337. struct device_drv avalon_drv = {
  1338. .drv_id = DRIVER_AVALON,
  1339. .dname = "avalon",
  1340. .name = "AVA",
  1341. .drv_detect = avalon_detect,
  1342. .thread_prepare = avalon_prepare,
  1343. .hash_work = hash_queued_work,
  1344. .queue_full = avalon_fill,
  1345. .scanwork = avalon_scanhash,
  1346. .flush_work = avalon_flush_work,
  1347. .get_api_stats = avalon_api_stats,
  1348. .get_statline_before = get_avalon_statline_before,
  1349. .set_device = avalon_set_device,
  1350. .reinit_device = avalon_init,
  1351. .thread_shutdown = avalon_shutdown,
  1352. };