driver-avalon.c 22 KB

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  1. /*
  2. * Copyright 2013 Xiangfu
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int option_offset = -1;
  34. struct avalon_info **avalon_info;
  35. struct device_api avalon_api;
  36. static int avalon_init_task(struct thr_info *thr, struct avalon_task *at,
  37. uint8_t reset, uint8_t ff, uint8_t fan,
  38. uint8_t timeout_p, uint8_t asic_num_p,
  39. uint8_t miner_num_p, uint8_t nonce_elf_p)
  40. {
  41. static bool first = true;
  42. uint8_t timeout;
  43. uint8_t asic_num;
  44. uint8_t miner_num;
  45. struct cgpu_info *avalon;
  46. struct avalon_info *info;
  47. if (unlikely(!at))
  48. return -1;
  49. if (unlikely(!thr && (timeout_p <= 0 || asic_num_p <= 0 || miner_num_p <= 0)))
  50. return -1;
  51. timeout = timeout_p;
  52. miner_num = miner_num_p;
  53. asic_num = asic_num_p;
  54. if (likely(thr)) {
  55. avalon = thr->cgpu;
  56. info = avalon_info[avalon->device_id];
  57. timeout = info->timeout;
  58. miner_num = info->miner_count;
  59. asic_num = info->asic_count;
  60. }
  61. memset(at, 0, sizeof(struct avalon_task));
  62. if (unlikely(reset)) {
  63. at->reset = 1;
  64. at->fan_eft = 1;
  65. at->timer_eft = 1;
  66. first = true;
  67. }
  68. at->flush_fifo = (ff ? 1 : 0);
  69. at->fan_eft = (fan ? 1 : 0);
  70. if (unlikely(first && !at->reset)) {
  71. at->fan_eft = 1;
  72. at->timer_eft = 1;
  73. first = false;
  74. }
  75. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  76. at->timeout_data = timeout;
  77. at->asic_num = asic_num;
  78. at->miner_num = miner_num;
  79. at->nonce_elf = nonce_elf_p;
  80. return 0;
  81. }
  82. static inline void avalon_create_task(struct avalon_task *at,
  83. struct work *work)
  84. {
  85. memcpy(at->midstate, work->midstate, 32);
  86. memcpy(at->data, work->data + 64, 12);
  87. }
  88. static int avalon_send_task(int fd, const struct avalon_task *at,
  89. struct thr_info *thr)
  90. {
  91. size_t ret;
  92. int full;
  93. struct timespec p;
  94. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  95. size_t nr_len;
  96. struct cgpu_info *avalon;
  97. struct avalon_info *info;
  98. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  99. uint32_t nonce_range;
  100. int i;
  101. if (at->nonce_elf)
  102. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  103. else
  104. nr_len = AVALON_WRITE_SIZE;
  105. memcpy(buf, at, AVALON_WRITE_SIZE);
  106. if (at->nonce_elf) {
  107. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  108. for (i = 0; i < at->asic_num; i++) {
  109. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  110. (i * nonce_range & 0xff000000) >> 24;
  111. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  112. (i * nonce_range & 0x00ff0000) >> 16;
  113. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  114. (i * nonce_range & 0x0000ff00) >> 8;
  115. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  116. (i * nonce_range & 0x000000ff) >> 0;
  117. }
  118. }
  119. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  120. uint8_t tt = 0;
  121. tt = (buf[0] & 0x0f) << 4;
  122. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  123. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  124. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  125. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  126. buf[0] = tt;
  127. buf[4] = rev8(buf[4]);
  128. #endif
  129. if (at->reset)
  130. nr_len = 1;
  131. if (opt_debug) {
  132. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  133. hexdump((uint8_t *)buf, nr_len);
  134. }
  135. ret = write(fd, buf, nr_len);
  136. if (unlikely(ret != nr_len))
  137. return AVA_SEND_ERROR;
  138. if (likely(thr)) {
  139. avalon = thr->cgpu;
  140. info = avalon_info[avalon->device_id];
  141. delay = nr_len * 10 * 1000000000ULL;
  142. delay = delay / info->baud;
  143. }
  144. p.tv_sec = 0;
  145. p.tv_nsec = (long)delay + 4000000;
  146. nanosleep(&p, NULL);
  147. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  148. full = avalon_buffer_full(fd);
  149. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  150. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  151. if (unlikely(full == AVA_BUFFER_FULL))
  152. return AVA_SEND_BUFFER_FULL;
  153. return AVA_SEND_BUFFER_EMPTY;
  154. }
  155. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  156. struct thr_info *thr, struct timeval *tv_finish)
  157. {
  158. ssize_t ret = 0;
  159. int rc = 0;
  160. int read_amount = AVALON_READ_SIZE;
  161. bool first = true;
  162. /* Read reply 1 byte at a time to get earliest tv_finish */
  163. while (true) {
  164. ret = read(fd, buf, 1);
  165. if (ret < 0)
  166. return AVA_GETS_ERROR;
  167. if (first && tv_finish != NULL)
  168. gettimeofday(tv_finish, NULL);
  169. if (ret >= read_amount)
  170. return AVA_GETS_OK;
  171. if (ret > 0) {
  172. buf += ret;
  173. read_amount -= ret;
  174. first = false;
  175. continue;
  176. }
  177. rc++;
  178. if (rc >= read_count) {
  179. if (opt_debug) {
  180. applog(LOG_WARNING,
  181. "Avalon: No data in %.2f seconds",
  182. (float)rc/(float)TIME_FACTOR);
  183. }
  184. return AVA_GETS_TIMEOUT;
  185. }
  186. if (thr && thr->work_restart) {
  187. if (opt_debug) {
  188. applog(LOG_WARNING,
  189. "Avalon: Work restart at %.2f seconds",
  190. (float)(rc)/(float)TIME_FACTOR);
  191. }
  192. return AVA_GETS_RESTART;
  193. }
  194. }
  195. }
  196. static int avalon_get_result(int fd, struct avalon_result *ar,
  197. struct thr_info *thr, struct timeval *tv_finish)
  198. {
  199. struct cgpu_info *avalon;
  200. struct avalon_info *info;
  201. uint8_t result[AVALON_READ_SIZE];
  202. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * TIME_FACTOR;
  203. if (likely(thr)) {
  204. avalon = thr->cgpu;
  205. info = avalon_info[avalon->device_id];
  206. read_count = info->read_count;
  207. }
  208. memset(result, 0, AVALON_READ_SIZE);
  209. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  210. if (ret == AVA_GETS_OK) {
  211. if (opt_debug) {
  212. applog(LOG_DEBUG, "Avalon: get:");
  213. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  214. }
  215. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  216. }
  217. return ret;
  218. }
  219. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  220. struct avalon_result *ar, uint32_t *nonce)
  221. {
  222. struct cgpu_info *avalon;
  223. struct avalon_info *info;
  224. int avalon_get_work_count, i;
  225. if (unlikely(!work))
  226. return -1;
  227. avalon = thr->cgpu;
  228. info = avalon_info[avalon->device_id];
  229. avalon_get_work_count = info->miner_count;
  230. for (i = 0; i < avalon_get_work_count; i++) {
  231. if (work[i] &&
  232. !memcmp(ar->data, work[i]->data + 64, 12) &&
  233. !memcmp(ar->midstate, work[i]->midstate, 32))
  234. break;
  235. }
  236. if (i == avalon_get_work_count)
  237. return -1;
  238. ++info->matching_work[i];
  239. *nonce = ar->nonce;
  240. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  241. *nonce = swab32(*nonce);
  242. #endif
  243. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  244. info->matching_work[i]);
  245. return i;
  246. }
  247. static int avalon_reset(int fd, uint8_t timeout_p, uint8_t asic_num_p,
  248. uint8_t miner_num_p, struct avalon_result *ar)
  249. {
  250. struct avalon_task at;
  251. uint8_t *buf;
  252. int ret, i = 0;
  253. struct timespec p;
  254. avalon_init_task(NULL,
  255. &at, 1, 0,
  256. AVALON_DEFAULT_FAN_PWM,
  257. timeout_p, asic_num_p, miner_num_p, 1);
  258. ret = avalon_send_task(fd, &at, NULL);
  259. if (ret == AVA_SEND_ERROR)
  260. return 1;
  261. avalon_get_result(fd, ar, NULL, NULL);
  262. buf = (uint8_t *)ar;
  263. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  264. buf[2] == 0xAA && buf[3] == 0x55) {
  265. for (i = 4; i < 11; i++)
  266. if (buf[i] != 0)
  267. break;
  268. }
  269. if (i != 11) {
  270. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  271. " (%d: %02x %02x %02x %02x)",
  272. i, buf[0], buf[1], buf[2], buf[3]);
  273. /* FIXME: return 1; */
  274. }
  275. p.tv_sec = 1;
  276. p.tv_nsec = AVALON_RESET_PITCH;
  277. nanosleep(&p, NULL);
  278. applog(LOG_WARNING,
  279. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  280. "Temp1: %d, Temp2: %d, Temp3: %d",
  281. ar->fan0, ar->fan1, ar->fan2, ar->temp0, ar->temp1, ar->temp2);
  282. applog(LOG_WARNING, "Avalon: Reset succeeded");
  283. return 0;
  284. }
  285. static void set_timing_mode(struct cgpu_info *avalon, struct avalon_result *ar)
  286. {
  287. struct avalon_info *info = avalon_info[avalon->device_id];
  288. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  289. TIME_FACTOR) / (float)info->miner_count;
  290. info->fan0 = ar->fan0;
  291. info->fan1 = ar->fan1;
  292. info->fan2 = ar->fan2;
  293. info->temp0 = ar->temp0;
  294. info->temp1 = ar->temp1;
  295. info->temp2 = ar->temp2;
  296. if (info->temp0 > info->temp_max)
  297. info->temp_max = info->temp0;
  298. if (info->temp1 > info->temp_max)
  299. info->temp_max = info->temp1;
  300. if (info->temp2 > info->temp_max)
  301. info->temp_max = info->temp2;
  302. }
  303. static void get_options(int this_option_offset, int *baud, int *miner_count,
  304. int *asic_count, int *timeout)
  305. {
  306. char err_buf[BUFSIZ+1];
  307. char buf[BUFSIZ+1];
  308. char *ptr, *comma, *colon, *colon2, *colon3;
  309. size_t max;
  310. int i, tmp;
  311. if (opt_avalon_options == NULL)
  312. buf[0] = '\0';
  313. else {
  314. ptr = opt_avalon_options;
  315. for (i = 0; i < this_option_offset; i++) {
  316. comma = strchr(ptr, ',');
  317. if (comma == NULL)
  318. break;
  319. ptr = comma + 1;
  320. }
  321. comma = strchr(ptr, ',');
  322. if (comma == NULL)
  323. max = strlen(ptr);
  324. else
  325. max = comma - ptr;
  326. if (max > BUFSIZ)
  327. max = BUFSIZ;
  328. strncpy(buf, ptr, max);
  329. buf[max] = '\0';
  330. }
  331. *baud = AVALON_IO_SPEED;
  332. *miner_count = AVALON_DEFAULT_MINER_NUM;
  333. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  334. *timeout = AVALON_DEFAULT_TIMEOUT;
  335. if (!(*buf))
  336. return;
  337. colon = strchr(buf, ':');
  338. if (colon)
  339. *(colon++) = '\0';
  340. tmp = atoi(buf);
  341. switch (tmp) {
  342. case 115200:
  343. *baud = 115200;
  344. break;
  345. case 57600:
  346. *baud = 57600;
  347. break;
  348. case 38400:
  349. *baud = 38400;
  350. break;
  351. case 19200:
  352. *baud = 19200;
  353. break;
  354. default:
  355. sprintf(err_buf,
  356. "Invalid avalon-options for baud (%s) "
  357. "must be 115200, 57600, 38400 or 19200", buf);
  358. quit(1, err_buf);
  359. }
  360. if (colon && *colon) {
  361. colon2 = strchr(colon, ':');
  362. if (colon2)
  363. *(colon2++) = '\0';
  364. if (*colon) {
  365. tmp = atoi(colon);
  366. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  367. *miner_count = tmp;
  368. } else {
  369. sprintf(err_buf,
  370. "Invalid avalon-options for "
  371. "miner_count (%s) must be 1 ~ %d",
  372. colon, AVALON_DEFAULT_MINER_NUM);
  373. quit(1, err_buf);
  374. }
  375. }
  376. if (colon2 && *colon2) {
  377. colon3 = strchr(colon2, ':');
  378. if (colon3)
  379. *(colon3++) = '\0';
  380. tmp = atoi(colon2);
  381. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  382. *asic_count = tmp;
  383. else {
  384. sprintf(err_buf,
  385. "Invalid avalon-options for "
  386. "asic_count (%s) must be 1 ~ %d",
  387. colon2, AVALON_DEFAULT_ASIC_NUM);
  388. quit(1, err_buf);
  389. }
  390. if (colon3 && *colon3) {
  391. tmp = atoi(colon3);
  392. if (tmp > 0 && tmp <= 0xff)
  393. *timeout = tmp;
  394. else {
  395. sprintf(err_buf,
  396. "Invalid avalon-options for "
  397. "timeout (%s) must be 1 ~ %d",
  398. colon3, 0xff);
  399. quit(1, err_buf);
  400. }
  401. }
  402. }
  403. }
  404. }
  405. static bool avalon_detect_one(const char *devpath)
  406. {
  407. struct avalon_info *info;
  408. struct avalon_result ar;
  409. int fd, ret;
  410. int baud, miner_count, asic_count, timeout;
  411. int this_option_offset = ++option_offset;
  412. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  413. &timeout);
  414. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  415. "(baud=%d miner_count=%d asic_count=%d timeout=%d)",
  416. devpath, baud, miner_count, asic_count, timeout);
  417. fd = avalon_open2(devpath, baud, true);
  418. if (unlikely(fd == -1)) {
  419. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  420. return false;
  421. }
  422. ret = avalon_reset(fd, timeout, asic_count, miner_count, &ar);
  423. avalon_close(fd);
  424. if (ret) {
  425. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  426. }
  427. /* We have a real Avalon! */
  428. struct cgpu_info *avalon;
  429. avalon = calloc(1, sizeof(struct cgpu_info));
  430. avalon->api = &avalon_api;
  431. avalon->device_path = strdup(devpath);
  432. avalon->device_fd = -1;
  433. avalon->threads = AVALON_MINER_THREADS;
  434. add_cgpu(avalon);
  435. avalon_info = realloc(avalon_info,
  436. sizeof(struct avalon_info *) *
  437. (total_devices + 1));
  438. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  439. devpath, avalon->device_id);
  440. avalon_info[avalon->device_id] = (struct avalon_info *)
  441. malloc(sizeof(struct avalon_info));
  442. if (unlikely(!(avalon_info[avalon->device_id])))
  443. quit(1, "Failed to malloc avalon_info");
  444. info = avalon_info[avalon->device_id];
  445. memset(info, 0, sizeof(struct avalon_info));
  446. info->baud = baud;
  447. info->miner_count = miner_count;
  448. info->asic_count = asic_count;
  449. info->timeout = timeout;
  450. set_timing_mode(avalon, &ar);
  451. return true;
  452. }
  453. static inline void avalon_detect()
  454. {
  455. serial_detect(&avalon_api, avalon_detect_one);
  456. }
  457. static bool avalon_prepare(struct thr_info *thr)
  458. {
  459. struct avalon_result ar;
  460. struct cgpu_info *avalon = thr->cgpu;
  461. struct timeval now;
  462. int fd, ret;
  463. struct avalon_info *info = avalon_info[avalon->device_id];
  464. avalon->device_fd = -1;
  465. fd = avalon_open(avalon->device_path,
  466. avalon_info[avalon->device_id]->baud);
  467. if (unlikely(fd == -1)) {
  468. applog(LOG_ERR, "Avalon: Failed to open on %s",
  469. avalon->device_path);
  470. return false;
  471. }
  472. ret = avalon_reset(fd, info->timeout, info->asic_count,
  473. info->miner_count, &ar);
  474. if (ret)
  475. return false;
  476. avalon->device_fd = fd;
  477. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  478. gettimeofday(&now, NULL);
  479. get_datestamp(avalon->init, &now);
  480. return true;
  481. }
  482. static void avalon_free_work(struct thr_info *thr, struct work **work)
  483. {
  484. struct cgpu_info *avalon;
  485. struct avalon_info *info;
  486. int i;
  487. if (unlikely(!work))
  488. return;
  489. avalon = thr->cgpu;
  490. info = avalon_info[avalon->device_id];
  491. for (i = 0; i < info->miner_count; i++)
  492. if (likely(work[i])) {
  493. free_work(work[i]);
  494. work[i] = NULL;
  495. }
  496. }
  497. static void do_avalon_close(struct thr_info *thr)
  498. {
  499. struct cgpu_info *avalon = thr->cgpu;
  500. struct avalon_info *info = avalon_info[avalon->device_id];
  501. avalon_close(avalon->device_fd);
  502. avalon->device_fd = -1;
  503. info->no_matching_work = 0;
  504. avalon_free_work(thr, info->bulk0);
  505. avalon_free_work(thr, info->bulk1);
  506. avalon_free_work(thr, info->bulk2);
  507. avalon_free_work(thr, info->bulk3);
  508. }
  509. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  510. __maybe_unused int64_t max_nonce)
  511. {
  512. struct cgpu_info *avalon;
  513. int fd, ret, full;
  514. struct avalon_info *info;
  515. struct avalon_task at;
  516. struct avalon_result ar;
  517. int i, work_i0, work_i1, work_i2, work_i3;
  518. int avalon_get_work_count;
  519. struct timeval tv_start, tv_finish, elapsed;
  520. uint32_t nonce;
  521. int64_t hash_count;
  522. static int first_try = 0;
  523. avalon = thr->cgpu;
  524. info = avalon_info[avalon->device_id];
  525. avalon_get_work_count = info->miner_count;
  526. if (unlikely(avalon->device_fd == -1))
  527. if (!avalon_prepare(thr)) {
  528. applog(LOG_ERR, "AVA%i: Comms error(open)",
  529. avalon->device_id);
  530. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  531. /* fail the device if the reopen attempt fails */
  532. return -1;
  533. }
  534. fd = avalon->device_fd;
  535. #ifndef WIN32
  536. tcflush(fd, TCOFLUSH);
  537. #endif
  538. for (i = 0; i < avalon_get_work_count; i++) {
  539. info->bulk0[i] = info->bulk1[i];
  540. info->bulk1[i] = info->bulk2[i];
  541. info->bulk2[i] = info->bulk3[i];
  542. info->bulk3[i] = work[i];
  543. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p",
  544. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  545. }
  546. i = 0;
  547. while (true) {
  548. avalon_init_task(thr, &at, 0, 0, 0, 0, 0, 0, 1);
  549. avalon_create_task(&at, work[i]);
  550. ret = avalon_send_task(fd, &at, thr);
  551. if (unlikely(ret == AVA_SEND_ERROR ||
  552. (ret == AVA_SEND_BUFFER_EMPTY &&
  553. (i + 1 == avalon_get_work_count) &&
  554. first_try))) {
  555. avalon_free_work(thr, info->bulk0);
  556. avalon_free_work(thr, info->bulk1);
  557. avalon_free_work(thr, info->bulk2);
  558. avalon_free_work(thr, info->bulk3);
  559. do_avalon_close(thr);
  560. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  561. avalon->device_id);
  562. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  563. first_try = 0;
  564. sleep(1);
  565. return 0; /* This should never happen */
  566. }
  567. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  568. first_try = 1;
  569. return 0xffffffff;
  570. }
  571. work[i]->blk.nonce = 0xffffffff;
  572. if (ret == AVA_SEND_BUFFER_FULL)
  573. break;
  574. i++;
  575. }
  576. if (unlikely(first_try))
  577. first_try = 0;
  578. elapsed.tv_sec = elapsed.tv_usec = 0;
  579. gettimeofday(&tv_start, NULL);
  580. hash_count = 0;
  581. while (true) {
  582. work_i0 = work_i1 = work_i2 = -1;
  583. full = avalon_buffer_full(fd);
  584. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  585. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  586. if (unlikely(full == AVA_BUFFER_EMPTY))
  587. break;
  588. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  589. if (unlikely(ret == AVA_GETS_ERROR)) {
  590. avalon_free_work(thr, info->bulk0);
  591. avalon_free_work(thr, info->bulk1);
  592. avalon_free_work(thr, info->bulk2);
  593. avalon_free_work(thr, info->bulk3);
  594. do_avalon_close(thr);
  595. applog(LOG_ERR,
  596. "AVA%i: Comms error(read)", avalon->device_id);
  597. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  598. return 0;
  599. }
  600. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  601. timersub(&tv_finish, &tv_start, &elapsed);
  602. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  603. elapsed.tv_sec, elapsed.tv_usec);
  604. continue;
  605. }
  606. if (unlikely(ret == AVA_GETS_RESTART)) {
  607. avalon_free_work(thr, info->bulk0);
  608. avalon_free_work(thr, info->bulk1);
  609. avalon_free_work(thr, info->bulk2);
  610. avalon_free_work(thr, info->bulk3);
  611. continue;
  612. }
  613. avalon->temp = (ar.temp0 + ar.temp1 + ar.temp2) / 3;
  614. info->fan0 = ar.fan0;
  615. info->fan1 = ar.fan1;
  616. info->fan2 = ar.fan2;
  617. info->temp0 = ar.temp0;
  618. info->temp1 = ar.temp1;
  619. info->temp2 = ar.temp2;
  620. if (info->temp0 > info->temp_max)
  621. info->temp_max = info->temp0;
  622. if (info->temp1 > info->temp_max)
  623. info->temp_max = info->temp1;
  624. if (info->temp2 > info->temp_max)
  625. info->temp_max = info->temp2;
  626. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  627. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  628. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  629. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  630. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  631. if (opt_debug) {
  632. timersub(&tv_finish, &tv_start, &elapsed);
  633. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  634. " (%ld.%06lds)", ++info->no_matching_work,
  635. elapsed.tv_sec, elapsed.tv_usec);
  636. }
  637. continue;
  638. }
  639. if (work_i0 >= 0)
  640. submit_nonce(thr, info->bulk0[work_i0], nonce);
  641. if (work_i1 >= 0)
  642. submit_nonce(thr, info->bulk1[work_i1], nonce);
  643. if (work_i2 >= 0)
  644. submit_nonce(thr, info->bulk2[work_i2], nonce);
  645. if (work_i3 >= 0)
  646. submit_nonce(thr, info->bulk3[work_i3], nonce);
  647. hash_count += nonce;
  648. if (opt_debug) {
  649. timersub(&tv_finish, &tv_start, &elapsed);
  650. applog(LOG_DEBUG,
  651. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  652. "(%ld.%06lds)", nonce, hash_count,
  653. elapsed.tv_sec, elapsed.tv_usec);
  654. }
  655. }
  656. avalon_free_work(thr, info->bulk0);
  657. applog(LOG_WARNING,
  658. "Avalon: Fan1: %d, Fan2: %d, Fan3: %d\t"
  659. "Temp1: %d, Temp2: %d, Temp3: %d, TempMAX: %d",
  660. info->fan0, info->fan1, info->fan2,
  661. info->temp0, info->temp1, info->temp2, info->temp_max);
  662. /*
  663. * FIXME: Each work split to 10 pieces, each piece send to a
  664. * asic(256MHs). one work can be mulit-nonce back. it is not
  665. * easy calculate correct hash on such situation. so I simplely
  666. * add each nonce to hash_count. base on Utility/m hash_count*2
  667. * give a very good result.
  668. *
  669. * Any patch will be great.
  670. */
  671. return (hash_count * 2);
  672. }
  673. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  674. {
  675. struct api_data *root = NULL;
  676. struct avalon_info *info = avalon_info[cgpu->device_id];
  677. root = api_add_int(root, "read_count", &(info->read_count), false);
  678. root = api_add_int(root, "baud", &(info->baud), false);
  679. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  680. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  681. root = api_add_int(root, "fan1", &(info->fan0), false);
  682. root = api_add_int(root, "fan2", &(info->fan1), false);
  683. root = api_add_int(root, "fan3", &(info->fan2), false);
  684. root = api_add_int(root, "temp1", &(info->temp0), false);
  685. root = api_add_int(root, "temp2", &(info->temp1), false);
  686. root = api_add_int(root, "temp3", &(info->temp2), false);
  687. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  688. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  689. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  690. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  691. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  692. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  693. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  694. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  695. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  696. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  697. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  698. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  699. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  700. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  701. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  702. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  703. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  704. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  705. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  706. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  707. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  708. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  709. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  710. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  711. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  712. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  713. return root;
  714. }
  715. static void avalon_shutdown(struct thr_info *thr)
  716. {
  717. do_avalon_close(thr);
  718. }
  719. struct device_api avalon_api = {
  720. .dname = "avalon",
  721. .name = "AVA",
  722. .api_detect = avalon_detect,
  723. .thread_prepare = avalon_prepare,
  724. .scanhash_queue = avalon_scanhash,
  725. .get_api_stats = avalon_api_stats,
  726. .thread_shutdown = avalon_shutdown,
  727. };