driver-avalon.c 29 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. static int option_offset = -1;
  40. struct device_drv avalon_drv;
  41. static int avalon_init_task(struct avalon_task *at,
  42. uint8_t reset, uint8_t ff, uint8_t fan,
  43. uint8_t timeout, uint8_t asic_num,
  44. uint8_t miner_num, uint8_t nonce_elf,
  45. uint8_t gate_miner, int frequency)
  46. {
  47. uint8_t *buf;
  48. static bool first = true;
  49. if (unlikely(!at))
  50. return -1;
  51. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  52. return -1;
  53. memset(at, 0, sizeof(struct avalon_task));
  54. if (unlikely(reset)) {
  55. at->reset = 1;
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = true;
  59. }
  60. at->flush_fifo = (ff ? 1 : 0);
  61. at->fan_eft = (fan ? 1 : 0);
  62. if (unlikely(first && !at->reset)) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  68. at->timeout_data = timeout;
  69. at->asic_num = asic_num;
  70. at->miner_num = miner_num;
  71. at->nonce_elf = nonce_elf;
  72. at->gate_miner_elf = 1;
  73. at->asic_pll = 1;
  74. if (unlikely(gate_miner)) {
  75. at-> gate_miner = 1;
  76. at->asic_pll = 0;
  77. }
  78. buf = (uint8_t *)at;
  79. buf[5] = 0x00;
  80. buf[8] = 0x74;
  81. buf[9] = 0x01;
  82. buf[10] = 0x00;
  83. buf[11] = 0x00;
  84. if (frequency == 256) {
  85. buf[6] = 0x03;
  86. buf[7] = 0x08;
  87. } else if (frequency == 270) {
  88. buf[6] = 0x73;
  89. buf[7] = 0x08;
  90. } else if (frequency == 282) {
  91. buf[6] = 0xd3;
  92. buf[7] = 0x08;
  93. } else if (frequency == 300) {
  94. buf[6] = 0x63;
  95. buf[7] = 0x09;
  96. }
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  106. {
  107. int err, amount;
  108. err = usb_write(avalon, buf, len, &amount, ep);
  109. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  110. avalon->device_id, err);
  111. if (unlikely(err != 0)) {
  112. applog(LOG_WARNING, "usb_write error on avalon_write");
  113. return AVA_SEND_ERROR;
  114. }
  115. if (amount != len) {
  116. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  117. return AVA_SEND_ERROR;
  118. }
  119. return AVA_SEND_OK;
  120. }
  121. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  122. {
  123. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  124. int delay, ret, i, ep = C_AVALON_TASK;
  125. struct avalon_info *info;
  126. uint32_t nonce_range;
  127. size_t nr_len;
  128. if (at->nonce_elf)
  129. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  130. else
  131. nr_len = AVALON_WRITE_SIZE;
  132. memcpy(buf, at, AVALON_WRITE_SIZE);
  133. if (at->nonce_elf) {
  134. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  135. for (i = 0; i < at->asic_num; i++) {
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  137. (i * nonce_range & 0xff000000) >> 24;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  139. (i * nonce_range & 0x00ff0000) >> 16;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  141. (i * nonce_range & 0x0000ff00) >> 8;
  142. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  143. (i * nonce_range & 0x000000ff) >> 0;
  144. }
  145. }
  146. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  147. uint8_t tt = 0;
  148. tt = (buf[0] & 0x0f) << 4;
  149. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  150. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  151. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  152. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  153. buf[0] = tt;
  154. tt = (buf[4] & 0x0f) << 4;
  155. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  156. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  157. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  158. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  159. buf[4] = tt;
  160. #endif
  161. info = avalon->device_data;
  162. delay = nr_len * 10 * 1000000;
  163. delay = delay / info->baud;
  164. if (at->reset) {
  165. ep = C_AVALON_RESET;
  166. nr_len = 1;
  167. }
  168. if (opt_debug) {
  169. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  170. hexdump(buf, nr_len);
  171. }
  172. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  173. delay += 4000;
  174. nusleep(delay);
  175. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  176. return ret;
  177. }
  178. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  179. struct avalon_info *info, struct avalon_result *ar,
  180. struct work *work)
  181. {
  182. uint32_t nonce;
  183. info = avalon->device_data;
  184. info->matching_work[work->subid]++;
  185. nonce = htole32(ar->nonce);
  186. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  187. return submit_nonce(thr, work, nonce);
  188. }
  189. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  190. static void wait_avalon_ready(struct cgpu_info *avalon)
  191. {
  192. while (avalon_buffer_full(avalon)) {
  193. nmsleep(40);
  194. }
  195. }
  196. #define AVALON_CTS (1 << 4)
  197. static inline bool avalon_cts(char c)
  198. {
  199. return (c & AVALON_CTS);
  200. }
  201. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  202. size_t bufsize, int timeout, int ep)
  203. {
  204. struct avalon_info *info = avalon->device_data;
  205. size_t total = 0, readsize = bufsize + 2;
  206. char readbuf[AVALON_READBUF_SIZE];
  207. int err, amount, ofs = 2, cp;
  208. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  209. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  210. avalon->drv->name, avalon->device_id, err);
  211. if (amount < 2)
  212. goto out;
  213. /* Use the fact that we're reading the status with the buffer to tell
  214. * the write thread it should send more work without needing to call
  215. * avalon_buffer_full directly. */
  216. if (avalon_cts(buf[0]))
  217. cgsem_post(&info->write_sem);
  218. /* The first 2 of every 64 bytes are status on FTDIRL */
  219. while (amount > 2) {
  220. cp = amount - 2;
  221. if (cp > 62)
  222. cp = 62;
  223. memcpy(&buf[total], &readbuf[ofs], cp);
  224. total += cp;
  225. amount -= cp + 2;
  226. ofs += 64;
  227. }
  228. out:
  229. return total;
  230. }
  231. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  232. {
  233. struct avalon_result ar;
  234. int ret, i, spare;
  235. struct avalon_task at;
  236. uint8_t *buf, *tmp;
  237. struct timespec p;
  238. /* Send reset, then check for result */
  239. avalon_init_task(&at, 1, 0,
  240. AVALON_DEFAULT_FAN_MAX_PWM,
  241. AVALON_DEFAULT_TIMEOUT,
  242. AVALON_DEFAULT_ASIC_NUM,
  243. AVALON_DEFAULT_MINER_NUM,
  244. 0, 0,
  245. AVALON_DEFAULT_FREQUENCY);
  246. wait_avalon_ready(avalon);
  247. ret = avalon_send_task(&at, avalon);
  248. if (unlikely(ret == AVA_SEND_ERROR))
  249. return -1;
  250. if (!initial) {
  251. applog(LOG_ERR, "AVA%d reset sequence sent", avalon->device_id);
  252. return 0;
  253. }
  254. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  255. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  256. /* What do these sleeps do?? */
  257. p.tv_sec = 0;
  258. p.tv_nsec = AVALON_RESET_PITCH;
  259. nanosleep(&p, NULL);
  260. /* Look for the first occurrence of 0xAA, the reset response should be:
  261. * AA 55 AA 55 00 00 00 00 00 00 */
  262. spare = ret - 10;
  263. buf = tmp = (uint8_t *)&ar;
  264. if (opt_debug) {
  265. applog(LOG_DEBUG, "AVA%d reset: get:", avalon->device_id);
  266. hexdump(tmp, AVALON_READ_SIZE);
  267. }
  268. for (i = 0; i <= spare; i++) {
  269. buf = &tmp[i];
  270. if (buf[0] == 0xAA)
  271. break;
  272. }
  273. i = 0;
  274. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  275. buf[2] == 0xAA && buf[3] == 0x55) {
  276. for (i = 4; i < 11; i++)
  277. if (buf[i] != 0)
  278. break;
  279. }
  280. if (i != 11) {
  281. applog(LOG_ERR, "AVA%d: Reset failed! not an Avalon?"
  282. " (%d: %02x %02x %02x %02x)", avalon->device_id,
  283. i, buf[0], buf[1], buf[2], buf[3]);
  284. /* FIXME: return 1; */
  285. } else
  286. applog(LOG_WARNING, "AVA%d: Reset succeeded",
  287. avalon->device_id);
  288. return 0;
  289. }
  290. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  291. int *asic_count, int *timeout, int *frequency)
  292. {
  293. char buf[BUFSIZ+1];
  294. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  295. size_t max;
  296. int i, tmp;
  297. if (opt_avalon_options == NULL)
  298. buf[0] = '\0';
  299. else {
  300. ptr = opt_avalon_options;
  301. for (i = 0; i < this_option_offset; i++) {
  302. comma = strchr(ptr, ',');
  303. if (comma == NULL)
  304. break;
  305. ptr = comma + 1;
  306. }
  307. comma = strchr(ptr, ',');
  308. if (comma == NULL)
  309. max = strlen(ptr);
  310. else
  311. max = comma - ptr;
  312. if (max > BUFSIZ)
  313. max = BUFSIZ;
  314. strncpy(buf, ptr, max);
  315. buf[max] = '\0';
  316. }
  317. if (!(*buf))
  318. return false;
  319. colon = strchr(buf, ':');
  320. if (colon)
  321. *(colon++) = '\0';
  322. tmp = atoi(buf);
  323. switch (tmp) {
  324. case 115200:
  325. *baud = 115200;
  326. break;
  327. case 57600:
  328. *baud = 57600;
  329. break;
  330. case 38400:
  331. *baud = 38400;
  332. break;
  333. case 19200:
  334. *baud = 19200;
  335. break;
  336. default:
  337. quit(1, "Invalid avalon-options for baud (%s) "
  338. "must be 115200, 57600, 38400 or 19200", buf);
  339. }
  340. if (colon && *colon) {
  341. colon2 = strchr(colon, ':');
  342. if (colon2)
  343. *(colon2++) = '\0';
  344. if (*colon) {
  345. tmp = atoi(colon);
  346. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  347. *miner_count = tmp;
  348. } else {
  349. quit(1, "Invalid avalon-options for "
  350. "miner_count (%s) must be 1 ~ %d",
  351. colon, AVALON_DEFAULT_MINER_NUM);
  352. }
  353. }
  354. if (colon2 && *colon2) {
  355. colon3 = strchr(colon2, ':');
  356. if (colon3)
  357. *(colon3++) = '\0';
  358. tmp = atoi(colon2);
  359. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  360. *asic_count = tmp;
  361. else {
  362. quit(1, "Invalid avalon-options for "
  363. "asic_count (%s) must be 1 ~ %d",
  364. colon2, AVALON_DEFAULT_ASIC_NUM);
  365. }
  366. if (colon3 && *colon3) {
  367. colon4 = strchr(colon3, ':');
  368. if (colon4)
  369. *(colon4++) = '\0';
  370. tmp = atoi(colon3);
  371. if (tmp > 0 && tmp <= 0xff)
  372. *timeout = tmp;
  373. else {
  374. quit(1, "Invalid avalon-options for "
  375. "timeout (%s) must be 1 ~ %d",
  376. colon3, 0xff);
  377. }
  378. if (colon4 && *colon4) {
  379. tmp = atoi(colon4);
  380. switch (tmp) {
  381. case 256:
  382. case 270:
  383. case 282:
  384. case 300:
  385. *frequency = tmp;
  386. break;
  387. default:
  388. quit(1, "Invalid avalon-options for "
  389. "frequency must be 256/270/282/300");
  390. }
  391. }
  392. }
  393. }
  394. }
  395. return true;
  396. }
  397. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  398. {
  399. int i;
  400. info->idle = true;
  401. wait_avalon_ready(avalon);
  402. /* Send idle to all miners */
  403. for (i = 0; i < info->miner_count; i++) {
  404. struct avalon_task at;
  405. if (unlikely(avalon_buffer_full(avalon)))
  406. break;
  407. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  408. info->asic_count, info->miner_count, 1, 1,
  409. info->frequency);
  410. avalon_send_task(&at, avalon);
  411. }
  412. applog(LOG_WARNING, "AVA%i: Idling %d miners", avalon->device_id, i);
  413. wait_avalon_ready(avalon);
  414. }
  415. static void avalon_initialise(struct cgpu_info *avalon)
  416. {
  417. int err, interface;
  418. if (avalon->usbinfo.nodev)
  419. return;
  420. interface = avalon->usbdev->found->interface;
  421. // Reset
  422. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  423. FTDI_VALUE_RESET, interface, C_RESET);
  424. applog(LOG_DEBUG, "%s%i: reset got err %d",
  425. avalon->drv->name, avalon->device_id, err);
  426. if (avalon->usbinfo.nodev)
  427. return;
  428. // Set latency
  429. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  430. AVALON_LATENCY, interface, C_LATENCY);
  431. applog(LOG_DEBUG, "%s%i: latency got err %d",
  432. avalon->drv->name, avalon->device_id, err);
  433. if (avalon->usbinfo.nodev)
  434. return;
  435. // Set data
  436. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  437. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  438. applog(LOG_DEBUG, "%s%i: data got err %d",
  439. avalon->drv->name, avalon->device_id, err);
  440. if (avalon->usbinfo.nodev)
  441. return;
  442. // Set the baud
  443. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  444. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  445. C_SETBAUD);
  446. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  447. avalon->drv->name, avalon->device_id, err);
  448. if (avalon->usbinfo.nodev)
  449. return;
  450. // Set Modem Control
  451. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  452. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  453. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  454. avalon->drv->name, avalon->device_id, err);
  455. if (avalon->usbinfo.nodev)
  456. return;
  457. // Set Flow Control
  458. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  459. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  460. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  461. avalon->drv->name, avalon->device_id, err);
  462. if (avalon->usbinfo.nodev)
  463. return;
  464. /* Avalon repeats the following */
  465. // Set Modem Control
  466. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  467. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  468. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  469. avalon->drv->name, avalon->device_id, err);
  470. if (avalon->usbinfo.nodev)
  471. return;
  472. // Set Flow Control
  473. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  474. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  475. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  476. avalon->drv->name, avalon->device_id, err);
  477. }
  478. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  479. {
  480. int baud, miner_count, asic_count, timeout, frequency = 0;
  481. int this_option_offset = ++option_offset;
  482. struct avalon_info *info;
  483. struct cgpu_info *avalon;
  484. bool configured;
  485. int ret;
  486. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  487. configured = get_options(this_option_offset, &baud, &miner_count,
  488. &asic_count, &timeout, &frequency);
  489. if (!usb_init(avalon, dev, found))
  490. goto shin;
  491. /* Even though this is an FTDI type chip, we want to do the parsing
  492. * all ourselves so set it to std usb type */
  493. avalon->usbdev->usb_type = USB_TYPE_STD;
  494. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  495. /* We have a real Avalon! */
  496. avalon_initialise(avalon);
  497. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  498. if (unlikely(!(avalon->device_data)))
  499. quit(1, "Failed to calloc avalon_info data");
  500. info = avalon->device_data;
  501. if (configured) {
  502. info->baud = baud;
  503. info->miner_count = miner_count;
  504. info->asic_count = asic_count;
  505. info->timeout = timeout;
  506. info->frequency = frequency;
  507. } else {
  508. info->baud = AVALON_IO_SPEED;
  509. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  510. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  511. info->timeout = AVALON_DEFAULT_TIMEOUT;
  512. info->frequency = AVALON_DEFAULT_FREQUENCY;
  513. }
  514. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  515. info->temp_max = 0;
  516. /* This is for check the temp/fan every 3~4s */
  517. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  518. if (info->temp_history_count <= 0)
  519. info->temp_history_count = 1;
  520. info->temp_history_index = 0;
  521. info->temp_sum = 0;
  522. info->temp_old = 0;
  523. if (!add_cgpu(avalon))
  524. goto unshin;
  525. ret = avalon_reset(avalon, true);
  526. if (ret && !configured)
  527. goto unshin;
  528. update_usb_stats(avalon);
  529. avalon_idle(avalon, info);
  530. applog(LOG_DEBUG, "Avalon Detected: %s "
  531. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  532. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  533. info->frequency);
  534. return true;
  535. unshin:
  536. usb_uninit(avalon);
  537. shin:
  538. free(avalon->device_data);
  539. avalon->device_data = NULL;
  540. avalon = usb_free_cgpu(avalon);
  541. return false;
  542. }
  543. static void avalon_detect(void)
  544. {
  545. usb_detect(&avalon_drv, avalon_detect_one);
  546. }
  547. static void avalon_init(struct cgpu_info *avalon)
  548. {
  549. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  550. }
  551. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  552. {
  553. return find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  554. (char *)ar->data, 64, 12);
  555. }
  556. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  557. struct avalon_result *ar);
  558. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  559. {
  560. if (unlikely(info->idle))
  561. return;
  562. applog(LOG_WARNING, "%s%d: No matching work - HW error",
  563. thr->cgpu->drv->name, thr->cgpu->device_id);
  564. inc_hw_errors(thr);
  565. info->no_matching_work++;
  566. }
  567. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  568. struct thr_info *thr, char *buf, int *offset)
  569. {
  570. int i, spare = *offset - AVALON_READ_SIZE;
  571. bool found = false;
  572. for (i = 0; i <= spare; i++) {
  573. struct avalon_result *ar;
  574. struct work *work;
  575. ar = (struct avalon_result *)&buf[i];
  576. work = avalon_valid_result(avalon, ar);
  577. if (work) {
  578. bool gettemp = false;
  579. found = true;
  580. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  581. mutex_lock(&info->lock);
  582. if (!info->nonces++)
  583. gettemp = true;
  584. mutex_unlock(&info->lock);
  585. }
  586. if (gettemp)
  587. avalon_update_temps(avalon, info, ar);
  588. break;
  589. }
  590. }
  591. if (!found) {
  592. spare = *offset - AVALON_READ_SIZE;
  593. /* We are buffering and haven't accumulated one more corrupt
  594. * work result. */
  595. if (spare < (int)AVALON_READ_SIZE)
  596. return;
  597. avalon_inc_nvw(info, thr);
  598. } else {
  599. spare = AVALON_READ_SIZE + i;
  600. if (i) {
  601. if (i >= (int)AVALON_READ_SIZE)
  602. avalon_inc_nvw(info, thr);
  603. else
  604. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  605. }
  606. }
  607. *offset -= spare;
  608. memmove(buf, buf + spare, *offset);
  609. }
  610. static void avalon_running_reset(struct cgpu_info *avalon,
  611. struct avalon_info *info)
  612. {
  613. avalon_reset(avalon, false);
  614. avalon_idle(avalon, info);
  615. avalon->results = 0;
  616. info->reset = false;
  617. }
  618. static void *avalon_get_results(void *userdata)
  619. {
  620. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  621. struct avalon_info *info = avalon->device_data;
  622. int offset = 0, read_delay = 0, ret = 0;
  623. const int rsize = AVALON_FTDI_READSIZE;
  624. char readbuf[AVALON_READBUF_SIZE];
  625. struct thr_info *thr = info->thr;
  626. struct timeval tv_start, tv_end;
  627. char threadname[24];
  628. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  629. RenameThread(threadname);
  630. while (likely(!avalon->shutdown)) {
  631. unsigned char buf[rsize];
  632. struct timeval tv_diff;
  633. int us_diff;
  634. if (offset >= (int)AVALON_READ_SIZE)
  635. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  636. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  637. /* This should never happen */
  638. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  639. offset = 0;
  640. }
  641. if (unlikely(info->reset)) {
  642. avalon_running_reset(avalon, info);
  643. /* Discard anything in the buffer */
  644. offset = 0;
  645. }
  646. /* As the usb read returns after just 1ms, sleep long enough
  647. * to leave the interface idle for writes to occur, but do not
  648. * sleep if we have been receiving data as more may be coming. */
  649. if (ret < 1) {
  650. cgtime(&tv_end);
  651. timersub(&tv_end, &tv_start, &tv_diff);
  652. /* Assume it has not been > 1 second so ignore tv_sec */
  653. us_diff = tv_diff.tv_usec;
  654. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  655. if (likely(read_delay >= 1000))
  656. nusleep(read_delay);
  657. }
  658. cgtime(&tv_start);
  659. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  660. C_AVALON_READ);
  661. if (ret < 1)
  662. continue;
  663. if (opt_debug) {
  664. applog(LOG_DEBUG, "Avalon: get:");
  665. hexdump((uint8_t *)buf, ret);
  666. }
  667. memcpy(&readbuf[offset], &buf, ret);
  668. offset += ret;
  669. }
  670. return NULL;
  671. }
  672. static void avalon_rotate_array(struct cgpu_info *avalon)
  673. {
  674. avalon->queued = 0;
  675. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  676. avalon->work_array = 0;
  677. }
  678. static void *avalon_send_tasks(void *userdata)
  679. {
  680. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  681. struct avalon_info *info = avalon->device_data;
  682. const int avalon_get_work_count = info->miner_count;
  683. char threadname[24];
  684. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  685. RenameThread(threadname);
  686. while (likely(!avalon->shutdown)) {
  687. int start_count, end_count, i, j, ret;
  688. struct avalon_task at;
  689. int idled = 0;
  690. while (avalon_buffer_full(avalon))
  691. cgsem_wait(&info->write_sem);
  692. mutex_lock(&info->qlock);
  693. start_count = avalon->work_array * avalon_get_work_count;
  694. end_count = start_count + avalon_get_work_count;
  695. for (i = start_count, j = 0; i < end_count; i++, j++) {
  696. if (avalon_buffer_full(avalon)) {
  697. applog(LOG_INFO,
  698. "AVA%i: Buffer full after only %d of %d work queued",
  699. avalon->device_id, j, avalon_get_work_count);
  700. break;
  701. }
  702. if (likely(j < avalon->queued)) {
  703. info->idle = false;
  704. avalon_init_task(&at, 0, 0, info->fan_pwm,
  705. info->timeout, info->asic_count,
  706. info->miner_count, 1, 0, info->frequency);
  707. avalon_create_task(&at, avalon->works[i]);
  708. } else {
  709. idled++;
  710. avalon_init_task(&at, 0, 0, info->fan_pwm,
  711. info->timeout, info->asic_count,
  712. info->miner_count, 1, 1, info->frequency);
  713. }
  714. ret = avalon_send_task(&at, avalon);
  715. if (unlikely(ret == AVA_SEND_ERROR)) {
  716. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  717. avalon->device_id);
  718. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  719. info->reset = true;
  720. break;
  721. }
  722. }
  723. avalon_rotate_array(avalon);
  724. pthread_cond_signal(&info->qcond);
  725. mutex_unlock(&info->qlock);
  726. if (unlikely(idled && !info->idle)) {
  727. info->idle = true;
  728. applog(LOG_WARNING, "AVA%i: Idled %d miners",
  729. avalon->device_id, idled);
  730. }
  731. }
  732. return NULL;
  733. }
  734. static bool avalon_prepare(struct thr_info *thr)
  735. {
  736. struct cgpu_info *avalon = thr->cgpu;
  737. struct avalon_info *info = avalon->device_data;
  738. struct timeval now;
  739. free(avalon->works);
  740. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  741. AVALON_ARRAY_SIZE);
  742. if (!avalon->works)
  743. quit(1, "Failed to calloc avalon works in avalon_prepare");
  744. info->thr = thr;
  745. mutex_init(&info->lock);
  746. mutex_init(&info->qlock);
  747. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  748. quit(1, "Failed to pthread_cond_init avalon qcond");
  749. cgsem_init(&info->write_sem);
  750. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  751. quit(1, "Failed to create avalon read_thr");
  752. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  753. quit(1, "Failed to create avalon write_thr");
  754. avalon_init(avalon);
  755. cgtime(&now);
  756. get_datestamp(avalon->init, &now);
  757. return true;
  758. }
  759. static void do_avalon_close(struct thr_info *thr)
  760. {
  761. struct cgpu_info *avalon = thr->cgpu;
  762. struct avalon_info *info = avalon->device_data;
  763. pthread_join(info->read_thr, NULL);
  764. pthread_join(info->write_thr, NULL);
  765. avalon_running_reset(avalon, info);
  766. info->no_matching_work = 0;
  767. cgsem_destroy(&info->write_sem);
  768. }
  769. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  770. {
  771. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  772. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  773. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  774. info->temp0 = ar->temp0;
  775. info->temp1 = ar->temp1;
  776. info->temp2 = ar->temp2;
  777. if (ar->temp0 & 0x80) {
  778. ar->temp0 &= 0x7f;
  779. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  780. }
  781. if (ar->temp1 & 0x80) {
  782. ar->temp1 &= 0x7f;
  783. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  784. }
  785. if (ar->temp2 & 0x80) {
  786. ar->temp2 &= 0x7f;
  787. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  788. }
  789. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  790. if (info->temp0 > info->temp_max)
  791. info->temp_max = info->temp0;
  792. if (info->temp1 > info->temp_max)
  793. info->temp_max = info->temp1;
  794. if (info->temp2 > info->temp_max)
  795. info->temp_max = info->temp2;
  796. }
  797. static inline void adjust_fan(struct avalon_info *info)
  798. {
  799. int temp_new;
  800. temp_new = info->temp_sum / info->temp_history_count;
  801. if (temp_new < 35) {
  802. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  803. info->temp_old = temp_new;
  804. } else if (temp_new > 55) {
  805. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  806. info->temp_old = temp_new;
  807. } else if (abs(temp_new - info->temp_old) >= 2) {
  808. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  809. info->temp_old = temp_new;
  810. }
  811. }
  812. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  813. struct avalon_result *ar)
  814. {
  815. record_temp_fan(info, ar, &(avalon->temp));
  816. applog(LOG_INFO,
  817. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  818. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  819. info->fan0, info->fan1, info->fan2,
  820. info->temp0, info->temp1, info->temp2, info->temp_max);
  821. info->temp_history_index++;
  822. info->temp_sum += avalon->temp;
  823. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  824. info->temp_history_index, info->temp_history_count, info->temp_old);
  825. if (info->temp_history_index == info->temp_history_count) {
  826. adjust_fan(info);
  827. info->temp_history_index = 0;
  828. info->temp_sum = 0;
  829. }
  830. }
  831. static void get_avalon_statline_before(char *buf, struct cgpu_info *avalon)
  832. {
  833. struct avalon_info *info = avalon->device_data;
  834. int lowfan = 10000;
  835. /* Find the lowest fan speed of the ASIC cooling fans. */
  836. if (info->fan1 >= 0 && info->fan1 < lowfan)
  837. lowfan = info->fan1;
  838. if (info->fan2 >= 0 && info->fan2 < lowfan)
  839. lowfan = info->fan2;
  840. tailsprintf(buf, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  841. }
  842. /* We use a replacement algorithm to only remove references to work done from
  843. * the buffer when we need the extra space for new work. */
  844. static bool avalon_fill(struct cgpu_info *avalon)
  845. {
  846. struct avalon_info *info = avalon->device_data;
  847. int subid, slot, mc;
  848. struct work *work;
  849. bool ret = true;
  850. mc = info->miner_count;
  851. mutex_lock(&info->qlock);
  852. if (avalon->queued >= mc)
  853. goto out_unlock;
  854. work = get_queued(avalon);
  855. if (unlikely(!work)) {
  856. ret = false;
  857. goto out_unlock;
  858. }
  859. subid = avalon->queued++;
  860. work->subid = subid;
  861. slot = avalon->work_array * mc + subid;
  862. if (likely(avalon->works[slot]))
  863. work_completed(avalon, avalon->works[slot]);
  864. avalon->works[slot] = work;
  865. if (avalon->queued < mc)
  866. ret = false;
  867. out_unlock:
  868. mutex_unlock(&info->qlock);
  869. return ret;
  870. }
  871. static int64_t avalon_scanhash(struct thr_info *thr)
  872. {
  873. struct cgpu_info *avalon = thr->cgpu;
  874. struct avalon_info *info = avalon->device_data;
  875. const int miner_count = info->miner_count;
  876. struct timeval now, then, tdiff;
  877. int64_t hash_count, us_timeout;
  878. struct timespec abstime;
  879. /* Half nonce range */
  880. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  881. tdiff.tv_sec = us_timeout / 1000000;
  882. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  883. cgtime(&now);
  884. timeradd(&now, &tdiff, &then);
  885. abstime.tv_sec = then.tv_sec;
  886. abstime.tv_nsec = then.tv_usec * 1000;
  887. /* Wait until avalon_send_tasks signals us that it has completed
  888. * sending its work or a full nonce range timeout has occurred */
  889. mutex_lock(&info->qlock);
  890. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  891. mutex_unlock(&info->qlock);
  892. mutex_lock(&info->lock);
  893. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  894. avalon->results += info->nonces;
  895. if (avalon->results > miner_count)
  896. avalon->results = miner_count;
  897. if (!info->idle && !info->reset)
  898. avalon->results -= miner_count / 3;
  899. else
  900. avalon->results = miner_count;
  901. info->nonces = 0;
  902. mutex_unlock(&info->lock);
  903. /* Check for nothing but consecutive bad results or consistently less
  904. * results than we should be getting and reset the FPGA if necessary */
  905. if (avalon->results < -miner_count && !info->reset) {
  906. applog(LOG_ERR, "AVA%d: Result return rate low, resetting!",
  907. avalon->device_id);
  908. info->reset = true;
  909. }
  910. if (unlikely(avalon->usbinfo.nodev)) {
  911. applog(LOG_ERR, "AVA%d: Device disappeared, shutting down thread",
  912. avalon->device_id);
  913. avalon->shutdown = true;
  914. }
  915. /* This hashmeter is just a utility counter based on returned shares */
  916. return hash_count;
  917. }
  918. static void avalon_flush_work(struct cgpu_info *avalon)
  919. {
  920. struct avalon_info *info = avalon->device_data;
  921. mutex_lock(&info->qlock);
  922. /* Will overwrite any work queued */
  923. avalon->queued = 0;
  924. pthread_cond_signal(&info->qcond);
  925. mutex_unlock(&info->qlock);
  926. }
  927. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  928. {
  929. struct api_data *root = NULL;
  930. struct avalon_info *info = cgpu->device_data;
  931. int i;
  932. root = api_add_int(root, "baud", &(info->baud), false);
  933. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  934. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  935. root = api_add_int(root, "timeout", &(info->timeout), false);
  936. root = api_add_int(root, "frequency", &(info->frequency), false);
  937. root = api_add_int(root, "fan1", &(info->fan0), false);
  938. root = api_add_int(root, "fan2", &(info->fan1), false);
  939. root = api_add_int(root, "fan3", &(info->fan2), false);
  940. root = api_add_int(root, "temp1", &(info->temp0), false);
  941. root = api_add_int(root, "temp2", &(info->temp1), false);
  942. root = api_add_int(root, "temp3", &(info->temp2), false);
  943. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  944. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  945. for (i = 0; i < info->miner_count; i++) {
  946. char mcw[24];
  947. sprintf(mcw, "match_work_count%d", i + 1);
  948. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  949. }
  950. return root;
  951. }
  952. static void avalon_shutdown(struct thr_info *thr)
  953. {
  954. do_avalon_close(thr);
  955. }
  956. struct device_drv avalon_drv = {
  957. .drv_id = DRIVER_AVALON,
  958. .dname = "avalon",
  959. .name = "AVA",
  960. .drv_detect = avalon_detect,
  961. .thread_prepare = avalon_prepare,
  962. .hash_work = hash_queued_work,
  963. .queue_full = avalon_fill,
  964. .scanwork = avalon_scanhash,
  965. .flush_work = avalon_flush_work,
  966. .get_api_stats = avalon_api_stats,
  967. .get_statline_before = get_avalon_statline_before,
  968. .reinit_device = avalon_init,
  969. .thread_shutdown = avalon_shutdown,
  970. };