driver-hashfast.c 18 KB

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  1. /*
  2. * Copyright 2013 Luke Dashjr
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <stdbool.h>
  11. #include <stdint.h>
  12. #include <stdlib.h>
  13. #include <string.h>
  14. #include <unistd.h>
  15. #include <utlist.h>
  16. #include "deviceapi.h"
  17. #include "logging.h"
  18. #include "lowlevel.h"
  19. #include "lowl-vcom.h"
  20. #include "util.h"
  21. BFG_REGISTER_DRIVER(hashfast_ums_drv)
  22. #define HASHFAST_QUEUE_MEMORY 0x20
  23. #define HASHFAST_ALL_CHIPS 0xff
  24. #define HASHFAST_ALL_CORES 0xff
  25. #define HASHFAST_HEADER_SIZE 8
  26. #define HASHFAST_MAX_DATA 0x3fc
  27. #define HASHFAST_HASH_SIZE (0x20 + 0xc + 4 + 4 + 2 + 1 + 1)
  28. #define HASHFAST_MAX_VOLTAGES 4
  29. enum hashfast_opcode {
  30. HFOP_NULL = 0,
  31. HFOP_ROOT = 1,
  32. HFOP_RESET = 2,
  33. HFOP_PLL_CONFIG = 3,
  34. HFOP_ADDRESS = 4,
  35. HFOP_READDRESS = 5,
  36. HFOP_HIGHEST = 6,
  37. HFOP_BAUD = 7,
  38. HFOP_UNROOT = 8,
  39. HFOP_HASH = 9,
  40. HFOP_NONCE = 0x0a,
  41. HFOP_ABORT = 0x0b,
  42. HFOP_STATUS = 0x0c,
  43. HFOP_GPIO = 0x0d,
  44. HFOP_CONFIG = 0x0e,
  45. HFOP_STATISTICS = 0x0f,
  46. HFOP_GROUP = 0x10,
  47. HFOP_CLOCKGATE = 0x11,
  48. HFOP_USB_INIT = 0x80,
  49. HFOP_GET_TRACE = 0x81,
  50. HFOP_LOOPBACK_USB = 0x82,
  51. HFOP_LOOPBACK_UART = 0x83,
  52. HFOP_DFU = 0x84,
  53. HFOP_USB_SHUTDOWN = 0x85,
  54. HFOP_DIE_STATUS = 0x86,
  55. HFOP_GWQ_STATUS = 0x87,
  56. HFOP_WORK_RESTART = 0x88,
  57. HFOP_USB_STATS1 = 0x89,
  58. HFOP_USB_GWQSTATS = 0x8a,
  59. HFOP_USB_NOTICE = 0x8b,
  60. HFOP_USB_DEBUG = 0xff,
  61. };
  62. typedef unsigned long hashfast_isn_t;
  63. static inline
  64. float hashfast_temperature_conv(const uint8_t * const data)
  65. {
  66. // Temperature is 12-bit fraction ranging between -61.5 C and ~178.5 C
  67. uint32_t tempdata = ((uint32_t)data[1] << 8) | data[0];
  68. tempdata &= 0xfff;
  69. tempdata *= 240;
  70. tempdata -= 251904; // 61.5 * 4096
  71. float temp = tempdata;
  72. temp /= 4096.;
  73. return temp;
  74. }
  75. static inline
  76. float hashfast_voltage_conv(const uint8_t vdata)
  77. {
  78. // Voltage is 8-bit fraction ranging between 0 V and ~1.2 V
  79. return (float)vdata / 256. * 1.2;
  80. }
  81. struct hashfast_parsed_msg {
  82. uint8_t opcode;
  83. uint8_t chipaddr;
  84. uint8_t coreaddr;
  85. uint16_t hdata;
  86. uint8_t data[HASHFAST_MAX_DATA];
  87. size_t datalen;
  88. };
  89. static
  90. ssize_t hashfast_write(const int fd, void * const buf, size_t bufsz)
  91. {
  92. const ssize_t rv = write(fd, buf, bufsz);
  93. if (opt_debug && opt_dev_protocol)
  94. {
  95. char hex[(bufsz * 2) + 1];
  96. bin2hex(hex, buf, bufsz);
  97. if (rv < 0)
  98. applog(LOG_DEBUG, "%s fd=%d: SEND (%s) => %d",
  99. "hashfast", fd, hex, (int)rv);
  100. else
  101. if (rv < bufsz)
  102. applog(LOG_DEBUG, "%s fd=%d: SEND %.*s(%s)",
  103. "hashfast", fd, rv * 2, hex, &hex[rv * 2]);
  104. else
  105. if (rv > bufsz)
  106. applog(LOG_DEBUG, "%s fd=%d: SEND %s => +%d",
  107. "hashfast", fd, hex, (int)(rv - bufsz));
  108. else
  109. applog(LOG_DEBUG, "%s fd=%d: SEND %s",
  110. "hashfast", fd, hex);
  111. }
  112. return rv;
  113. }
  114. static
  115. ssize_t hashfast_read(const int fd, void * const buf, size_t bufsz)
  116. {
  117. const ssize_t rv = serial_read(fd, buf, bufsz);
  118. if (opt_debug && opt_dev_protocol && rv)
  119. {
  120. char hex[(rv * 2) + 1];
  121. bin2hex(hex, buf, rv);
  122. applog(LOG_DEBUG, "%s fd=%d: RECV %s",
  123. "hashfast", fd, hex);
  124. }
  125. return rv;
  126. }
  127. static
  128. bool hashfast_prepare_msg(uint8_t * const buf, const uint8_t opcode, const uint8_t chipaddr, const uint8_t coreaddr, const uint16_t hdata, const size_t datalen)
  129. {
  130. buf[0] = '\xaa';
  131. buf[1] = opcode;
  132. buf[2] = chipaddr;
  133. buf[3] = coreaddr;
  134. buf[4] = hdata & 0xff;
  135. buf[5] = hdata >> 8;
  136. if (datalen > 1020 || datalen % 4)
  137. return false;
  138. buf[6] = datalen / 4;
  139. buf[7] = crc8ccitt(&buf[1], 6);
  140. return true;
  141. }
  142. static
  143. bool hashfast_send_msg(const int fd, uint8_t * const buf, const uint8_t opcode, const uint8_t chipaddr, const uint8_t coreaddr, const uint16_t hdata, const size_t datalen)
  144. {
  145. if (!hashfast_prepare_msg(buf, opcode, chipaddr, coreaddr, hdata, datalen))
  146. return false;
  147. const size_t buflen = HASHFAST_HEADER_SIZE + datalen;
  148. return (buflen == hashfast_write(fd, buf, buflen));
  149. }
  150. static
  151. bool hashfast_parse_msg(const int fd, struct hashfast_parsed_msg * const out_msg)
  152. {
  153. uint8_t buf[HASHFAST_HEADER_SIZE];
  154. startover:
  155. if (HASHFAST_HEADER_SIZE != hashfast_read(fd, buf, HASHFAST_HEADER_SIZE))
  156. return false;
  157. uint8_t *p = memchr(buf, '\xaa', HASHFAST_HEADER_SIZE);
  158. if (p != buf)
  159. {
  160. ignoresome:
  161. if (!p)
  162. goto startover;
  163. int moreneeded = p - buf;
  164. int alreadyhave = HASHFAST_HEADER_SIZE - moreneeded;
  165. memmove(buf, p, alreadyhave);
  166. if (moreneeded != hashfast_read(fd, &buf[alreadyhave], moreneeded))
  167. return false;
  168. }
  169. const uint8_t correct_crc8 = crc8ccitt(&buf[1], 6);
  170. if (buf[7] != correct_crc8)
  171. {
  172. p = memchr(&buf[1], '\xaa', HASHFAST_HEADER_SIZE - 1);
  173. goto ignoresome;
  174. }
  175. out_msg->opcode = buf[1];
  176. out_msg->chipaddr = buf[2];
  177. out_msg->coreaddr = buf[3];
  178. out_msg->hdata = (uint16_t)buf[4] | ((uint16_t)buf[5] << 8);
  179. out_msg->datalen = buf[6] * 4;
  180. return (out_msg->datalen == hashfast_read(fd, &out_msg->data[0], out_msg->datalen));
  181. }
  182. static
  183. bool hashfast_lowl_match(const struct lowlevel_device_info * const info)
  184. {
  185. if (!lowlevel_match_id(info, &lowl_vcom, 0, 0))
  186. return false;
  187. return (info->manufacturer && strstr(info->manufacturer, "HashFast"));
  188. }
  189. static
  190. bool hashfast_detect_one(const char * const devpath)
  191. {
  192. uint16_t clock = 550;
  193. uint8_t buf[HASHFAST_HEADER_SIZE];
  194. const int fd = serial_open(devpath, 0, 100, true);
  195. if (fd == -1)
  196. {
  197. applog(LOG_DEBUG, "%s: Failed to open %s", __func__, devpath);
  198. return false;
  199. }
  200. struct hashfast_parsed_msg * const pmsg = malloc(sizeof(*pmsg));
  201. hashfast_send_msg(fd, buf, HFOP_USB_INIT, 0, 0, clock, 0);
  202. do {
  203. if (!hashfast_parse_msg(fd, pmsg))
  204. {
  205. applog(LOG_DEBUG, "%s: Failed to parse response on %s",
  206. __func__, devpath);
  207. serial_close(fd);
  208. goto err;
  209. }
  210. } while (pmsg->opcode != HFOP_USB_INIT);
  211. serial_close(fd);
  212. const int expectlen = 0x20 + (pmsg->chipaddr * pmsg->coreaddr) / 8;
  213. if (pmsg->datalen < expectlen)
  214. {
  215. applog(LOG_DEBUG, "%s: USB_INIT response too short on %s (%d < %d)",
  216. __func__, devpath, (int)pmsg->datalen, expectlen);
  217. goto err;
  218. }
  219. if (pmsg->data[8] != 0)
  220. {
  221. applog(LOG_DEBUG, "%s: USB_INIT failed on %s (err=%d)",
  222. __func__, devpath, pmsg->data[8]);
  223. goto err;
  224. }
  225. struct cgpu_info * const cgpu = malloc(sizeof(*cgpu));
  226. *cgpu = (struct cgpu_info){
  227. .drv = &hashfast_ums_drv,
  228. .device_path = strdup(devpath),
  229. .deven = DEV_ENABLED,
  230. .procs = (pmsg->chipaddr * pmsg->coreaddr),
  231. .threads = 1,
  232. .device_data = pmsg,
  233. };
  234. return add_cgpu(cgpu);
  235. err:
  236. free(pmsg);
  237. return false;
  238. }
  239. static
  240. bool hashfast_lowl_probe(const struct lowlevel_device_info * const info)
  241. {
  242. return vcom_lowl_probe_wrapper(info, hashfast_detect_one);
  243. }
  244. struct hashfast_dev_state {
  245. uint8_t cores_per_chip;
  246. int fd;
  247. struct hashfast_chip_state *chipstates;
  248. };
  249. struct hashfast_chip_state {
  250. struct cgpu_info **coreprocs;
  251. hashfast_isn_t last_isn;
  252. float voltages[HASHFAST_MAX_VOLTAGES];
  253. };
  254. struct hashfast_core_state {
  255. uint8_t chipaddr;
  256. uint8_t coreaddr;
  257. int next_device_id;
  258. uint8_t last_seq;
  259. hashfast_isn_t last_isn;
  260. hashfast_isn_t last2_isn;
  261. bool has_pending;
  262. unsigned queued;
  263. };
  264. static
  265. bool hashfast_init(struct thr_info * const master_thr)
  266. {
  267. struct cgpu_info * const dev = master_thr->cgpu, *proc;
  268. struct hashfast_parsed_msg * const pmsg = dev->device_data;
  269. struct hashfast_dev_state * const devstate = malloc(sizeof(*devstate));
  270. struct hashfast_chip_state * const chipstates = malloc(sizeof(*chipstates) * pmsg->chipaddr), *chipstate;
  271. struct hashfast_core_state * const corestates = malloc(sizeof(*corestates) * dev->procs), *cs;
  272. int i;
  273. *devstate = (struct hashfast_dev_state){
  274. .chipstates = chipstates,
  275. .cores_per_chip = pmsg->coreaddr,
  276. .fd = serial_open(dev->device_path, 0, 1, true),
  277. };
  278. for (i = 0; i < pmsg->chipaddr; ++i)
  279. {
  280. chipstate = &chipstates[i];
  281. *chipstate = (struct hashfast_chip_state){
  282. .coreprocs = malloc(sizeof(struct cgpu_info *) * pmsg->coreaddr),
  283. };
  284. }
  285. for ((i = 0), (proc = dev); proc; ++i, (proc = proc->next_proc))
  286. {
  287. struct thr_info * const thr = proc->thr[0];
  288. const bool core_is_working = pmsg->data[0x20 + (i / 8)] & (1 << (i % 8));
  289. if (!core_is_working)
  290. proc->deven = DEV_RECOVER_DRV;
  291. proc->device_data = devstate;
  292. thr->cgpu_data = cs = &corestates[i];
  293. *cs = (struct hashfast_core_state){
  294. .chipaddr = i / pmsg->coreaddr,
  295. .coreaddr = i % pmsg->coreaddr,
  296. };
  297. chipstates[cs->chipaddr].coreprocs[cs->coreaddr] = proc;
  298. }
  299. free(pmsg);
  300. // TODO: actual clock = [12,13]
  301. timer_set_now(&master_thr->tv_poll);
  302. return true;
  303. }
  304. static
  305. bool hashfast_queue_append(struct thr_info * const thr, struct work * const work)
  306. {
  307. struct cgpu_info * const proc = thr->cgpu;
  308. struct hashfast_dev_state * const devstate = proc->device_data;
  309. const int fd = devstate->fd;
  310. struct hashfast_core_state * const cs = thr->cgpu_data;
  311. struct hashfast_chip_state * const chipstate = &devstate->chipstates[cs->chipaddr];
  312. const size_t cmdlen = HASHFAST_HEADER_SIZE + HASHFAST_HASH_SIZE;
  313. uint8_t cmd[cmdlen];
  314. uint8_t * const hashdata = &cmd[HASHFAST_HEADER_SIZE];
  315. hashfast_isn_t isn;
  316. uint8_t seq;
  317. if (cs->has_pending)
  318. {
  319. thr->queue_full = true;
  320. return false;
  321. }
  322. isn = ++chipstate->last_isn;
  323. seq = ++cs->last_seq;
  324. work->device_id = seq;
  325. cs->last2_isn = cs->last_isn;
  326. cs->last_isn = isn;
  327. hashfast_prepare_msg(cmd, HFOP_HASH, cs->chipaddr, cs->coreaddr, (cs->coreaddr << 8) | seq, 56);
  328. memcpy(&hashdata[ 0], work->midstate, 0x20);
  329. memcpy(&hashdata[0x20], &work->data[64], 0xc);
  330. memset(&hashdata[0x2c], '\0', 0xa); // starting_nonce, nonce_loops, ntime_loops
  331. hashdata[0x36] = 32; // search target (number of zero bits)
  332. hashdata[0x37] = 0;
  333. cs->has_pending = true;
  334. if (cmdlen != hashfast_write(fd, cmd, cmdlen))
  335. return false;
  336. DL_APPEND(thr->work, work);
  337. if (cs->queued > HASHFAST_QUEUE_MEMORY)
  338. {
  339. struct work * const old_work = thr->work;
  340. DL_DELETE(thr->work, old_work);
  341. free_work(old_work);
  342. }
  343. else
  344. ++cs->queued;
  345. return true;
  346. }
  347. static
  348. void hashfast_queue_flush(struct thr_info * const thr)
  349. {
  350. struct cgpu_info * const proc = thr->cgpu;
  351. struct hashfast_dev_state * const devstate = proc->device_data;
  352. const int fd = devstate->fd;
  353. struct hashfast_core_state * const cs = thr->cgpu_data;
  354. uint8_t cmd[HASHFAST_HEADER_SIZE];
  355. uint16_t hdata = 2;
  356. if ((!thr->work) || stale_work(thr->work->prev, true))
  357. {
  358. applog(LOG_DEBUG, "%"PRIpreprv": Flushing both active and pending work",
  359. proc->proc_repr);
  360. hdata |= 1;
  361. }
  362. else
  363. applog(LOG_DEBUG, "%"PRIpreprv": Flushing pending work",
  364. proc->proc_repr);
  365. hashfast_send_msg(fd, cmd, HFOP_ABORT, cs->chipaddr, cs->coreaddr, hdata, 0);
  366. }
  367. static
  368. struct cgpu_info *hashfast_find_proc(struct thr_info * const master_thr, int chipaddr, int coreaddr)
  369. {
  370. struct cgpu_info *proc = master_thr->cgpu;
  371. struct hashfast_dev_state * const devstate = proc->device_data;
  372. if (coreaddr >= devstate->cores_per_chip)
  373. return NULL;
  374. const unsigned chip_count = proc->procs / devstate->cores_per_chip;
  375. if (chipaddr >= chip_count)
  376. return NULL;
  377. struct hashfast_chip_state * const chipstate = &devstate->chipstates[chipaddr];
  378. return chipstate->coreprocs[coreaddr];
  379. }
  380. static
  381. hashfast_isn_t hashfast_get_isn(struct hashfast_chip_state * const chipstate, uint16_t hfseq)
  382. {
  383. const uint8_t coreaddr = hfseq >> 8;
  384. const uint8_t seq = hfseq & 0xff;
  385. struct cgpu_info * const proc = chipstate->coreprocs[coreaddr];
  386. struct thr_info * const thr = proc->thr[0];
  387. struct hashfast_core_state * const cs = thr->cgpu_data;
  388. if (cs->last_seq == seq)
  389. return cs->last_isn;
  390. if (cs->last_seq == (uint8_t)(seq + 1))
  391. return cs->last2_isn;
  392. return 0;
  393. }
  394. static
  395. void hashfast_submit_nonce(struct thr_info * const thr, struct work * const work, const uint32_t nonce, const bool searched)
  396. {
  397. struct cgpu_info * const proc = thr->cgpu;
  398. struct hashfast_core_state * const cs = thr->cgpu_data;
  399. applog(LOG_DEBUG, "%"PRIpreprv": Found nonce for seq %02x (last=%02x): %08lx%s",
  400. proc->proc_repr, (unsigned)work->device_id, (unsigned)cs->last_seq,
  401. (unsigned long)nonce, searched ? " (searched)" : "");
  402. submit_nonce(thr, work, nonce);
  403. }
  404. static
  405. bool hashfast_poll_msg(struct thr_info * const master_thr)
  406. {
  407. struct cgpu_info * const dev = master_thr->cgpu;
  408. struct hashfast_dev_state * const devstate = dev->device_data;
  409. const int fd = devstate->fd;
  410. struct hashfast_parsed_msg msg;
  411. if (!hashfast_parse_msg(fd, &msg))
  412. return false;
  413. switch (msg.opcode)
  414. {
  415. case HFOP_NONCE:
  416. {
  417. const uint8_t *data = msg.data;
  418. for (int i = msg.datalen / 8; i; --i, (data = &data[8]))
  419. {
  420. const uint32_t nonce = (data[0] << 0)
  421. | (data[1] << 8)
  422. | (data[2] << 16)
  423. | (data[3] << 24);
  424. const uint8_t seq = data[4];
  425. const uint8_t coreaddr = data[5];
  426. // uint32_t ntime = data[6] | ((data[7] & 0xf) << 8);
  427. const bool search = data[7] & 0x10;
  428. struct cgpu_info * const proc = hashfast_find_proc(master_thr, msg.chipaddr, coreaddr);
  429. if (unlikely(!proc))
  430. {
  431. applog(LOG_ERR, "%s: Unknown chip/core address %u/%u",
  432. dev->dev_repr, (unsigned)msg.chipaddr, (unsigned)coreaddr);
  433. inc_hw_errors_only(master_thr);
  434. continue;
  435. }
  436. struct thr_info * const thr = proc->thr[0];
  437. struct hashfast_core_state * const cs = thr->cgpu_data;
  438. struct work *work;
  439. DL_SEARCH_SCALAR(thr->work, work, device_id, seq);
  440. if (unlikely(!work))
  441. {
  442. applog(LOG_WARNING, "%"PRIpreprv": Unknown seq %02x (last=%02x)",
  443. proc->proc_repr, (unsigned)seq, (unsigned)cs->last_seq);
  444. inc_hw_errors2(thr, NULL, &nonce);
  445. continue;
  446. }
  447. unsigned nonces_found = 1;
  448. hashfast_submit_nonce(thr, work, nonce, false);
  449. if (search)
  450. {
  451. for (int noffset = 1; noffset <= 0x80; ++noffset)
  452. {
  453. const uint32_t nonce2 = nonce + noffset;
  454. if (test_nonce(work, nonce2, false))
  455. {
  456. hashfast_submit_nonce(thr, work, nonce2, true);
  457. ++nonces_found;
  458. }
  459. }
  460. if (!nonces_found)
  461. {
  462. inc_hw_errors_only(thr);
  463. applog(LOG_WARNING, "%"PRIpreprv": search=1, but failed to turn up any additional solutions",
  464. proc->proc_repr);
  465. }
  466. }
  467. hashes_done2(thr, 0x100000000 * nonces_found, NULL);
  468. }
  469. break;
  470. }
  471. case HFOP_STATUS:
  472. {
  473. const uint8_t *data = &msg.data[8];
  474. struct cgpu_info *proc = hashfast_find_proc(master_thr, msg.chipaddr, 0);
  475. if (unlikely(!proc))
  476. {
  477. applog(LOG_ERR, "%s: Unknown chip address %u",
  478. dev->dev_repr, (unsigned)msg.chipaddr);
  479. inc_hw_errors_only(master_thr);
  480. break;
  481. }
  482. struct hashfast_chip_state * const chipstate = &devstate->chipstates[msg.chipaddr];
  483. hashfast_isn_t isn = hashfast_get_isn(chipstate, msg.hdata);
  484. const float temp = hashfast_temperature_conv(&msg.data[0]);
  485. for (int i = 0; i < HASHFAST_MAX_VOLTAGES; ++i)
  486. chipstate->voltages[i] = hashfast_voltage_conv(msg.data[2 + i]);
  487. int cores_uptodate, cores_active, cores_pending, cores_transitioned;
  488. cores_uptodate = cores_active = cores_pending = cores_transitioned = 0;
  489. for (int i = 0; i < devstate->cores_per_chip; ++i, (proc = proc->next_proc))
  490. {
  491. struct thr_info * const thr = proc->thr[0];
  492. struct hashfast_core_state * const cs = thr->cgpu_data;
  493. const uint8_t bits = data[i / 4] >> (2 * (i % 4));
  494. const bool has_active = bits & 1;
  495. const bool has_pending = bits & 2;
  496. bool try_transition = true;
  497. proc->temp = temp;
  498. if (cs->last_isn <= isn)
  499. ++cores_uptodate;
  500. else
  501. try_transition = false;
  502. if (has_active)
  503. ++cores_active;
  504. if (has_pending)
  505. ++cores_pending;
  506. else
  507. if (try_transition)
  508. {
  509. ++cores_transitioned;
  510. cs->has_pending = false;
  511. thr->queue_full = false;
  512. }
  513. }
  514. applog(LOG_DEBUG, "%s: STATUS from chipaddr=0x%02x with hdata=0x%04x (isn=0x%lx): total=%d uptodate=%d active=%d pending=%d transitioned=%d",
  515. dev->dev_repr, (unsigned)msg.chipaddr, (unsigned)msg.hdata, isn,
  516. devstate->cores_per_chip, cores_uptodate,
  517. cores_active, cores_pending, cores_transitioned);
  518. break;
  519. }
  520. }
  521. return true;
  522. }
  523. static
  524. void hashfast_poll(struct thr_info * const master_thr)
  525. {
  526. struct cgpu_info * const dev = master_thr->cgpu;
  527. struct timeval tv_timeout;
  528. timer_set_delay_from_now(&tv_timeout, 10000);
  529. while (true)
  530. {
  531. if (!hashfast_poll_msg(master_thr))
  532. {
  533. applog(LOG_DEBUG, "%s poll: No more messages", dev->dev_repr);
  534. break;
  535. }
  536. if (timer_passed(&tv_timeout, NULL))
  537. {
  538. applog(LOG_DEBUG, "%s poll: 10ms timeout met", dev->dev_repr);
  539. break;
  540. }
  541. }
  542. timer_set_delay_from_now(&master_thr->tv_poll, 100000);
  543. }
  544. static
  545. struct api_data *hashfast_api_stats(struct cgpu_info * const proc)
  546. {
  547. struct hashfast_dev_state * const devstate = proc->device_data;
  548. struct thr_info * const thr = proc->thr[0];
  549. struct hashfast_core_state * const cs = thr->cgpu_data;
  550. struct hashfast_chip_state * const chipstate = &devstate->chipstates[cs->chipaddr];
  551. struct api_data *root = NULL;
  552. char key[] = "VoltageNN";
  553. for (int i = 0; i < HASHFAST_MAX_VOLTAGES; ++i)
  554. {
  555. snprintf(&key[7], 3, "%d", i);
  556. if (chipstate->voltages[i])
  557. root = api_add_volts(root, key, &chipstate->voltages[i], false);
  558. }
  559. return root;
  560. }
  561. #ifdef HAVE_CURSES
  562. static
  563. void hashfast_wlogprint_status(struct cgpu_info * const proc)
  564. {
  565. struct hashfast_dev_state * const devstate = proc->device_data;
  566. struct thr_info * const thr = proc->thr[0];
  567. struct hashfast_core_state * const cs = thr->cgpu_data;
  568. struct hashfast_chip_state * const chipstate = &devstate->chipstates[cs->chipaddr];
  569. {
  570. // -> "NNN.xxx / NNN.xxx / NNN.xxx"
  571. size_t sz = (HASHFAST_MAX_VOLTAGES * 10) + 1;
  572. char buf[sz];
  573. char *s = buf;
  574. int rv = 0;
  575. for (int i = 0; i < HASHFAST_MAX_VOLTAGES; ++i)
  576. {
  577. const float voltage = chipstate->voltages[i];
  578. if (!voltage)
  579. continue;
  580. _SNP("%.3f / ", voltage);
  581. }
  582. if (rv >= 3 && s[-2] == '/')
  583. {
  584. s[-3] = '\0';
  585. wlogprint("Voltages: %s\n", buf);
  586. }
  587. }
  588. }
  589. #endif
  590. struct device_drv hashfast_ums_drv = {
  591. .dname = "hashfast_ums",
  592. .name = "HFA",
  593. .lowl_match = hashfast_lowl_match,
  594. .lowl_probe = hashfast_lowl_probe,
  595. .thread_init = hashfast_init,
  596. .minerloop = minerloop_queue,
  597. .queue_append = hashfast_queue_append,
  598. .queue_flush = hashfast_queue_flush,
  599. .poll = hashfast_poll,
  600. .get_api_stats = hashfast_api_stats,
  601. #ifdef HAVE_CURSES
  602. .proc_wlogprint_status = hashfast_wlogprint_status,
  603. #endif
  604. };