driver-avalon.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695
  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static int option_offset = -1;
  35. static struct avalon_info **avalon_info;
  36. struct device_api avalon_api;
  37. static int avalon_init_task(struct avalon_task *at, uint8_t reset, uint8_t ff,
  38. uint8_t fan, uint8_t timeout, uint8_t chip_num,
  39. uint8_t miner_num)
  40. {
  41. static bool first = true;
  42. if (!at)
  43. return -1;
  44. memset(at, 0, sizeof(struct avalon_task));
  45. if (reset) {
  46. at->reset = 1;
  47. first = true;
  48. }
  49. at->flush_fifo = (ff ? 1 : 0);
  50. at->fan_eft = (fan ? 1 : 0);
  51. if (timeout || chip_num || miner_num) {
  52. at->timer_eft = 1;
  53. }
  54. if (first && !at->reset) {
  55. at->fan_eft = 1;
  56. at->timer_eft = 1;
  57. first = false;
  58. }
  59. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  60. at->timeout_data = (timeout ? timeout : AVALON_DEFAULT_TIMEOUT);
  61. at->chip_num = (chip_num ? chip_num : AVALON_DEFAULT_CHIP_NUM);
  62. at->miner_num = (miner_num ? miner_num : AVALON_DEFAULT_MINER_NUM);
  63. at->nonce_elf = 1;
  64. return 0;
  65. }
  66. static inline void avalon_create_task(struct avalon_task *at,
  67. struct work *work)
  68. {
  69. memcpy(at->midstate, work->midstate, 32);
  70. memcpy(at->data, work->data + 64, 12);
  71. }
  72. static int avalon_send_task(int fd, const struct avalon_task *at)
  73. {
  74. size_t ret;
  75. int full;
  76. struct timespec p;
  77. uint8_t *buf;
  78. size_t nr_len;
  79. nr_len = AVALON_WRITE_SIZE + 4 * at->chip_num;
  80. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  81. if (!buf)
  82. return AVA_SEND_ERROR;
  83. memcpy(buf, at, AVALON_WRITE_SIZE);
  84. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  85. uint8_t tt = 0;
  86. tt = (buf[0] & 0x0f) << 4;
  87. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  88. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  89. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  90. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  91. buf[0] = tt;
  92. buf[4] = rev8(buf[4]);
  93. #endif
  94. if (opt_debug) {
  95. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  96. hexdump((uint8_t *)buf, nr_len);
  97. }
  98. ret = write(fd, buf, nr_len);
  99. free(buf);
  100. if (unlikely(ret != nr_len))
  101. return AVA_SEND_ERROR;
  102. p.tv_sec = 0;
  103. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  104. nanosleep(&p, NULL);
  105. full = avalon_buffer_full(fd);
  106. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  107. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  108. if (full == AVA_BUFFER_EMPTY)
  109. return AVA_SEND_BUFFER_EMPTY;
  110. return AVA_SEND_BUFFER_FULL;
  111. }
  112. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  113. struct thr_info *thr, struct timeval *tv_finish)
  114. {
  115. ssize_t ret = 0;
  116. int rc = 0;
  117. int read_amount = AVALON_READ_SIZE;
  118. bool first = true;
  119. /* Read reply 1 byte at a time to get earliest tv_finish */
  120. while (true) {
  121. ret = read(fd, buf, 1);
  122. if (ret < 0)
  123. return AVA_GETS_ERROR;
  124. if (first && tv_finish != NULL)
  125. gettimeofday(tv_finish, NULL);
  126. if (ret >= read_amount)
  127. return AVA_GETS_OK;
  128. if (ret > 0) {
  129. buf += ret;
  130. read_amount -= ret;
  131. first = false;
  132. continue;
  133. }
  134. rc++;
  135. if (rc >= read_count) {
  136. if (opt_debug) {
  137. applog(LOG_ERR,
  138. "Avalon: No data in %.2f seconds",
  139. (float)rc/(float)TIME_FACTOR);
  140. }
  141. return AVA_GETS_TIMEOUT;
  142. }
  143. if (thr && thr->work_restart) {
  144. if (opt_debug) {
  145. applog(LOG_ERR,
  146. "Avalon: Work restart at %.2f seconds",
  147. (float)(rc)/(float)TIME_FACTOR);
  148. }
  149. return AVA_GETS_RESTART;
  150. }
  151. }
  152. }
  153. static int avalon_get_result(int fd, struct avalon_result *ar,
  154. struct thr_info *thr, struct timeval *tv_finish)
  155. {
  156. struct cgpu_info *avalon;
  157. struct avalon_info *info;
  158. uint8_t result[AVALON_READ_SIZE];
  159. int ret, read_count = 16;
  160. if (thr) {
  161. avalon = thr->cgpu;
  162. info = avalon_info[avalon->device_id];
  163. read_count = info->read_count;
  164. }
  165. memset(result, 0, AVALON_READ_SIZE);
  166. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  167. if (ret == AVA_GETS_OK) {
  168. if (opt_debug) {
  169. applog(LOG_DEBUG, "Avalon: get:");
  170. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  171. }
  172. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  173. }
  174. return ret;
  175. }
  176. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  177. uint32_t *nonce)
  178. {
  179. int i;
  180. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  181. if (!work || !work[i])
  182. return -1;
  183. }
  184. *nonce = ar->nonce;
  185. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  186. *nonce = swab32(*nonce);
  187. #endif
  188. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  189. if (!memcmp(ar->data, work[i]->data + 64, 12) &&
  190. !memcmp(ar->midstate, work[i]->midstate, 32))
  191. break;
  192. }
  193. if (i == AVALON_GET_WORK_COUNT)
  194. return -1;
  195. applog(LOG_DEBUG, "Avalon: match to work: %d", i);
  196. return i;
  197. }
  198. static int avalon_reset(int fd)
  199. {
  200. struct avalon_task at;
  201. struct avalon_result ar;
  202. uint8_t *buf;
  203. int ret, i;
  204. struct timespec p;
  205. avalon_init_task(&at,
  206. 1,
  207. 0,
  208. AVALON_DEFAULT_FAN_PWM,
  209. AVALON_DEFAULT_TIMEOUT,
  210. AVALON_DEFAULT_CHIP_NUM,
  211. AVALON_DEFAULT_MINER_NUM);
  212. ret = avalon_send_task(fd, &at);
  213. if (ret == AVA_SEND_ERROR)
  214. return 1;
  215. avalon_get_result(fd, &ar, NULL, NULL);
  216. buf = (uint8_t *)&ar;
  217. for (i = 0; i < 11; i++)
  218. if (buf[i] != 0)
  219. break;
  220. /* FIXME: add more avalon info base on return */
  221. if (i != 11) {
  222. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  223. return 1;
  224. }
  225. p.tv_sec = 1;
  226. p.tv_nsec = AVALON_RESET_PITCH;
  227. nanosleep(&p, NULL);
  228. applog(LOG_ERR, "Avalon: Reset succeeded");
  229. return 0;
  230. }
  231. static void do_avalon_close(struct thr_info *thr)
  232. {
  233. struct cgpu_info *avalon = thr->cgpu;
  234. avalon_close(avalon->device_fd);
  235. avalon->device_fd = -1;
  236. }
  237. static void set_timing_mode(struct cgpu_info *avalon)
  238. {
  239. struct avalon_info *info = avalon_info[avalon->device_id];
  240. /* Anything else in buf just uses DEFAULT mode */
  241. info->Hs = AVALON_HASH_TIME;
  242. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  243. info->read_count =
  244. (int)(info->fullnonce * TIME_FACTOR) - 1;
  245. }
  246. static void get_options(int this_option_offset, int *baud, int *miner_count,
  247. int *asic_count)
  248. {
  249. char err_buf[BUFSIZ+1];
  250. char buf[BUFSIZ+1];
  251. char *ptr, *comma, *colon, *colon2;
  252. size_t max;
  253. int i, tmp;
  254. if (opt_avalon_options == NULL)
  255. buf[0] = '\0';
  256. else {
  257. ptr = opt_avalon_options;
  258. for (i = 0; i < this_option_offset; i++) {
  259. comma = strchr(ptr, ',');
  260. if (comma == NULL)
  261. break;
  262. ptr = comma + 1;
  263. }
  264. comma = strchr(ptr, ',');
  265. if (comma == NULL)
  266. max = strlen(ptr);
  267. else
  268. max = comma - ptr;
  269. if (max > BUFSIZ)
  270. max = BUFSIZ;
  271. strncpy(buf, ptr, max);
  272. buf[max] = '\0';
  273. }
  274. *baud = AVALON_IO_SPEED;
  275. *miner_count = AVALON_DEFAULT_MINER_NUM;
  276. *asic_count = AVALON_DEFAULT_CHIP_NUM;
  277. if (*buf) {
  278. colon = strchr(buf, ':');
  279. if (colon)
  280. *(colon++) = '\0';
  281. if (*buf) {
  282. tmp = atoi(buf);
  283. switch (tmp) {
  284. case 115200:
  285. *baud = 115200;
  286. break;
  287. case 57600:
  288. *baud = 57600;
  289. break;
  290. case 19200:
  291. *baud = 19200;
  292. break;
  293. default:
  294. sprintf(err_buf,
  295. "Invalid avalon-options for baud (%s) "
  296. "must be 115200, 57600 or 19200", buf);
  297. quit(1, err_buf);
  298. }
  299. }
  300. if (colon && *colon) {
  301. colon2 = strchr(colon, ':');
  302. if (colon2)
  303. *(colon2++) = '\0';
  304. if (*colon) {
  305. tmp = atoi(colon);
  306. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  307. *miner_count = tmp;
  308. } else {
  309. sprintf(err_buf,
  310. "Invalid avalon-options for "
  311. "miner_count (%s) must be 1 ~ 32",
  312. colon);
  313. quit(1, err_buf);
  314. }
  315. }
  316. if (colon2 && *colon2) {
  317. tmp = atoi(colon2);
  318. if (tmp > 0 && tmp <= AVALON_DEFAULT_CHIP_NUM)
  319. *asic_count = tmp;
  320. else {
  321. sprintf(err_buf,
  322. "Invalid avalon-options for "
  323. "asic_count (%s) must be 1 ~ 10 ",
  324. colon2);
  325. quit(1, err_buf);
  326. }
  327. }
  328. }
  329. }
  330. }
  331. static bool avalon_detect_one(const char *devpath)
  332. {
  333. struct avalon_info *info;
  334. int fd, ret;
  335. int baud, miner_count, asic_count;
  336. int this_option_offset = ++option_offset;
  337. get_options(this_option_offset, &baud, &miner_count, &asic_count);
  338. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  339. fd = avalon_open2(devpath, baud, true);
  340. if (unlikely(fd == -1)) {
  341. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  342. return false;
  343. }
  344. ret = avalon_reset(fd);
  345. avalon_close(fd);
  346. if (ret)
  347. return false;
  348. /* We have a real Avalon! */
  349. struct cgpu_info *avalon;
  350. avalon = calloc(1, sizeof(struct cgpu_info));
  351. avalon->api = &avalon_api;
  352. avalon->device_path = strdup(devpath);
  353. avalon->device_fd = -1;
  354. avalon->threads = AVALON_MINER_THREADS;
  355. add_cgpu(avalon);
  356. avalon_info = realloc(avalon_info,
  357. sizeof(struct avalon_info *) *
  358. (total_devices + 1));
  359. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  360. devpath, avalon->device_id);
  361. applog(LOG_DEBUG,
  362. "Avalon: Init: %d baud=%d miner_count=%d asic_count=%d",
  363. avalon->device_id, baud, miner_count, asic_count);
  364. avalon_info[avalon->device_id] = (struct avalon_info *)
  365. malloc(sizeof(struct avalon_info));
  366. if (unlikely(!(avalon_info[avalon->device_id])))
  367. quit(1, "Failed to malloc avalon_info");
  368. info = avalon_info[avalon->device_id];
  369. memset(info, 0, sizeof(struct avalon_info));
  370. info->baud = baud;
  371. info->miner_count = miner_count;
  372. info->asic_count = asic_count;
  373. set_timing_mode(avalon);
  374. return true;
  375. }
  376. static inline void avalon_detect()
  377. {
  378. serial_detect(&avalon_api, avalon_detect_one);
  379. }
  380. static bool avalon_prepare(struct thr_info *thr)
  381. {
  382. struct cgpu_info *avalon = thr->cgpu;
  383. struct timeval now;
  384. int fd, ret;
  385. avalon->device_fd = -1;
  386. fd = avalon_open(avalon->device_path,
  387. avalon_info[avalon->device_id]->baud);
  388. if (unlikely(fd == -1)) {
  389. applog(LOG_ERR, "Avalon: Failed to open on %s",
  390. avalon->device_path);
  391. return false;
  392. }
  393. ret = avalon_reset(fd);
  394. if (ret)
  395. return false;
  396. avalon->device_fd = fd;
  397. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  398. gettimeofday(&now, NULL);
  399. get_datestamp(avalon->init, &now);
  400. return true;
  401. }
  402. static void avalon_free_work(struct work **work)
  403. {
  404. int i;
  405. if (!work)
  406. return;
  407. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  408. if (work[i])
  409. free_work(work[i++]);
  410. }
  411. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  412. __maybe_unused int64_t max_nonce)
  413. {
  414. struct cgpu_info *avalon;
  415. int fd;
  416. int ret;
  417. int full;
  418. struct avalon_info *info;
  419. struct avalon_task at;
  420. struct avalon_result ar;
  421. static struct work *bulk0[3] = {NULL, NULL, NULL};
  422. static struct work *bulk1[3] = {NULL, NULL, NULL};
  423. static struct work *bulk2[3] = {NULL, NULL, NULL};
  424. struct work **work = NULL;
  425. int i, work_i0, work_i1, work_i2;
  426. uint32_t nonce;
  427. int64_t hash_count;
  428. struct timeval tv_start, tv_finish, elapsed;
  429. int curr_hw_errors;
  430. bool was_hw_error;
  431. int64_t estimate_hashes;
  432. avalon = thr->cgpu;
  433. info = avalon_info[avalon->device_id];
  434. if (avalon->device_fd == -1)
  435. if (!avalon_prepare(thr)) {
  436. applog(LOG_ERR, "AVA%i: Comms error",
  437. avalon->device_id);
  438. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  439. /* fail the device if the reopen attempt fails */
  440. return -1;
  441. }
  442. fd = avalon->device_fd;
  443. #ifndef WIN32
  444. tcflush(fd, TCOFLUSH);
  445. #endif
  446. work = bulk_work;
  447. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  448. bulk0[i] = bulk1[i];
  449. bulk1[i] = bulk2[i];
  450. bulk2[i] = bulk_work[i];
  451. }
  452. i = 0;
  453. while (true) {
  454. avalon_init_default_task(&at);
  455. avalon_create_task(&at, work[i]);
  456. ret = avalon_send_task(fd, &at);
  457. if (ret == AVA_SEND_ERROR) {
  458. avalon_free_work(bulk0);
  459. avalon_free_work(bulk1);
  460. avalon_free_work(bulk2);
  461. do_avalon_close(thr);
  462. applog(LOG_ERR, "AVA%i: Comms error",
  463. avalon->device_id);
  464. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  465. sleep(1);
  466. return 0; /* This should never happen */
  467. }
  468. work[i]->blk.nonce = 0xffffffff;
  469. if (ret == AVA_SEND_BUFFER_FULL)
  470. break;
  471. i++;
  472. if (i == AVALON_GET_WORK_COUNT &&
  473. ret != AVA_SEND_BUFFER_FULL) {
  474. return 0xffffffff;
  475. }
  476. }
  477. elapsed.tv_sec = elapsed.tv_usec = 0;
  478. gettimeofday(&tv_start, NULL);
  479. while(true) {
  480. full = avalon_buffer_full(fd);
  481. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  482. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  483. if (full == AVA_BUFFER_EMPTY)
  484. break;
  485. work_i0 = work_i1 = work_i2 = -1;
  486. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  487. if (ret == AVA_GETS_ERROR) {
  488. avalon_free_work(bulk0);
  489. avalon_free_work(bulk1);
  490. avalon_free_work(bulk2);
  491. do_avalon_close(thr);
  492. applog(LOG_ERR,
  493. "AVA%i: Comms error", avalon->device_id);
  494. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  495. return 0;
  496. }
  497. /* aborted before becoming idle, get new work */
  498. if (ret == AVA_GETS_TIMEOUT) {
  499. timersub(&tv_finish, &tv_start, &elapsed);
  500. estimate_hashes = ((double)(elapsed.tv_sec) +
  501. ((double)(elapsed.tv_usec)) /
  502. ((double)1000000)) / info->Hs;
  503. /* If Serial-USB delay allowed the full nonce range to
  504. * complete it can't have done more than a full nonce
  505. */
  506. if (unlikely(estimate_hashes > 0xffffffff))
  507. estimate_hashes = 0xffffffff;
  508. applog(LOG_DEBUG,
  509. "Avalon: no nonce = 0x%08llx hashes "
  510. "(%ld.%06lds)",
  511. estimate_hashes, elapsed.tv_sec,
  512. elapsed.tv_usec);
  513. continue;
  514. }
  515. if (ret == AVA_GETS_RESTART) {
  516. avalon_free_work(bulk0);
  517. avalon_free_work(bulk1);
  518. avalon_free_work(bulk2);
  519. continue;
  520. }
  521. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  522. if (work_i0 < 0)
  523. applog(LOG_DEBUG,
  524. "Avalon: can not match nonce to bulk0");
  525. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  526. if (work_i1 < 0)
  527. applog(LOG_DEBUG,
  528. "Avalon: can not match nonce to bulk1");
  529. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  530. if (work_i2 < 0)
  531. applog(LOG_DEBUG,
  532. "Avalon: can not match nonce to bulk2");
  533. curr_hw_errors = avalon->hw_errors;
  534. if (work_i0 >= 0)
  535. submit_nonce(thr, bulk0[work_i0], nonce);
  536. if (work_i1 >= 0)
  537. submit_nonce(thr, bulk1[work_i1], nonce);
  538. if (work_i2 >= 0)
  539. submit_nonce(thr, bulk2[work_i2], nonce);
  540. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  541. /* Force a USB close/reopen on any hw error */
  542. if (was_hw_error)
  543. do_avalon_close(thr);
  544. hash_count = nonce;
  545. hash_count++;
  546. hash_count *= info->asic_count;
  547. }
  548. avalon_free_work(bulk0);
  549. if (opt_debug) {
  550. timersub(&tv_finish, &tv_start, &elapsed);
  551. applog(LOG_DEBUG,
  552. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  553. "(%ld.%06lds)",
  554. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  555. }
  556. return hash_count;
  557. }
  558. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  559. {
  560. struct api_data *root = NULL;
  561. struct avalon_info *info = avalon_info[cgpu->device_id];
  562. /* Warning, access to these is not locked - but we don't really
  563. * care since hashing performance is way more important than
  564. * locking access to displaying API debug 'stats'
  565. * If locking becomes an issue for any of them, use copy_data=true also */
  566. root = api_add_int(root, "read_count", &(info->read_count), false);
  567. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  568. root = api_add_int(root, "baud", &(info->baud), false);
  569. root = api_add_int(root, "miner_count", &(info->miner_count),
  570. false);
  571. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  572. return root;
  573. }
  574. static void avalon_shutdown(struct thr_info *thr)
  575. {
  576. do_avalon_close(thr);
  577. }
  578. struct device_api avalon_api = {
  579. .dname = "avalon",
  580. .name = "AVA",
  581. .api_detect = avalon_detect,
  582. .thread_prepare = avalon_prepare,
  583. .scanhash_queue = avalon_scanhash,
  584. .get_api_stats = avalon_api_stats,
  585. .thread_shutdown = avalon_shutdown,
  586. };