driver-avalon.c 24 KB

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  1. /*
  2. * Copyright 2012-2013 Xiangfu
  3. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <sys/select.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #ifndef WIN32
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include "deviceapi.h"
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "fpgautils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. static int option_offset = -1;
  39. struct avalon_info **avalon_infos;
  40. struct device_drv avalon_drv;
  41. static int avalon_init_task(struct avalon_task *at,
  42. uint8_t reset, uint8_t ff, uint8_t fan,
  43. uint8_t timeout, uint8_t asic_num,
  44. uint8_t miner_num, uint8_t nonce_elf,
  45. uint8_t gate_miner, int frequency)
  46. {
  47. uint8_t *buf;
  48. static bool first = true;
  49. if (unlikely(!at))
  50. return -1;
  51. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  52. return -1;
  53. memset(at, 0, sizeof(struct avalon_task));
  54. if (unlikely(reset)) {
  55. at->reset = 1;
  56. at->fan_eft = 1;
  57. at->timer_eft = 1;
  58. first = true;
  59. }
  60. at->flush_fifo = (ff ? 1 : 0);
  61. at->fan_eft = (fan ? 1 : 0);
  62. if (unlikely(first && !at->reset)) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  68. at->timeout_data = timeout;
  69. at->asic_num = asic_num;
  70. at->miner_num = miner_num;
  71. at->nonce_elf = nonce_elf;
  72. at->gate_miner_elf = 1;
  73. at->asic_pll = 1;
  74. if (unlikely(gate_miner)) {
  75. at-> gate_miner = 1;
  76. at->asic_pll = 0;
  77. }
  78. buf = (uint8_t *)at;
  79. buf[5] = 0x00;
  80. buf[8] = 0x74;
  81. buf[9] = 0x01;
  82. buf[10] = 0x00;
  83. buf[11] = 0x00;
  84. if (frequency == 256) {
  85. buf[6] = 0x03;
  86. buf[7] = 0x08;
  87. } else if (frequency == 270) {
  88. buf[6] = 0x73;
  89. buf[7] = 0x08;
  90. } else if (frequency == 282) {
  91. buf[6] = 0xd3;
  92. buf[7] = 0x08;
  93. } else if (frequency == 300) {
  94. buf[6] = 0x63;
  95. buf[7] = 0x09;
  96. }
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_send_task(int fd, const struct avalon_task *at,
  106. struct cgpu_info *avalon)
  107. {
  108. size_t ret;
  109. int full;
  110. struct timespec p;
  111. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  112. size_t nr_len;
  113. struct avalon_info *info;
  114. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  115. uint32_t nonce_range;
  116. int i;
  117. if (at->nonce_elf)
  118. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  119. else
  120. nr_len = AVALON_WRITE_SIZE;
  121. memcpy(buf, at, AVALON_WRITE_SIZE);
  122. if (at->nonce_elf) {
  123. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  124. for (i = 0; i < at->asic_num; i++) {
  125. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  126. (i * nonce_range & 0xff000000) >> 24;
  127. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  128. (i * nonce_range & 0x00ff0000) >> 16;
  129. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  130. (i * nonce_range & 0x0000ff00) >> 8;
  131. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  132. (i * nonce_range & 0x000000ff) >> 0;
  133. }
  134. }
  135. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  136. uint8_t tt = 0;
  137. tt = (buf[0] & 0x0f) << 4;
  138. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  139. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  140. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  141. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  142. buf[0] = tt;
  143. tt = (buf[4] & 0x0f) << 4;
  144. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  145. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  146. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  147. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  148. buf[4] = tt;
  149. #endif
  150. if (likely(avalon)) {
  151. info = avalon_infos[avalon->device_id];
  152. delay = nr_len * 10 * 1000000000ULL;
  153. delay = delay / info->baud;
  154. }
  155. if (at->reset)
  156. nr_len = 1;
  157. if (opt_debug) {
  158. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  159. hexdump((uint8_t *)buf, nr_len);
  160. }
  161. ret = write(fd, buf, nr_len);
  162. if (unlikely(ret != nr_len))
  163. return AVA_SEND_ERROR;
  164. p.tv_sec = 0;
  165. p.tv_nsec = (long)delay + 4000000;
  166. nanosleep(&p, NULL);
  167. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  168. full = avalon_buffer_full(fd);
  169. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  170. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  171. if (unlikely(full == AVA_BUFFER_FULL))
  172. return AVA_SEND_BUFFER_FULL;
  173. return AVA_SEND_BUFFER_EMPTY;
  174. }
  175. static inline int avalon_gets(int fd, uint8_t *buf, struct thr_info *thr,
  176. struct timeval *tv_finish)
  177. {
  178. int read_amount = AVALON_READ_SIZE;
  179. bool first = true;
  180. ssize_t ret = 0;
  181. while (true) {
  182. struct timeval timeout;
  183. fd_set rd;
  184. if (unlikely(thr->work_restart)) {
  185. applog(LOG_DEBUG, "Avalon: Work restart");
  186. return AVA_GETS_RESTART;
  187. }
  188. timeout.tv_sec = 0;
  189. timeout.tv_usec = 100000;
  190. FD_ZERO(&rd);
  191. FD_SET(fd, &rd);
  192. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  193. if (unlikely(ret < 0)) {
  194. applog(LOG_ERR, "Avalon: Error %d on select in avalon_gets", errno);
  195. return AVA_GETS_ERROR;
  196. }
  197. if (ret) {
  198. ret = read(fd, buf, read_amount);
  199. if (unlikely(ret < 0)) {
  200. applog(LOG_ERR, "Avalon: Error %d on read in avalon_gets", errno);
  201. return AVA_GETS_ERROR;
  202. }
  203. if (likely(first)) {
  204. gettimeofday(tv_finish, NULL);
  205. first = false;
  206. }
  207. if (likely(ret >= read_amount))
  208. return AVA_GETS_OK;
  209. buf += ret;
  210. read_amount -= ret;
  211. continue;
  212. }
  213. if (unlikely(thr->work_restart)) {
  214. applog(LOG_DEBUG, "Avalon: Work restart");
  215. return AVA_GETS_RESTART;
  216. }
  217. return AVA_GETS_TIMEOUT;
  218. }
  219. }
  220. static int avalon_get_result(int fd, struct avalon_result *ar,
  221. struct thr_info *thr, struct timeval *tv_finish)
  222. {
  223. uint8_t result[AVALON_READ_SIZE];
  224. int ret;
  225. memset(result, 0, AVALON_READ_SIZE);
  226. ret = avalon_gets(fd, result, thr, tv_finish);
  227. if (ret == AVA_GETS_OK) {
  228. if (opt_debug) {
  229. applog(LOG_DEBUG, "Avalon: get:");
  230. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  231. }
  232. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  233. }
  234. return ret;
  235. }
  236. static bool avalon_decode_nonce(struct thr_info *thr, struct avalon_result *ar,
  237. uint32_t *nonce)
  238. {
  239. struct cgpu_info *avalon;
  240. struct avalon_info *info;
  241. struct work *work;
  242. avalon = thr->cgpu;
  243. if (unlikely(!avalon->works))
  244. return false;
  245. work = find_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  246. (char *)ar->data, 64, 12);
  247. if (!work)
  248. return false;
  249. info = avalon_infos[avalon->device_id];
  250. info->matching_work++;
  251. *nonce = htole32(ar->nonce);
  252. submit_nonce(thr, work, *nonce);
  253. return true;
  254. }
  255. static void avalon_get_reset(int fd, struct avalon_result *ar)
  256. {
  257. int read_amount = AVALON_READ_SIZE;
  258. uint8_t result[AVALON_READ_SIZE];
  259. struct timeval timeout = {1, 0};
  260. ssize_t ret = 0, offset = 0;
  261. fd_set rd;
  262. memset(result, 0, AVALON_READ_SIZE);
  263. memset(ar, 0, AVALON_READ_SIZE);
  264. FD_ZERO(&rd);
  265. FD_SET(fd, &rd);
  266. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  267. if (unlikely(ret < 0)) {
  268. applog(LOG_WARNING, "Avalon: Error %d on select in avalon_get_reset", errno);
  269. return;
  270. }
  271. if (!ret) {
  272. applog(LOG_WARNING, "Avalon: Timeout on select in avalon_get_reset");
  273. return;
  274. }
  275. do {
  276. ret = read(fd, result + offset, read_amount);
  277. if (unlikely(ret < 0)) {
  278. applog(LOG_WARNING, "Avalon: Error %d on read in avalon_get_reset", errno);
  279. return;
  280. }
  281. read_amount -= ret;
  282. offset += ret;
  283. } while (read_amount > 0);
  284. if (opt_debug) {
  285. applog(LOG_DEBUG, "Avalon: get:");
  286. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  287. }
  288. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  289. }
  290. static int avalon_reset(int fd, struct avalon_result *ar)
  291. {
  292. struct avalon_task at;
  293. uint8_t *buf;
  294. int ret, i = 0;
  295. struct timespec p;
  296. avalon_init_task(&at, 1, 0,
  297. AVALON_DEFAULT_FAN_MAX_PWM,
  298. AVALON_DEFAULT_TIMEOUT,
  299. AVALON_DEFAULT_ASIC_NUM,
  300. AVALON_DEFAULT_MINER_NUM,
  301. 0, 0,
  302. AVALON_DEFAULT_FREQUENCY);
  303. ret = avalon_send_task(fd, &at, NULL);
  304. if (ret == AVA_SEND_ERROR)
  305. return 1;
  306. avalon_get_reset(fd, ar);
  307. buf = (uint8_t *)ar;
  308. /* Sometimes there is one extra 0 byte for some reason in the buffer,
  309. * so work around it. */
  310. if (buf[0] == 0)
  311. buf = (uint8_t *)(ar + 1);
  312. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  313. buf[2] == 0xAA && buf[3] == 0x55) {
  314. for (i = 4; i < 11; i++)
  315. if (buf[i] != 0)
  316. break;
  317. }
  318. p.tv_sec = 0;
  319. p.tv_nsec = AVALON_RESET_PITCH;
  320. nanosleep(&p, NULL);
  321. if (i != 11) {
  322. applog(LOG_ERR, "Avalon: Reset failed! not an Avalon?"
  323. " (%d: %02x %02x %02x %02x)",
  324. i, buf[0], buf[1], buf[2], buf[3]);
  325. /* FIXME: return 1; */
  326. } else
  327. applog(LOG_WARNING, "Avalon: Reset succeeded");
  328. return 0;
  329. }
  330. static void avalon_idle(struct cgpu_info *avalon)
  331. {
  332. int i, ret;
  333. struct avalon_task at;
  334. int fd = avalon->device_fd;
  335. struct avalon_info *info = avalon_infos[avalon->device_id];
  336. int avalon_get_work_count = info->miner_count;
  337. i = 0;
  338. while (true) {
  339. avalon_init_task(&at, 0, 0, info->fan_pwm,
  340. info->timeout, info->asic_count,
  341. info->miner_count, 1, 1, info->frequency);
  342. ret = avalon_send_task(fd, &at, avalon);
  343. if (unlikely(ret == AVA_SEND_ERROR ||
  344. (ret == AVA_SEND_BUFFER_EMPTY &&
  345. (i + 1 == avalon_get_work_count * 2)))) {
  346. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  347. return;
  348. }
  349. if (i + 1 == avalon_get_work_count * 2)
  350. break;
  351. if (ret == AVA_SEND_BUFFER_FULL)
  352. break;
  353. i++;
  354. }
  355. applog(LOG_ERR, "Avalon: Goto idle mode");
  356. }
  357. static void get_options(int this_option_offset, int *baud, int *miner_count,
  358. int *asic_count, int *timeout, int *frequency)
  359. {
  360. char buf[BUFSIZ+1];
  361. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  362. size_t max;
  363. int i, tmp;
  364. if (opt_avalon_options == NULL)
  365. buf[0] = '\0';
  366. else {
  367. ptr = opt_avalon_options;
  368. for (i = 0; i < this_option_offset; i++) {
  369. comma = strchr(ptr, ',');
  370. if (comma == NULL)
  371. break;
  372. ptr = comma + 1;
  373. }
  374. comma = strchr(ptr, ',');
  375. if (comma == NULL)
  376. max = strlen(ptr);
  377. else
  378. max = comma - ptr;
  379. if (max > BUFSIZ)
  380. max = BUFSIZ;
  381. strncpy(buf, ptr, max);
  382. buf[max] = '\0';
  383. }
  384. *baud = AVALON_IO_SPEED;
  385. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  386. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  387. *timeout = AVALON_DEFAULT_TIMEOUT;
  388. *frequency = AVALON_DEFAULT_FREQUENCY;
  389. if (!(*buf))
  390. return;
  391. colon = strchr(buf, ':');
  392. if (colon)
  393. *(colon++) = '\0';
  394. tmp = atoi(buf);
  395. switch (tmp) {
  396. case 115200:
  397. *baud = 115200;
  398. break;
  399. case 57600:
  400. *baud = 57600;
  401. break;
  402. case 38400:
  403. *baud = 38400;
  404. break;
  405. case 19200:
  406. *baud = 19200;
  407. break;
  408. default:
  409. quit(1,
  410. "Invalid avalon-options for baud (%s) "
  411. "must be 115200, 57600, 38400 or 19200", buf);
  412. }
  413. if (colon && *colon) {
  414. colon2 = strchr(colon, ':');
  415. if (colon2)
  416. *(colon2++) = '\0';
  417. if (*colon) {
  418. tmp = atoi(colon);
  419. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  420. *miner_count = tmp;
  421. } else {
  422. quit(1,
  423. "Invalid avalon-options for "
  424. "miner_count (%s) must be 1 ~ %d",
  425. colon, AVALON_DEFAULT_MINER_NUM);
  426. }
  427. }
  428. if (colon2 && *colon2) {
  429. colon3 = strchr(colon2, ':');
  430. if (colon3)
  431. *(colon3++) = '\0';
  432. tmp = atoi(colon2);
  433. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  434. *asic_count = tmp;
  435. else {
  436. quit(1,
  437. "Invalid avalon-options for "
  438. "asic_count (%s) must be 1 ~ %d",
  439. colon2, AVALON_DEFAULT_ASIC_NUM);
  440. }
  441. if (colon3 && *colon3) {
  442. colon4 = strchr(colon3, ':');
  443. if (colon4)
  444. *(colon4++) = '\0';
  445. tmp = atoi(colon3);
  446. if (tmp > 0 && tmp <= 0xff)
  447. *timeout = tmp;
  448. else {
  449. quit(1,
  450. "Invalid avalon-options for "
  451. "timeout (%s) must be 1 ~ %d",
  452. colon3, 0xff);
  453. }
  454. if (colon4 && *colon4) {
  455. tmp = atoi(colon4);
  456. switch (tmp) {
  457. case 256:
  458. case 270:
  459. case 282:
  460. case 300:
  461. *frequency = tmp;
  462. break;
  463. default:
  464. quit(1,
  465. "Invalid avalon-options for "
  466. "frequency must be 256/270/282/300");
  467. }
  468. }
  469. }
  470. }
  471. }
  472. }
  473. static bool avalon_detect_one(const char *devpath)
  474. {
  475. struct avalon_info *info;
  476. struct avalon_result ar;
  477. int fd, ret;
  478. int baud, miner_count, asic_count, timeout, frequency = 0;
  479. struct cgpu_info *avalon;
  480. int this_option_offset = ++option_offset;
  481. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  482. &timeout, &frequency);
  483. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  484. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  485. devpath, baud, miner_count, asic_count, timeout, frequency);
  486. fd = avalon_open2(devpath, baud, true);
  487. if (unlikely(fd == -1)) {
  488. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  489. return false;
  490. }
  491. /* We have a real Avalon! */
  492. avalon = calloc(1, sizeof(struct cgpu_info));
  493. avalon->drv = &avalon_drv;
  494. avalon->device_path = strdup(devpath);
  495. avalon->device_fd = fd;
  496. avalon->threads = AVALON_MINER_THREADS;
  497. add_cgpu(avalon);
  498. ret = avalon_reset(fd, &ar);
  499. if (ret) {
  500. ; /* FIXME: I think IT IS avalon and wait on reset;
  501. * avalon_close(fd);
  502. * return false; */
  503. }
  504. avalon_infos = realloc(avalon_infos,
  505. sizeof(struct avalon_info *) *
  506. (total_devices + 1));
  507. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  508. devpath, avalon->device_id);
  509. avalon_infos[avalon->device_id] = (struct avalon_info *)
  510. malloc(sizeof(struct avalon_info));
  511. if (unlikely(!(avalon_infos[avalon->device_id])))
  512. quit(1, "Failed to malloc avalon_infos");
  513. info = avalon_infos[avalon->device_id];
  514. memset(info, 0, sizeof(struct avalon_info));
  515. info->baud = baud;
  516. info->miner_count = miner_count;
  517. info->asic_count = asic_count;
  518. info->timeout = timeout;
  519. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  520. info->temp_max = 0;
  521. /* This is for check the temp/fan every 3~4s */
  522. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  523. if (info->temp_history_count <= 0)
  524. info->temp_history_count = 1;
  525. info->temp_history_index = 0;
  526. info->temp_sum = 0;
  527. info->temp_old = 0;
  528. info->frequency = frequency;
  529. /* Do something for failed reset ? */
  530. if (0) {
  531. /* Set asic to idle mode after detect */
  532. avalon_idle(avalon);
  533. avalon->device_fd = -1;
  534. avalon_close(fd);
  535. }
  536. return true;
  537. }
  538. static inline void avalon_detect()
  539. {
  540. serial_detect(&avalon_drv, avalon_detect_one);
  541. }
  542. static void __avalon_init(struct cgpu_info *avalon)
  543. {
  544. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  545. }
  546. static void avalon_init(struct cgpu_info *avalon)
  547. {
  548. struct avalon_result ar;
  549. int fd, ret;
  550. avalon->device_fd = -1;
  551. fd = avalon_open(avalon->device_path,
  552. avalon_infos[avalon->device_id]->baud);
  553. if (unlikely(fd == -1)) {
  554. applog(LOG_ERR, "Avalon: Failed to open on %s",
  555. avalon->device_path);
  556. return;
  557. }
  558. ret = avalon_reset(fd, &ar);
  559. if (ret) {
  560. avalon_close(fd);
  561. return;
  562. }
  563. avalon->device_fd = fd;
  564. __avalon_init(avalon);
  565. }
  566. static bool avalon_prepare(struct thr_info *thr)
  567. {
  568. struct cgpu_info *avalon = thr->cgpu;
  569. struct avalon_info *info = avalon_infos[avalon->device_id];
  570. struct timeval now;
  571. free(avalon->works);
  572. avalon->works = calloc(info->miner_count * sizeof(struct work *), 4);
  573. if (!avalon->works)
  574. quit(1, "Failed to calloc avalon works in avalon_prepare");
  575. if (avalon->device_fd == -1)
  576. avalon_init(avalon);
  577. else
  578. __avalon_init(avalon);
  579. gettimeofday(&now, NULL);
  580. get_datestamp(avalon->init, &now);
  581. return true;
  582. }
  583. static void avalon_free_work(struct thr_info *thr)
  584. {
  585. struct cgpu_info *avalon;
  586. struct avalon_info *info;
  587. struct work **works;
  588. int i;
  589. avalon = thr->cgpu;
  590. avalon->queued = 0;
  591. if (unlikely(!avalon->works))
  592. return;
  593. works = avalon->works;
  594. info = avalon_infos[avalon->device_id];
  595. for (i = 0; i < info->miner_count * 4; i++) {
  596. if (works[i]) {
  597. work_completed(avalon, works[i]);
  598. works[i] = NULL;
  599. }
  600. }
  601. }
  602. static void avalon_free_work_array(struct thr_info *thr)
  603. {
  604. struct cgpu_info *avalon;
  605. struct work **works;
  606. int i, j, mc;
  607. avalon = thr->cgpu;
  608. avalon->queued = 0;
  609. if (unlikely(!avalon->works))
  610. return;
  611. works = avalon->works;
  612. mc = avalon_infos[avalon->device_id]->miner_count;
  613. if (++avalon->work_array > 3)
  614. avalon->work_array = 0;
  615. for (i = avalon->work_array * mc, j = 0; j < mc; i++, j++) {
  616. if (likely(works[i])) {
  617. work_completed(avalon, works[i]);
  618. works[i] = NULL;
  619. }
  620. }
  621. }
  622. static void do_avalon_close(struct thr_info *thr)
  623. {
  624. struct avalon_result ar;
  625. struct cgpu_info *avalon = thr->cgpu;
  626. struct avalon_info *info = avalon_infos[avalon->device_id];
  627. avalon_free_work(thr);
  628. nmsleep(1000);
  629. avalon_reset(avalon->device_fd, &ar);
  630. avalon_idle(avalon);
  631. avalon_close(avalon->device_fd);
  632. avalon->device_fd = -1;
  633. info->no_matching_work = 0;
  634. }
  635. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  636. {
  637. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  638. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  639. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  640. info->temp0 = ar->temp0;
  641. info->temp1 = ar->temp1;
  642. info->temp2 = ar->temp2;
  643. if (ar->temp0 & 0x80) {
  644. ar->temp0 &= 0x7f;
  645. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  646. }
  647. if (ar->temp1 & 0x80) {
  648. ar->temp1 &= 0x7f;
  649. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  650. }
  651. if (ar->temp2 & 0x80) {
  652. ar->temp2 &= 0x7f;
  653. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  654. }
  655. *temp_avg = info->temp2;
  656. if (info->temp0 > info->temp_max)
  657. info->temp_max = info->temp0;
  658. if (info->temp1 > info->temp_max)
  659. info->temp_max = info->temp1;
  660. if (info->temp2 > info->temp_max)
  661. info->temp_max = info->temp2;
  662. }
  663. static inline void adjust_fan(struct avalon_info *info)
  664. {
  665. int temp_new;
  666. temp_new = info->temp_sum / info->temp_history_count;
  667. if (temp_new < 35) {
  668. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  669. info->temp_old = temp_new;
  670. } else if (temp_new > 55) {
  671. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  672. info->temp_old = temp_new;
  673. } else if (abs(temp_new - info->temp_old) >= 2) {
  674. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  675. info->temp_old = temp_new;
  676. }
  677. }
  678. static bool avalon_fill(struct cgpu_info *avalon)
  679. {
  680. int subid, mc = avalon_infos[avalon->device_id]->miner_count;
  681. struct work *work;
  682. if (avalon->queued >= mc)
  683. return true;
  684. work = get_queued(avalon);
  685. if (unlikely(!work))
  686. return false;
  687. subid = avalon->queued++;
  688. work->subid = subid;
  689. avalon->works[avalon->work_array * mc + subid] = work;
  690. if (avalon->queued >= mc)
  691. return true;
  692. return false;
  693. }
  694. static int64_t avalon_scanhash(struct thr_info *thr)
  695. {
  696. struct cgpu_info *avalon;
  697. struct work **works;
  698. int fd, ret = AVA_GETS_OK, full;
  699. struct avalon_info *info;
  700. struct avalon_task at;
  701. struct avalon_result ar;
  702. int i;
  703. int avalon_get_work_count;
  704. int start_count, end_count;
  705. struct timeval tv_start, tv_finish, elapsed;
  706. uint32_t nonce;
  707. int64_t hash_count;
  708. static int first_try = 0;
  709. int result_wrong;
  710. avalon = thr->cgpu;
  711. works = avalon->works;
  712. info = avalon_infos[avalon->device_id];
  713. avalon_get_work_count = info->miner_count;
  714. if (unlikely(avalon->device_fd == -1)) {
  715. if (!avalon_prepare(thr)) {
  716. applog(LOG_ERR, "AVA%i: Comms error(open)",
  717. avalon->device_id);
  718. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  719. /* fail the device if the reopen attempt fails */
  720. return -1;
  721. }
  722. }
  723. fd = avalon->device_fd;
  724. #ifndef WIN32
  725. tcflush(fd, TCOFLUSH);
  726. #endif
  727. start_count = avalon->work_array * avalon_get_work_count;
  728. end_count = start_count + avalon_get_work_count;
  729. i = start_count;
  730. while (true) {
  731. avalon_init_task(&at, 0, 0, info->fan_pwm,
  732. info->timeout, info->asic_count,
  733. info->miner_count, 1, 0, info->frequency);
  734. avalon_create_task(&at, works[i]);
  735. ret = avalon_send_task(fd, &at, avalon);
  736. if (unlikely(ret == AVA_SEND_ERROR ||
  737. (ret == AVA_SEND_BUFFER_EMPTY &&
  738. (i + 1 == end_count) &&
  739. first_try))) {
  740. do_avalon_close(thr);
  741. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  742. avalon->device_id);
  743. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  744. first_try = 0;
  745. nmsleep(1000);
  746. avalon_init(avalon);
  747. return 0; /* This should never happen */
  748. }
  749. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == end_count)) {
  750. first_try = 1;
  751. avalon_free_work_array(thr);
  752. return 0xffffffff;
  753. }
  754. works[i]->blk.nonce = 0xffffffff;
  755. if (ret == AVA_SEND_BUFFER_FULL)
  756. break;
  757. i++;
  758. }
  759. if (unlikely(first_try))
  760. first_try = 0;
  761. elapsed.tv_sec = elapsed.tv_usec = 0;
  762. gettimeofday(&tv_start, NULL);
  763. result_wrong = 0;
  764. hash_count = 0;
  765. while (true) {
  766. full = avalon_buffer_full(fd);
  767. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  768. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  769. if (unlikely(full == AVA_BUFFER_EMPTY))
  770. break;
  771. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  772. if (unlikely(ret == AVA_GETS_ERROR)) {
  773. do_avalon_close(thr);
  774. applog(LOG_ERR,
  775. "AVA%i: Comms error(read)", avalon->device_id);
  776. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  777. return 0;
  778. }
  779. if (unlikely(ret == AVA_GETS_RESTART))
  780. break;
  781. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  782. timersub(&tv_finish, &tv_start, &elapsed);
  783. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  784. elapsed.tv_sec, elapsed.tv_usec);
  785. continue;
  786. }
  787. if (!avalon_decode_nonce(thr, &ar, &nonce)) {
  788. info->no_matching_work++;
  789. result_wrong++;
  790. if (opt_debug) {
  791. timersub(&tv_finish, &tv_start, &elapsed);
  792. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  793. " (%ld.%06lds)", info->no_matching_work,
  794. elapsed.tv_sec, elapsed.tv_usec);
  795. }
  796. continue;
  797. }
  798. hash_count += 0xffffffff;
  799. if (opt_debug) {
  800. timersub(&tv_finish, &tv_start, &elapsed);
  801. applog(LOG_DEBUG,
  802. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  803. "(%ld.%06lds)", nonce, hash_count,
  804. elapsed.tv_sec, elapsed.tv_usec);
  805. }
  806. }
  807. if (result_wrong >= avalon_get_work_count && ret != AVA_GETS_RESTART) {
  808. /* This mean FPGA controller gave all wrong results, so
  809. * try to reset the Avalon */
  810. do_avalon_close(thr);
  811. applog(LOG_ERR,
  812. "AVA%i: FPGA controller mess up", avalon->device_id);
  813. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  814. nmsleep(1000);
  815. avalon_init(avalon);
  816. return 0;
  817. }
  818. avalon_free_work_array(thr);
  819. record_temp_fan(info, &ar, &(avalon->temp));
  820. applog(LOG_INFO,
  821. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  822. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  823. info->fan0, info->fan1, info->fan2,
  824. info->temp0, info->temp1, info->temp2, info->temp_max);
  825. info->temp_history_index++;
  826. info->temp_sum += info->temp2;
  827. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  828. info->temp_history_index, info->temp_history_count, info->temp_old);
  829. if (info->temp_history_index == info->temp_history_count) {
  830. adjust_fan(info);
  831. info->temp_history_index = 0;
  832. info->temp_sum = 0;
  833. }
  834. /* This hashmeter is just a utility counter based on returned shares */
  835. return hash_count;
  836. }
  837. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  838. {
  839. struct api_data *root = NULL;
  840. struct avalon_info *info = avalon_infos[cgpu->device_id];
  841. root = api_add_int(root, "baud", &(info->baud), false);
  842. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  843. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  844. root = api_add_int(root, "timeout", &(info->timeout), false);
  845. root = api_add_int(root, "frequency", &(info->frequency), false);
  846. root = api_add_int(root, "fan1", &(info->fan0), false);
  847. root = api_add_int(root, "fan2", &(info->fan1), false);
  848. root = api_add_int(root, "fan3", &(info->fan2), false);
  849. root = api_add_int(root, "temp1", &(info->temp0), false);
  850. root = api_add_int(root, "temp2", &(info->temp1), false);
  851. root = api_add_int(root, "temp3", &(info->temp2), false);
  852. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  853. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  854. root = api_add_int(root, "matching_work_count", &(info->matching_work), false);
  855. return root;
  856. }
  857. static void avalon_shutdown(struct thr_info *thr)
  858. {
  859. do_avalon_close(thr);
  860. }
  861. struct device_drv avalon_drv = {
  862. .dname = "avalon",
  863. .name = "AVA",
  864. .drv_detect = avalon_detect,
  865. .thread_prepare = avalon_prepare,
  866. .minerloop = hash_queued_work,
  867. .queue_full = avalon_fill,
  868. .scanwork = avalon_scanhash,
  869. .get_api_stats = avalon_api_stats,
  870. .reinit_device = avalon_init,
  871. .thread_shutdown = avalon_shutdown,
  872. };