driver-avalon.c 37 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <unistd.h>
  20. #ifndef WIN32
  21. #include <sys/select.h>
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include "compat.h"
  30. #include <windows.h>
  31. #include <io.h>
  32. #endif
  33. #include "elist.h"
  34. #include "miner.h"
  35. #include "usbutils.h"
  36. #include "driver-avalon.h"
  37. #include "hexdump.c"
  38. #include "util.h"
  39. int opt_avalon_temp = AVALON_TEMP_TARGET;
  40. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  41. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  42. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  43. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  44. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  45. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  46. bool opt_avalon_auto;
  47. static int option_offset = -1;
  48. struct device_drv avalon_drv;
  49. static int avalon_init_task(struct avalon_task *at,
  50. uint8_t reset, uint8_t ff, uint8_t fan,
  51. uint8_t timeout, uint8_t asic_num,
  52. uint8_t miner_num, uint8_t nonce_elf,
  53. uint8_t gate_miner, int frequency)
  54. {
  55. uint16_t *lefreq16;
  56. uint8_t *buf;
  57. static bool first = true;
  58. if (unlikely(!at))
  59. return -1;
  60. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  61. return -1;
  62. memset(at, 0, sizeof(struct avalon_task));
  63. if (unlikely(reset)) {
  64. at->reset = 1;
  65. at->fan_eft = 1;
  66. at->timer_eft = 1;
  67. first = true;
  68. }
  69. at->flush_fifo = (ff ? 1 : 0);
  70. at->fan_eft = (fan ? 1 : 0);
  71. if (unlikely(first && !at->reset)) {
  72. at->fan_eft = 1;
  73. at->timer_eft = 1;
  74. first = false;
  75. }
  76. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  77. at->timeout_data = timeout;
  78. at->asic_num = asic_num;
  79. at->miner_num = miner_num;
  80. at->nonce_elf = nonce_elf;
  81. at->gate_miner_elf = 1;
  82. at->asic_pll = 1;
  83. if (unlikely(gate_miner)) {
  84. at-> gate_miner = 1;
  85. at->asic_pll = 0;
  86. }
  87. buf = (uint8_t *)at;
  88. buf[5] = 0x00;
  89. buf[8] = 0x74;
  90. buf[9] = 0x01;
  91. buf[10] = 0x00;
  92. buf[11] = 0x00;
  93. lefreq16 = (uint16_t *)&buf[6];
  94. *lefreq16 = htole16(frequency * 8);
  95. return 0;
  96. }
  97. static inline void avalon_create_task(struct avalon_task *at,
  98. struct work *work)
  99. {
  100. memcpy(at->midstate, work->midstate, 32);
  101. memcpy(at->data, work->data + 64, 12);
  102. }
  103. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  104. {
  105. int err, amount;
  106. err = usb_write(avalon, buf, len, &amount, ep);
  107. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  108. avalon->device_id, err);
  109. if (unlikely(err != 0)) {
  110. applog(LOG_WARNING, "usb_write error on avalon_write");
  111. return AVA_SEND_ERROR;
  112. }
  113. if (amount != len) {
  114. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  115. return AVA_SEND_ERROR;
  116. }
  117. return AVA_SEND_OK;
  118. }
  119. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  120. {
  121. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  122. int delay, ret, i, ep = C_AVALON_TASK;
  123. struct avalon_info *info;
  124. uint32_t nonce_range;
  125. size_t nr_len;
  126. if (at->nonce_elf)
  127. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  128. else
  129. nr_len = AVALON_WRITE_SIZE;
  130. memcpy(buf, at, AVALON_WRITE_SIZE);
  131. if (at->nonce_elf) {
  132. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  133. for (i = 0; i < at->asic_num; i++) {
  134. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  135. (i * nonce_range & 0xff000000) >> 24;
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  137. (i * nonce_range & 0x00ff0000) >> 16;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  139. (i * nonce_range & 0x0000ff00) >> 8;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  141. (i * nonce_range & 0x000000ff) >> 0;
  142. }
  143. }
  144. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  145. uint8_t tt = 0;
  146. tt = (buf[0] & 0x0f) << 4;
  147. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  148. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  149. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  150. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  151. buf[0] = tt;
  152. tt = (buf[4] & 0x0f) << 4;
  153. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  154. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  155. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  156. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  157. buf[4] = tt;
  158. #endif
  159. info = avalon->device_data;
  160. delay = nr_len * 10 * 1000000;
  161. delay = delay / info->baud;
  162. if (at->reset) {
  163. ep = C_AVALON_RESET;
  164. nr_len = 1;
  165. }
  166. if (opt_debug) {
  167. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  168. hexdump(buf, nr_len);
  169. }
  170. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  171. delay += 4000;
  172. nusleep(delay);
  173. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  174. return ret;
  175. }
  176. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  177. struct avalon_info *info, struct avalon_result *ar,
  178. struct work *work)
  179. {
  180. uint32_t nonce;
  181. info = avalon->device_data;
  182. info->matching_work[work->subid]++;
  183. nonce = htole32(ar->nonce);
  184. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  185. return submit_nonce(thr, work, nonce);
  186. }
  187. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  188. static void wait_avalon_ready(struct cgpu_info *avalon)
  189. {
  190. while (avalon_buffer_full(avalon)) {
  191. nmsleep(40);
  192. }
  193. }
  194. #define AVALON_CTS (1 << 4)
  195. static inline bool avalon_cts(char c)
  196. {
  197. return (c & AVALON_CTS);
  198. }
  199. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  200. size_t bufsize, int timeout, int ep)
  201. {
  202. size_t total = 0, readsize = bufsize + 2;
  203. char readbuf[AVALON_READBUF_SIZE];
  204. int err, amount, ofs = 2, cp;
  205. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  206. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  207. avalon->drv->name, avalon->device_id, err);
  208. if (amount < 2)
  209. goto out;
  210. /* The first 2 of every 64 bytes are status on FTDIRL */
  211. while (amount > 2) {
  212. cp = amount - 2;
  213. if (cp > 62)
  214. cp = 62;
  215. memcpy(&buf[total], &readbuf[ofs], cp);
  216. total += cp;
  217. amount -= cp + 2;
  218. ofs += 64;
  219. }
  220. out:
  221. return total;
  222. }
  223. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  224. {
  225. struct avalon_result ar;
  226. int ret, i, spare;
  227. struct avalon_task at;
  228. uint8_t *buf, *tmp;
  229. struct timespec p;
  230. /* Send reset, then check for result */
  231. avalon_init_task(&at, 1, 0,
  232. AVALON_DEFAULT_FAN_MAX_PWM,
  233. AVALON_DEFAULT_TIMEOUT,
  234. AVALON_DEFAULT_ASIC_NUM,
  235. AVALON_DEFAULT_MINER_NUM,
  236. 0, 0,
  237. AVALON_DEFAULT_FREQUENCY);
  238. wait_avalon_ready(avalon);
  239. ret = avalon_send_task(&at, avalon);
  240. if (unlikely(ret == AVA_SEND_ERROR))
  241. return -1;
  242. if (!initial) {
  243. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  244. return 0;
  245. }
  246. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  247. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  248. /* What do these sleeps do?? */
  249. p.tv_sec = 0;
  250. p.tv_nsec = AVALON_RESET_PITCH;
  251. nanosleep(&p, NULL);
  252. /* Look for the first occurrence of 0xAA, the reset response should be:
  253. * AA 55 AA 55 00 00 00 00 00 00 */
  254. spare = ret - 10;
  255. buf = tmp = (uint8_t *)&ar;
  256. if (opt_debug) {
  257. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  258. hexdump(tmp, AVALON_READ_SIZE);
  259. }
  260. for (i = 0; i <= spare; i++) {
  261. buf = &tmp[i];
  262. if (buf[0] == 0xAA)
  263. break;
  264. }
  265. i = 0;
  266. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  267. buf[2] == 0xAA && buf[3] == 0x55) {
  268. for (i = 4; i < 11; i++)
  269. if (buf[i] != 0)
  270. break;
  271. }
  272. if (i != 11) {
  273. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  274. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  275. i, buf[0], buf[1], buf[2], buf[3]);
  276. /* FIXME: return 1; */
  277. } else
  278. applog(LOG_WARNING, "%s%d: Reset succeeded",
  279. avalon->drv->name, avalon->device_id);
  280. return 0;
  281. }
  282. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  283. int *asic_count, int *timeout, int *frequency)
  284. {
  285. char buf[BUFSIZ+1];
  286. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  287. size_t max;
  288. int i, tmp;
  289. if (opt_avalon_options == NULL)
  290. buf[0] = '\0';
  291. else {
  292. ptr = opt_avalon_options;
  293. for (i = 0; i < this_option_offset; i++) {
  294. comma = strchr(ptr, ',');
  295. if (comma == NULL)
  296. break;
  297. ptr = comma + 1;
  298. }
  299. comma = strchr(ptr, ',');
  300. if (comma == NULL)
  301. max = strlen(ptr);
  302. else
  303. max = comma - ptr;
  304. if (max > BUFSIZ)
  305. max = BUFSIZ;
  306. strncpy(buf, ptr, max);
  307. buf[max] = '\0';
  308. }
  309. if (!(*buf))
  310. return false;
  311. colon = strchr(buf, ':');
  312. if (colon)
  313. *(colon++) = '\0';
  314. tmp = atoi(buf);
  315. switch (tmp) {
  316. case 115200:
  317. *baud = 115200;
  318. break;
  319. case 57600:
  320. *baud = 57600;
  321. break;
  322. case 38400:
  323. *baud = 38400;
  324. break;
  325. case 19200:
  326. *baud = 19200;
  327. break;
  328. default:
  329. quit(1, "Invalid avalon-options for baud (%s) "
  330. "must be 115200, 57600, 38400 or 19200", buf);
  331. }
  332. if (colon && *colon) {
  333. colon2 = strchr(colon, ':');
  334. if (colon2)
  335. *(colon2++) = '\0';
  336. if (*colon) {
  337. tmp = atoi(colon);
  338. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  339. *miner_count = tmp;
  340. } else {
  341. quit(1, "Invalid avalon-options for "
  342. "miner_count (%s) must be 1 ~ %d",
  343. colon, AVALON_DEFAULT_MINER_NUM);
  344. }
  345. }
  346. if (colon2 && *colon2) {
  347. colon3 = strchr(colon2, ':');
  348. if (colon3)
  349. *(colon3++) = '\0';
  350. tmp = atoi(colon2);
  351. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  352. *asic_count = tmp;
  353. else {
  354. quit(1, "Invalid avalon-options for "
  355. "asic_count (%s) must be 1 ~ %d",
  356. colon2, AVALON_DEFAULT_ASIC_NUM);
  357. }
  358. if (colon3 && *colon3) {
  359. colon4 = strchr(colon3, ':');
  360. if (colon4)
  361. *(colon4++) = '\0';
  362. tmp = atoi(colon3);
  363. if (tmp > 0 && tmp <= 0xff)
  364. *timeout = tmp;
  365. else {
  366. quit(1, "Invalid avalon-options for "
  367. "timeout (%s) must be 1 ~ %d",
  368. colon3, 0xff);
  369. }
  370. if (colon4 && *colon4) {
  371. tmp = atoi(colon4);
  372. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  373. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  374. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  375. }
  376. *frequency = tmp;
  377. }
  378. }
  379. }
  380. }
  381. return true;
  382. }
  383. char *set_avalon_fan(char *arg)
  384. {
  385. int val1, val2, ret;
  386. ret = sscanf(arg, "%d-%d", &val1, &val2);
  387. if (ret < 1)
  388. return "No values passed to avalon-fan";
  389. if (ret == 1)
  390. val2 = val1;
  391. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  392. return "Invalid value passed to avalon-fan";
  393. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  394. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  395. return NULL;
  396. }
  397. char *set_avalon_freq(char *arg)
  398. {
  399. int val1, val2, ret;
  400. ret = sscanf(arg, "%d-%d", &val1, &val2);
  401. if (ret < 1)
  402. return "No values passed to avalon-freq";
  403. if (ret == 1)
  404. val2 = val1;
  405. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  406. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  407. val2 < val1)
  408. return "Invalid value passed to avalon-freq";
  409. opt_avalon_freq_min = val1;
  410. opt_avalon_freq_max = val2;
  411. return NULL;
  412. }
  413. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  414. {
  415. int i;
  416. wait_avalon_ready(avalon);
  417. /* Send idle to all miners */
  418. for (i = 0; i < info->miner_count; i++) {
  419. struct avalon_task at;
  420. if (unlikely(avalon_buffer_full(avalon)))
  421. break;
  422. info->idle++;
  423. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  424. info->asic_count, info->miner_count, 1, 1,
  425. info->frequency);
  426. avalon_send_task(&at, avalon);
  427. }
  428. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  429. wait_avalon_ready(avalon);
  430. }
  431. static void avalon_initialise(struct cgpu_info *avalon)
  432. {
  433. int err, interface;
  434. if (avalon->usbinfo.nodev)
  435. return;
  436. interface = avalon->usbdev->found->interface;
  437. // Reset
  438. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  439. FTDI_VALUE_RESET, interface, C_RESET);
  440. applog(LOG_DEBUG, "%s%i: reset got err %d",
  441. avalon->drv->name, avalon->device_id, err);
  442. if (avalon->usbinfo.nodev)
  443. return;
  444. // Set latency
  445. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  446. AVALON_LATENCY, interface, C_LATENCY);
  447. applog(LOG_DEBUG, "%s%i: latency got err %d",
  448. avalon->drv->name, avalon->device_id, err);
  449. if (avalon->usbinfo.nodev)
  450. return;
  451. // Set data
  452. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  453. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  454. applog(LOG_DEBUG, "%s%i: data got err %d",
  455. avalon->drv->name, avalon->device_id, err);
  456. if (avalon->usbinfo.nodev)
  457. return;
  458. // Set the baud
  459. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  460. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  461. C_SETBAUD);
  462. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  463. avalon->drv->name, avalon->device_id, err);
  464. if (avalon->usbinfo.nodev)
  465. return;
  466. // Set Modem Control
  467. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  468. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  469. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  470. avalon->drv->name, avalon->device_id, err);
  471. if (avalon->usbinfo.nodev)
  472. return;
  473. // Set Flow Control
  474. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  475. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  476. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  477. avalon->drv->name, avalon->device_id, err);
  478. if (avalon->usbinfo.nodev)
  479. return;
  480. /* Avalon repeats the following */
  481. // Set Modem Control
  482. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  483. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  484. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  485. avalon->drv->name, avalon->device_id, err);
  486. if (avalon->usbinfo.nodev)
  487. return;
  488. // Set Flow Control
  489. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  490. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  491. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  492. avalon->drv->name, avalon->device_id, err);
  493. }
  494. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  495. {
  496. uint8_t buf[2];
  497. int err;
  498. if (usb_ident(avalon) == IDENT_BTB) {
  499. buf[0] = (uint8_t)core_voltage;
  500. buf[1] = (uint8_t)(core_voltage >> 8);
  501. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  502. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  503. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  504. if (unlikely(err < 0)) {
  505. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  506. avalon->drv->name, avalon->device_id, err);
  507. return false;
  508. } else {
  509. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  510. avalon->drv->name, avalon->device_id,
  511. core_voltage);
  512. }
  513. return true;
  514. }
  515. return false;
  516. }
  517. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  518. {
  519. uint8_t buf[2];
  520. int err;
  521. int amount;
  522. if (usb_ident(avalon) == IDENT_BTB) {
  523. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  524. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  525. (char *)buf, sizeof(buf), &amount,
  526. C_BB_GET_VOLTAGE);
  527. if (unlikely(err != 0 || amount != 2)) {
  528. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  529. avalon->drv->name, avalon->device_id, err, amount);
  530. return 0;
  531. } else {
  532. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  533. }
  534. } else {
  535. return 0;
  536. }
  537. }
  538. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  539. {
  540. int baud, uninitialised_var(miner_count), uninitialised_var(asic_count),
  541. uninitialised_var(timeout), frequency = 0;
  542. int this_option_offset = ++option_offset;
  543. struct avalon_info *info;
  544. struct cgpu_info *avalon;
  545. bool configured;
  546. int ret;
  547. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  548. configured = get_options(this_option_offset, &baud, &miner_count,
  549. &asic_count, &timeout, &frequency);
  550. if (!usb_init(avalon, dev, found))
  551. goto shin;
  552. /* Even though this is an FTDI type chip, we want to do the parsing
  553. * all ourselves so set it to std usb type */
  554. avalon->usbdev->usb_type = USB_TYPE_STD;
  555. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  556. /* We have a real Avalon! */
  557. avalon_initialise(avalon);
  558. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  559. if (unlikely(!(avalon->device_data)))
  560. quit(1, "Failed to calloc avalon_info data");
  561. info = avalon->device_data;
  562. if (configured) {
  563. info->baud = baud;
  564. info->miner_count = miner_count;
  565. info->asic_count = asic_count;
  566. info->timeout = timeout;
  567. info->frequency = frequency;
  568. } else {
  569. info->baud = AVALON_IO_SPEED;
  570. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  571. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  572. info->timeout = AVALON_DEFAULT_TIMEOUT;
  573. info->frequency = AVALON_DEFAULT_FREQUENCY;
  574. }
  575. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  576. info->temp_max = 0;
  577. /* This is for check the temp/fan every 3~4s */
  578. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  579. if (info->temp_history_count <= 0)
  580. info->temp_history_count = 1;
  581. info->temp_history_index = 0;
  582. info->temp_sum = 0;
  583. info->temp_old = 0;
  584. if (!add_cgpu(avalon))
  585. goto unshin;
  586. ret = avalon_reset(avalon, true);
  587. if (ret && !configured)
  588. goto unshin;
  589. update_usb_stats(avalon);
  590. avalon_idle(avalon, info);
  591. applog(LOG_DEBUG, "Avalon Detected: %s "
  592. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  593. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  594. info->frequency);
  595. if (usb_ident(avalon) == IDENT_BTB) {
  596. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  597. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  598. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  599. opt_bitburner_core_voltage,
  600. BITBURNER_MIN_COREMV,
  601. BITBURNER_MAX_COREMV);
  602. } else
  603. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  604. }
  605. return true;
  606. unshin:
  607. usb_uninit(avalon);
  608. shin:
  609. free(avalon->device_data);
  610. avalon->device_data = NULL;
  611. avalon = usb_free_cgpu(avalon);
  612. return false;
  613. }
  614. static void avalon_detect(void)
  615. {
  616. usb_detect(&avalon_drv, avalon_detect_one);
  617. }
  618. static void avalon_init(struct cgpu_info *avalon)
  619. {
  620. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  621. }
  622. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  623. {
  624. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  625. (char *)ar->data, 64, 12);
  626. }
  627. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  628. struct avalon_result *ar);
  629. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  630. {
  631. applog(LOG_INFO, "%s%d: No matching work - HW error",
  632. thr->cgpu->drv->name, thr->cgpu->device_id);
  633. inc_hw_errors(thr);
  634. info->no_matching_work++;
  635. }
  636. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  637. struct thr_info *thr, char *buf, int *offset)
  638. {
  639. int i, spare = *offset - AVALON_READ_SIZE;
  640. bool found = false;
  641. for (i = 0; i <= spare; i++) {
  642. struct avalon_result *ar;
  643. struct work *work;
  644. ar = (struct avalon_result *)&buf[i];
  645. work = avalon_valid_result(avalon, ar);
  646. if (work) {
  647. bool gettemp = false;
  648. found = true;
  649. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  650. mutex_lock(&info->lock);
  651. if (!info->nonces++)
  652. gettemp = true;
  653. info->auto_nonces++;
  654. mutex_unlock(&info->lock);
  655. } else if (opt_avalon_auto) {
  656. mutex_lock(&info->lock);
  657. info->auto_hw++;
  658. mutex_unlock(&info->lock);
  659. }
  660. free_work(work);
  661. if (gettemp)
  662. avalon_update_temps(avalon, info, ar);
  663. break;
  664. }
  665. }
  666. if (!found) {
  667. spare = *offset - AVALON_READ_SIZE;
  668. /* We are buffering and haven't accumulated one more corrupt
  669. * work result. */
  670. if (spare < (int)AVALON_READ_SIZE)
  671. return;
  672. avalon_inc_nvw(info, thr);
  673. } else {
  674. spare = AVALON_READ_SIZE + i;
  675. if (i) {
  676. if (i >= (int)AVALON_READ_SIZE)
  677. avalon_inc_nvw(info, thr);
  678. else
  679. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  680. }
  681. }
  682. *offset -= spare;
  683. memmove(buf, buf + spare, *offset);
  684. }
  685. static void avalon_running_reset(struct cgpu_info *avalon,
  686. struct avalon_info *info)
  687. {
  688. avalon_reset(avalon, false);
  689. avalon_idle(avalon, info);
  690. avalon->results = 0;
  691. info->reset = false;
  692. }
  693. static void *avalon_get_results(void *userdata)
  694. {
  695. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  696. struct avalon_info *info = avalon->device_data;
  697. int offset = 0, read_delay = 0, ret = 0;
  698. const int rsize = AVALON_FTDI_READSIZE;
  699. char readbuf[AVALON_READBUF_SIZE];
  700. struct thr_info *thr = info->thr;
  701. struct timeval tv_start, tv_end;
  702. char threadname[24];
  703. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  704. RenameThread(threadname);
  705. while (likely(!avalon->shutdown)) {
  706. unsigned char buf[rsize];
  707. struct timeval tv_diff;
  708. int us_diff;
  709. if (offset >= (int)AVALON_READ_SIZE)
  710. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  711. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  712. /* This should never happen */
  713. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  714. offset = 0;
  715. }
  716. if (unlikely(info->reset)) {
  717. avalon_running_reset(avalon, info);
  718. /* Discard anything in the buffer */
  719. offset = 0;
  720. }
  721. /* As the usb read returns after just 1ms, sleep long enough
  722. * to leave the interface idle for writes to occur, but do not
  723. * sleep if we have been receiving data as more may be coming. */
  724. if (ret < 1) {
  725. cgtime(&tv_end);
  726. timersub(&tv_end, &tv_start, &tv_diff);
  727. /* Assume it has not been > 1 second so ignore tv_sec */
  728. us_diff = tv_diff.tv_usec;
  729. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  730. if (likely(read_delay >= 1000))
  731. nusleep(read_delay);
  732. }
  733. cgtime(&tv_start);
  734. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  735. C_AVALON_READ);
  736. if (ret < 1)
  737. continue;
  738. if (opt_debug) {
  739. applog(LOG_DEBUG, "Avalon: get:");
  740. hexdump((uint8_t *)buf, ret);
  741. }
  742. memcpy(&readbuf[offset], &buf, ret);
  743. offset += ret;
  744. }
  745. return NULL;
  746. }
  747. static void avalon_rotate_array(struct cgpu_info *avalon)
  748. {
  749. avalon->queued = 0;
  750. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  751. avalon->work_array = 0;
  752. }
  753. static void avalon_set_timeout(struct avalon_info *info)
  754. {
  755. info->timeout = AVALON_TIMEOUT_FACTOR / info->frequency;
  756. }
  757. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  758. {
  759. struct avalon_info *info = avalon->device_data;
  760. info->frequency = frequency;
  761. if (info->frequency > opt_avalon_freq_max)
  762. info->frequency = opt_avalon_freq_max;
  763. if (info->frequency < opt_avalon_freq_min)
  764. info->frequency = opt_avalon_freq_min;
  765. avalon_set_timeout(info);
  766. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  767. avalon->drv->name, avalon->device_id,
  768. info->frequency, info->timeout);
  769. }
  770. static void avalon_inc_freq(struct avalon_info *info)
  771. {
  772. info->frequency += 2;
  773. if (info->frequency > opt_avalon_freq_max)
  774. info->frequency = opt_avalon_freq_max;
  775. avalon_set_timeout(info);
  776. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  777. info->frequency, info->timeout);
  778. }
  779. static void avalon_dec_freq(struct avalon_info *info)
  780. {
  781. info->frequency -= 1;
  782. if (info->frequency < opt_avalon_freq_min)
  783. info->frequency = opt_avalon_freq_min;
  784. avalon_set_timeout(info);
  785. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  786. info->frequency, info->timeout);
  787. }
  788. static void avalon_reset_auto(struct avalon_info *info)
  789. {
  790. info->auto_queued =
  791. info->auto_nonces =
  792. info->auto_hw = 0;
  793. }
  794. static void *avalon_send_tasks(void *userdata)
  795. {
  796. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  797. struct avalon_info *info = avalon->device_data;
  798. const int avalon_get_work_count = info->miner_count;
  799. char threadname[24];
  800. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  801. RenameThread(threadname);
  802. while (likely(!avalon->shutdown)) {
  803. int start_count, end_count, i, j, ret;
  804. struct avalon_task at;
  805. bool idled = false;
  806. while (avalon_buffer_full(avalon))
  807. nmsleep(40);
  808. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  809. mutex_lock(&info->lock);
  810. if (!info->optimal) {
  811. if (info->fan_pwm >= opt_avalon_fan_max) {
  812. applog(LOG_WARNING,
  813. "%s%i: Above optimal temperature, throttling",
  814. avalon->drv->name, avalon->device_id);
  815. avalon_dec_freq(info);
  816. }
  817. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  818. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  819. int total = info->auto_nonces + info->auto_hw;
  820. /* Try to keep hw errors < 2% */
  821. if (info->auto_hw * 100 < total)
  822. avalon_inc_freq(info);
  823. else if (info->auto_hw * 66 > total)
  824. avalon_dec_freq(info);
  825. }
  826. avalon_reset_auto(info);
  827. mutex_unlock(&info->lock);
  828. }
  829. mutex_lock(&info->qlock);
  830. start_count = avalon->work_array * avalon_get_work_count;
  831. end_count = start_count + avalon_get_work_count;
  832. for (i = start_count, j = 0; i < end_count; i++, j++) {
  833. if (avalon_buffer_full(avalon)) {
  834. applog(LOG_INFO,
  835. "%s%i: Buffer full after only %d of %d work queued",
  836. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  837. if (usb_ident(avalon) != IDENT_BTB)
  838. break;
  839. else {
  840. while (avalon_buffer_full(avalon))
  841. nmsleep(40);
  842. }
  843. }
  844. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  845. avalon_init_task(&at, 0, 0, info->fan_pwm,
  846. info->timeout, info->asic_count,
  847. info->miner_count, 1, 0, info->frequency);
  848. avalon_create_task(&at, avalon->works[i]);
  849. info->auto_queued++;
  850. } else {
  851. int idle_freq = info->frequency;
  852. if (!info->idle++)
  853. idled = true;
  854. if (unlikely(info->overheat && opt_avalon_auto))
  855. idle_freq = AVALON_MIN_FREQUENCY;
  856. avalon_init_task(&at, 0, 0, info->fan_pwm,
  857. info->timeout, info->asic_count,
  858. info->miner_count, 1, 1, idle_freq);
  859. /* Reset the auto_queued count if we end up
  860. * idling any miners. */
  861. avalon_reset_auto(info);
  862. }
  863. ret = avalon_send_task(&at, avalon);
  864. if (unlikely(ret == AVA_SEND_ERROR)) {
  865. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  866. avalon->drv->name, avalon->device_id);
  867. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  868. info->reset = true;
  869. break;
  870. }
  871. }
  872. avalon_rotate_array(avalon);
  873. pthread_cond_signal(&info->qcond);
  874. mutex_unlock(&info->qlock);
  875. if (unlikely(idled)) {
  876. applog(LOG_WARNING, "%s%i: Idled %d miners",
  877. avalon->drv->name, avalon->device_id, idled);
  878. }
  879. }
  880. return NULL;
  881. }
  882. static bool avalon_prepare(struct thr_info *thr)
  883. {
  884. struct cgpu_info *avalon = thr->cgpu;
  885. struct avalon_info *info = avalon->device_data;
  886. free(avalon->works);
  887. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  888. AVALON_ARRAY_SIZE);
  889. if (!avalon->works)
  890. quit(1, "Failed to calloc avalon works in avalon_prepare");
  891. info->thr = thr;
  892. mutex_init(&info->lock);
  893. mutex_init(&info->qlock);
  894. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  895. quit(1, "Failed to pthread_cond_init avalon qcond");
  896. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  897. quit(1, "Failed to create avalon read_thr");
  898. if (pthread_create(&info->write_thr, NULL, avalon_send_tasks, (void *)avalon))
  899. quit(1, "Failed to create avalon write_thr");
  900. avalon_init(avalon);
  901. return true;
  902. }
  903. static void do_avalon_close(struct thr_info *thr)
  904. {
  905. struct cgpu_info *avalon = thr->cgpu;
  906. struct avalon_info *info = avalon->device_data;
  907. pthread_join(info->read_thr, NULL);
  908. pthread_join(info->write_thr, NULL);
  909. avalon_running_reset(avalon, info);
  910. info->no_matching_work = 0;
  911. }
  912. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  913. {
  914. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  915. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  916. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  917. info->temp0 = ar->temp0;
  918. info->temp1 = ar->temp1;
  919. info->temp2 = ar->temp2;
  920. if (ar->temp0 & 0x80) {
  921. ar->temp0 &= 0x7f;
  922. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  923. }
  924. if (ar->temp1 & 0x80) {
  925. ar->temp1 &= 0x7f;
  926. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  927. }
  928. if (ar->temp2 & 0x80) {
  929. ar->temp2 &= 0x7f;
  930. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  931. }
  932. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  933. if (info->temp0 > info->temp_max)
  934. info->temp_max = info->temp0;
  935. if (info->temp1 > info->temp_max)
  936. info->temp_max = info->temp1;
  937. if (info->temp2 > info->temp_max)
  938. info->temp_max = info->temp2;
  939. }
  940. static void temp_rise(struct avalon_info *info, int temp)
  941. {
  942. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  943. info->fan_pwm = AVALON_PWM_MAX;
  944. return;
  945. }
  946. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  947. info->fan_pwm += 10;
  948. else if (temp > opt_avalon_temp)
  949. info->fan_pwm += 5;
  950. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  951. info->fan_pwm += 1;
  952. else
  953. return;
  954. if (info->fan_pwm > opt_avalon_fan_max)
  955. info->fan_pwm = opt_avalon_fan_max;
  956. }
  957. static void temp_drop(struct avalon_info *info, int temp)
  958. {
  959. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  960. info->fan_pwm = opt_avalon_fan_min;
  961. return;
  962. }
  963. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  964. info->fan_pwm -= 10;
  965. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  966. info->fan_pwm -= 5;
  967. else if (temp < opt_avalon_temp)
  968. info->fan_pwm -= 1;
  969. if (info->fan_pwm < opt_avalon_fan_min)
  970. info->fan_pwm = opt_avalon_fan_min;
  971. }
  972. static inline void adjust_fan(struct avalon_info *info)
  973. {
  974. int temp_new;
  975. temp_new = info->temp_sum / info->temp_history_count;
  976. if (temp_new > info->temp_old)
  977. temp_rise(info, temp_new);
  978. else if (temp_new < info->temp_old)
  979. temp_drop(info, temp_new);
  980. else {
  981. /* temp_new == info->temp_old */
  982. if (temp_new > opt_avalon_temp)
  983. temp_rise(info, temp_new);
  984. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  985. temp_drop(info, temp_new);
  986. }
  987. info->temp_old = temp_new;
  988. if (info->temp_old <= opt_avalon_temp)
  989. info->optimal = true;
  990. else
  991. info->optimal = false;
  992. }
  993. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  994. struct avalon_result *ar)
  995. {
  996. record_temp_fan(info, ar, &(avalon->temp));
  997. applog(LOG_INFO,
  998. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  999. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1000. info->fan0, info->fan1, info->fan2,
  1001. info->temp0, info->temp1, info->temp2, info->temp_max);
  1002. info->temp_history_index++;
  1003. info->temp_sum += avalon->temp;
  1004. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1005. info->temp_history_index, info->temp_history_count, info->temp_old);
  1006. if (usb_ident(avalon) == IDENT_BTB) {
  1007. info->core_voltage = bitburner_get_core_voltage(avalon);
  1008. }
  1009. if (info->temp_history_index == info->temp_history_count) {
  1010. adjust_fan(info);
  1011. info->temp_history_index = 0;
  1012. info->temp_sum = 0;
  1013. }
  1014. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1015. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1016. info->overheat = true;
  1017. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1018. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1019. info->overheat = false;
  1020. }
  1021. }
  1022. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1023. {
  1024. struct avalon_info *info = avalon->device_data;
  1025. int lowfan = 10000;
  1026. if (usb_ident(avalon) == IDENT_BTB) {
  1027. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1028. } else {
  1029. /* Find the lowest fan speed of the ASIC cooling fans. */
  1030. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1031. lowfan = info->fan1;
  1032. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1033. lowfan = info->fan2;
  1034. tailsprintf(buf, bufsiz, "%2d/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1035. }
  1036. }
  1037. /* We use a replacement algorithm to only remove references to work done from
  1038. * the buffer when we need the extra space for new work. */
  1039. static bool avalon_fill(struct cgpu_info *avalon)
  1040. {
  1041. struct avalon_info *info = avalon->device_data;
  1042. int subid, slot, mc;
  1043. struct work *work;
  1044. bool ret = true;
  1045. mc = info->miner_count;
  1046. mutex_lock(&info->qlock);
  1047. if (avalon->queued >= mc)
  1048. goto out_unlock;
  1049. work = get_queued(avalon);
  1050. if (unlikely(!work)) {
  1051. ret = false;
  1052. goto out_unlock;
  1053. }
  1054. subid = avalon->queued++;
  1055. work->subid = subid;
  1056. slot = avalon->work_array * mc + subid;
  1057. if (likely(avalon->works[slot]))
  1058. work_completed(avalon, avalon->works[slot]);
  1059. avalon->works[slot] = work;
  1060. if (avalon->queued < mc)
  1061. ret = false;
  1062. out_unlock:
  1063. mutex_unlock(&info->qlock);
  1064. return ret;
  1065. }
  1066. static int64_t avalon_scanhash(struct thr_info *thr)
  1067. {
  1068. struct cgpu_info *avalon = thr->cgpu;
  1069. struct avalon_info *info = avalon->device_data;
  1070. const int miner_count = info->miner_count;
  1071. struct timeval now, then, tdiff;
  1072. int64_t hash_count, us_timeout;
  1073. struct timespec abstime;
  1074. /* Half nonce range */
  1075. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1076. tdiff.tv_sec = us_timeout / 1000000;
  1077. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  1078. cgtime(&now);
  1079. timeradd(&now, &tdiff, &then);
  1080. abstime.tv_sec = then.tv_sec;
  1081. abstime.tv_nsec = then.tv_usec * 1000;
  1082. /* Wait until avalon_send_tasks signals us that it has completed
  1083. * sending its work or a full nonce range timeout has occurred */
  1084. mutex_lock(&info->qlock);
  1085. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1086. mutex_unlock(&info->qlock);
  1087. mutex_lock(&info->lock);
  1088. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1089. avalon->results += info->nonces + info->idle;
  1090. if (avalon->results > miner_count)
  1091. avalon->results = miner_count;
  1092. if (!info->reset)
  1093. avalon->results--;
  1094. info->nonces = info->idle = 0;
  1095. mutex_unlock(&info->lock);
  1096. /* Check for nothing but consecutive bad results or consistently less
  1097. * results than we should be getting and reset the FPGA if necessary */
  1098. if (usb_ident(avalon) != IDENT_BTB) {
  1099. if (avalon->results < -miner_count && !info->reset) {
  1100. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1101. avalon->drv->name, avalon->device_id);
  1102. info->reset = true;
  1103. }
  1104. }
  1105. if (unlikely(avalon->usbinfo.nodev)) {
  1106. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1107. avalon->drv->name, avalon->device_id);
  1108. avalon->shutdown = true;
  1109. }
  1110. /* This hashmeter is just a utility counter based on returned shares */
  1111. return hash_count;
  1112. }
  1113. static void avalon_flush_work(struct cgpu_info *avalon)
  1114. {
  1115. struct avalon_info *info = avalon->device_data;
  1116. mutex_lock(&info->qlock);
  1117. /* Will overwrite any work queued */
  1118. avalon->queued = 0;
  1119. pthread_cond_signal(&info->qcond);
  1120. mutex_unlock(&info->qlock);
  1121. }
  1122. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1123. {
  1124. struct api_data *root = NULL;
  1125. struct avalon_info *info = cgpu->device_data;
  1126. int i;
  1127. root = api_add_int(root, "baud", &(info->baud), false);
  1128. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1129. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1130. root = api_add_int(root, "timeout", &(info->timeout), false);
  1131. root = api_add_int(root, "frequency", &(info->frequency), false);
  1132. root = api_add_int(root, "fan1", &(info->fan0), false);
  1133. root = api_add_int(root, "fan2", &(info->fan1), false);
  1134. root = api_add_int(root, "fan3", &(info->fan2), false);
  1135. root = api_add_int(root, "temp1", &(info->temp0), false);
  1136. root = api_add_int(root, "temp2", &(info->temp1), false);
  1137. root = api_add_int(root, "temp3", &(info->temp2), false);
  1138. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1139. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1140. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1141. for (i = 0; i < info->miner_count; i++) {
  1142. char mcw[24];
  1143. sprintf(mcw, "match_work_count%d", i + 1);
  1144. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1145. }
  1146. return root;
  1147. }
  1148. static void avalon_shutdown(struct thr_info *thr)
  1149. {
  1150. do_avalon_close(thr);
  1151. }
  1152. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1153. {
  1154. int val;
  1155. if (strcasecmp(option, "help") == 0) {
  1156. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1157. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1158. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1159. return replybuf;
  1160. }
  1161. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1162. if (usb_ident(avalon) != IDENT_BTB) {
  1163. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1164. return replybuf;
  1165. }
  1166. if (!setting || !*setting) {
  1167. sprintf(replybuf, "missing millivolts setting");
  1168. return replybuf;
  1169. }
  1170. val = atoi(setting);
  1171. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1172. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1173. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1174. return replybuf;
  1175. }
  1176. if (bitburner_set_core_voltage(avalon, val))
  1177. return NULL;
  1178. else {
  1179. sprintf(replybuf, "Set millivolts failed");
  1180. return replybuf;
  1181. }
  1182. }
  1183. if (strcasecmp(option, "freq") == 0) {
  1184. if (!setting || !*setting) {
  1185. sprintf(replybuf, "missing freq setting");
  1186. return replybuf;
  1187. }
  1188. val = atoi(setting);
  1189. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1190. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1191. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1192. return replybuf;
  1193. }
  1194. avalon_set_freq(avalon, val);
  1195. return NULL;
  1196. }
  1197. sprintf(replybuf, "Unknown option: %s", option);
  1198. return replybuf;
  1199. }
  1200. struct device_drv avalon_drv = {
  1201. .drv_id = DRIVER_AVALON,
  1202. .dname = "avalon",
  1203. .name = "AVA",
  1204. .drv_detect = avalon_detect,
  1205. .thread_prepare = avalon_prepare,
  1206. .hash_work = hash_queued_work,
  1207. .queue_full = avalon_fill,
  1208. .scanwork = avalon_scanhash,
  1209. .flush_work = avalon_flush_work,
  1210. .get_api_stats = avalon_api_stats,
  1211. .get_statline_before = get_avalon_statline_before,
  1212. .set_device = avalon_set_device,
  1213. .reinit_device = avalon_init,
  1214. .thread_shutdown = avalon_shutdown,
  1215. };