driver-avalon.c 22 KB

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  1. /*
  2. * Copyright 2012 Luke Dashjr
  3. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. /*
  12. * Those code should be works fine with V2 and V3 bitstream of Avalon.
  13. * Operation:
  14. * No detection implement.
  15. * Input: 64B = 32B midstate + 20B fill bytes + last 12 bytes of block head.
  16. * Return: send back 32bits immediately when Avalon found a valid nonce.
  17. * no query protocol implemented here, if no data send back in ~11.3
  18. * seconds (full cover time on 32bit nonce range by 380MH/s speed)
  19. * just send another work.
  20. * Notice:
  21. * 1. Avalon will start calculate when you push a work to them, even they
  22. * are busy.
  23. * 2. The 2 FPGAs on Avalon will distribute the job, one will calculate the
  24. * 0 ~ 7FFFFFFF, another one will cover the 80000000 ~ FFFFFFFF.
  25. * 3. It's possible for 2 FPGAs both find valid nonce in the meantime, the 2
  26. * valid nonce will all be send back.
  27. * 4. Avalon will stop work when: a valid nonce has been found or 32 bits
  28. * nonce range is completely calculated.
  29. */
  30. #include "config.h"
  31. #include <limits.h>
  32. #include <pthread.h>
  33. #include <stdio.h>
  34. #include <sys/time.h>
  35. #include <sys/types.h>
  36. #include <dirent.h>
  37. #include <unistd.h>
  38. #ifndef WIN32
  39. #include <termios.h>
  40. #include <sys/stat.h>
  41. #include <fcntl.h>
  42. #ifndef O_CLOEXEC
  43. #define O_CLOEXEC 0
  44. #endif
  45. #else
  46. #include <windows.h>
  47. #include <io.h>
  48. #endif
  49. #include "elist.h"
  50. #include "miner.h"
  51. #include "fpgautils.h"
  52. #include "driver-avalon.h"
  53. static struct timeval history_sec = { HISTORY_SEC, 0 };
  54. static const char *MODE_DEFAULT_STR = "default";
  55. static const char *MODE_SHORT_STR = "short";
  56. static const char *MODE_LONG_STR = "long";
  57. static const char *MODE_VALUE_STR = "value";
  58. static const char *MODE_UNKNOWN_STR = "unknown";
  59. // One for each possible device
  60. static struct AVALON_INFO **avalon_info;
  61. // Looking for options in --avalon-timing and --avalon-options:
  62. //
  63. // Code increments this each time we start to look at a device
  64. // However, this means that if other devices are checked by
  65. // the Avalon code (e.g. BFL) they will count in the option offset
  66. //
  67. // This, however, is deterministic so that's OK
  68. //
  69. // If we were to increment after successfully finding an Avalon
  70. // that would be random since an Avalon may fail and thus we'd
  71. // not be able to predict the option order
  72. //
  73. // This also assumes that serial_detect() checks them sequentially
  74. // and in the order specified on the command line
  75. //
  76. static int option_offset = -1;
  77. struct device_api avalon_api;
  78. static void rev(uint8_t *s, size_t l)
  79. {
  80. size_t i, j;
  81. uint8_t t;
  82. for (i = 0, j = l - 1; i < j; i++, j--) {
  83. t = s[i];
  84. s[i] = s[j];
  85. s[j] = t;
  86. }
  87. }
  88. static inline void avalon_create_task(uint8_t *ob_bin, struct work *work)
  89. {
  90. memset(ob_bin, 0, sizeof(ob_bin));
  91. memcpy(ob_bin, work->midstate, 32);
  92. memcpy(ob_bin + 52, work->data + 64, 12);
  93. rev(ob_bin, 32);
  94. rev(ob_bin + 52, 12);
  95. }
  96. static int avalon_gets(uint8_t *buf, int fd, struct timeval *tv_finish,
  97. struct thr_info *thr, int read_count)
  98. {
  99. ssize_t ret = 0;
  100. int rc = 0;
  101. int read_amount = AVALON_READ_SIZE;
  102. bool first = true;
  103. int cts = get_serial_cts(fd);
  104. if (opt_debug)
  105. applog(LOG_DEBUG, "Avalon bulk task statue: %d", cts);
  106. if (cts) {
  107. /* TODO return here. and tell avalon all task are done */
  108. }
  109. // Read reply 1 byte at a time to get earliest tv_finish
  110. while (true) {
  111. ret = read(fd, buf, 1);
  112. if (ret < 0)
  113. return AVA_GETS_ERROR;
  114. if (first)
  115. gettimeofday(tv_finish, NULL);
  116. if (ret >= read_amount)
  117. return AVA_GETS_OK;
  118. if (ret > 0) {
  119. buf += ret;
  120. read_amount -= ret;
  121. first = false;
  122. continue;
  123. }
  124. rc++;
  125. if (rc >= read_count) {
  126. if (opt_debug) {
  127. applog(LOG_DEBUG,
  128. "Avalon Read: No data in %.2f seconds",
  129. (float)rc/(float)TIME_FACTOR);
  130. }
  131. return AVA_GETS_TIMEOUT;
  132. }
  133. if (thr && thr->work_restart) {
  134. if (opt_debug) {
  135. applog(LOG_DEBUG,
  136. "Avalon Read: Work restart at %.2f seconds",
  137. (float)(rc)/(float)TIME_FACTOR);
  138. }
  139. return AVA_GETS_RESTART;
  140. }
  141. }
  142. }
  143. static int avalon_read_work(uint8_t *nonce_bin, int fd,
  144. struct timeval *tv_finish, struct thr_info *thr)
  145. {
  146. /* TODO: create a globle buffer match that buffer retrun the work*/
  147. struct cgpu_info *avalon = thr->cgpu;
  148. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  149. int ret;
  150. memset(nonce_bin, 0, AVALON_READ_SIZE);
  151. ret = avalon_gets(nonce_bin, fd, tv_finish, thr, info->read_count);
  152. return ret;
  153. }
  154. static int avalon_submit_nonce(uint8_t *ob_bin)
  155. {
  156. return 0;
  157. }
  158. static int avalon_send_task(int fd, const void *buf, size_t bufLen)
  159. {
  160. size_t ret;
  161. ret = write(fd, buf, bufLen);
  162. if (unlikely(ret != bufLen))
  163. return 1;
  164. /* FIXME: there should be a nanosleep() according to the document */
  165. return 0;
  166. }
  167. #define avalon_close(fd) close(fd)
  168. static void do_avalon_close(struct thr_info *thr)
  169. {
  170. struct cgpu_info *avalon = thr->cgpu;
  171. avalon_close(avalon->device_fd);
  172. avalon->device_fd = -1;
  173. }
  174. static const char *timing_mode_str(enum timing_mode timing_mode)
  175. {
  176. switch(timing_mode) {
  177. case MODE_DEFAULT:
  178. return MODE_DEFAULT_STR;
  179. case MODE_SHORT:
  180. return MODE_SHORT_STR;
  181. case MODE_LONG:
  182. return MODE_LONG_STR;
  183. case MODE_VALUE:
  184. return MODE_VALUE_STR;
  185. default:
  186. return MODE_UNKNOWN_STR;
  187. }
  188. }
  189. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  190. {
  191. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  192. double Hs;
  193. char buf[BUFSIZ+1];
  194. char *ptr, *comma, *eq;
  195. size_t max;
  196. int i;
  197. if (opt_icarus_timing == NULL)
  198. buf[0] = '\0';
  199. else {
  200. ptr = opt_icarus_timing;
  201. for (i = 0; i < this_option_offset; i++) {
  202. comma = strchr(ptr, ',');
  203. if (comma == NULL)
  204. break;
  205. ptr = comma + 1;
  206. }
  207. comma = strchr(ptr, ',');
  208. if (comma == NULL)
  209. max = strlen(ptr);
  210. else
  211. max = comma - ptr;
  212. if (max > BUFSIZ)
  213. max = BUFSIZ;
  214. strncpy(buf, ptr, max);
  215. buf[max] = '\0';
  216. }
  217. info->Hs = 0;
  218. info->read_count = 0;
  219. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  220. info->Hs = AVALON_REV3_HASH_TIME;
  221. info->read_count = AVALON_READ_COUNT_TIMING;
  222. info->timing_mode = MODE_SHORT;
  223. info->do_avalon_timing = true;
  224. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  225. info->Hs = AVALON_REV3_HASH_TIME;
  226. info->read_count = AVALON_READ_COUNT_TIMING;
  227. info->timing_mode = MODE_LONG;
  228. info->do_avalon_timing = true;
  229. } else if ((Hs = atof(buf)) != 0) {
  230. info->Hs = Hs / NANOSEC;
  231. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  232. if ((eq = strchr(buf, '=')) != NULL)
  233. info->read_count = atoi(eq+1);
  234. if (info->read_count < 1)
  235. info->read_count =
  236. (int)(info->fullnonce * TIME_FACTOR) - 1;
  237. if (unlikely(info->read_count < 1))
  238. info->read_count = 1;
  239. info->timing_mode = MODE_VALUE;
  240. info->do_avalon_timing = false;
  241. } else {
  242. // Anything else in buf just uses DEFAULT mode
  243. info->Hs = AVALON_REV3_HASH_TIME;
  244. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  245. if ((eq = strchr(buf, '=')) != NULL)
  246. info->read_count = atoi(eq+1);
  247. if (info->read_count < 1)
  248. info->read_count =
  249. (int)(info->fullnonce * TIME_FACTOR) - 1;
  250. info->timing_mode = MODE_DEFAULT;
  251. info->do_avalon_timing = false;
  252. }
  253. info->min_data_count = MIN_DATA_COUNT;
  254. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  255. avalon->device_id, timing_mode_str(info->timing_mode),
  256. info->read_count, info->Hs);
  257. }
  258. static uint32_t mask(int work_division)
  259. {
  260. char err_buf[BUFSIZ+1];
  261. uint32_t nonce_mask = 0x7fffffff;
  262. // yes we can calculate these,
  263. // but this way it's easy to see what they are
  264. switch (work_division) {
  265. case 1:
  266. nonce_mask = 0xffffffff;
  267. break;
  268. case 2:
  269. nonce_mask = 0x7fffffff;
  270. break;
  271. case 4:
  272. nonce_mask = 0x3fffffff;
  273. break;
  274. case 8:
  275. nonce_mask = 0x1fffffff;
  276. break;
  277. default:
  278. sprintf(err_buf,
  279. "Invalid2 avalon-options for work_division (%d)"
  280. " must be 1, 2, 4 or 8", work_division);
  281. quit(1, err_buf);
  282. }
  283. return nonce_mask;
  284. }
  285. static void get_options(int this_option_offset, int *baud, int *work_division,
  286. int *asic_count)
  287. {
  288. char err_buf[BUFSIZ+1];
  289. char buf[BUFSIZ+1];
  290. char *ptr, *comma, *colon, *colon2;
  291. size_t max;
  292. int i, tmp;
  293. if (opt_icarus_options == NULL)
  294. buf[0] = '\0';
  295. else {
  296. ptr = opt_icarus_options;
  297. for (i = 0; i < this_option_offset; i++) {
  298. comma = strchr(ptr, ',');
  299. if (comma == NULL)
  300. break;
  301. ptr = comma + 1;
  302. }
  303. comma = strchr(ptr, ',');
  304. if (comma == NULL)
  305. max = strlen(ptr);
  306. else
  307. max = comma - ptr;
  308. if (max > BUFSIZ)
  309. max = BUFSIZ;
  310. strncpy(buf, ptr, max);
  311. buf[max] = '\0';
  312. }
  313. *baud = AVALON_IO_SPEED;
  314. *work_division = 2;
  315. *asic_count = 2;
  316. if (*buf) {
  317. colon = strchr(buf, ':');
  318. if (colon)
  319. *(colon++) = '\0';
  320. if (*buf) {
  321. tmp = atoi(buf);
  322. switch (tmp) {
  323. case 115200:
  324. *baud = 115200;
  325. break;
  326. case 57600:
  327. *baud = 57600;
  328. break;
  329. default:
  330. sprintf(err_buf,
  331. "Invalid avalon-options for baud (%s) "
  332. "must be 115200 or 57600", buf);
  333. quit(1, err_buf);
  334. }
  335. }
  336. if (colon && *colon) {
  337. colon2 = strchr(colon, ':');
  338. if (colon2)
  339. *(colon2++) = '\0';
  340. if (*colon) {
  341. tmp = atoi(colon);
  342. if (tmp == 1 || tmp == 2 ||
  343. tmp == 4 || tmp == 8) {
  344. *work_division = tmp;
  345. // default to the same
  346. *asic_count = tmp;
  347. } else {
  348. sprintf(err_buf,
  349. "Invalid avalon-options for "
  350. "work_division (%s) must be 1,"
  351. " 2, 4 or 8", colon);
  352. quit(1, err_buf);
  353. }
  354. }
  355. if (colon2 && *colon2) {
  356. tmp = atoi(colon2);
  357. if (tmp > 0 && tmp <= *work_division)
  358. *asic_count = tmp;
  359. else {
  360. sprintf(err_buf,
  361. "Invalid avalon-options for "
  362. "asic_count (%s) must be >0 "
  363. "and <=work_division (%d)",
  364. colon2, *work_division);
  365. quit(1, err_buf);
  366. }
  367. }
  368. }
  369. }
  370. }
  371. static bool avalon_detect_one(const char *devpath)
  372. {
  373. int this_option_offset = ++option_offset;
  374. struct AVALON_INFO *info;
  375. struct timeval tv_start, tv_finish;
  376. int fd;
  377. // Block 171874 nonce = (0xa2870100) = 0x000187a2
  378. // N.B. golden_ob MUST take less time to calculate
  379. // than the timeout set in avalon_open()
  380. // This one takes ~0.53ms on Rev3 Avalon
  381. const char golden_ob[] =
  382. "4679ba4ec99876bf4bfe086082b40025"
  383. "4df6c356451471139a3afa71e48f544a"
  384. "00000000000000000000000000000000"
  385. "0000000087320b1a1426674f2fa722ce";
  386. const char golden_nonce[] = "000187a2";
  387. const uint32_t golden_nonce_val = 0x000187a2;
  388. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  389. char *nonce_hex;
  390. int baud, work_division, asic_count;
  391. get_options(this_option_offset, &baud, &work_division, &asic_count);
  392. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  393. fd = avalon_open2(devpath, baud, true);
  394. if (unlikely(fd == -1)) {
  395. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  396. return false;
  397. }
  398. hex2bin(ob_bin, golden_ob, sizeof(ob_bin));
  399. avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  400. gettimeofday(&tv_start, NULL);
  401. memset(nonce_bin, 0, sizeof(nonce_bin));
  402. avalon_gets(nonce_bin, fd, &tv_finish, NULL, 1);
  403. avalon_close(fd);
  404. nonce_hex = bin2hex(nonce_bin, sizeof(nonce_bin));
  405. if (strncmp(nonce_hex, golden_nonce, 8)) {
  406. applog(LOG_ERR,
  407. "Avalon Detect: "
  408. "Test failed at %s: get %s, should: %s",
  409. devpath, nonce_hex, golden_nonce);
  410. free(nonce_hex);
  411. return false;
  412. }
  413. applog(LOG_DEBUG,
  414. "Avalon Detect: "
  415. "Test succeeded at %s: got %s",
  416. devpath, nonce_hex);
  417. free(nonce_hex);
  418. /* We have a real Avalon! */
  419. struct cgpu_info *avalon;
  420. avalon = calloc(1, sizeof(struct cgpu_info));
  421. avalon->api = &avalon_api;
  422. avalon->device_path = strdup(devpath);
  423. avalon->device_fd = -1;
  424. avalon->threads = AVALON_MINER_THREADS;
  425. add_cgpu(avalon);
  426. avalon_info = realloc(avalon_info,
  427. sizeof(struct AVALON_INFO *) *
  428. (total_devices + 1));
  429. applog(LOG_INFO, "Found Avalon at %s, mark as %d",
  430. devpath, avalon->device_id);
  431. applog(LOG_DEBUG,
  432. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  433. avalon->device_id, baud, work_division, asic_count);
  434. // Since we are adding a new device on the end it
  435. // needs to always be allocated
  436. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  437. malloc(sizeof(struct AVALON_INFO));
  438. if (unlikely(!(avalon_info[avalon->device_id])))
  439. quit(1, "Failed to malloc AVALON_INFO");
  440. info = avalon_info[avalon->device_id];
  441. // Initialise everything to zero for a new device
  442. memset(info, 0, sizeof(struct AVALON_INFO));
  443. info->baud = baud;
  444. info->work_division = work_division;
  445. info->asic_count = asic_count;
  446. info->nonce_mask = mask(work_division);
  447. info->golden_hashes = (golden_nonce_val & info->nonce_mask) *
  448. asic_count;
  449. timersub(&tv_finish, &tv_start, &(info->golden_tv));
  450. set_timing_mode(this_option_offset, avalon);
  451. return true;
  452. }
  453. static void avalon_detect()
  454. {
  455. serial_detect(&avalon_api, avalon_detect_one);
  456. }
  457. static bool avalon_prepare(struct thr_info *thr)
  458. {
  459. struct cgpu_info *avalon = thr->cgpu;
  460. struct timeval now;
  461. avalon->device_fd = -1;
  462. int fd = avalon_open(avalon->device_path,
  463. avalon_info[avalon->device_id]->baud);
  464. if (unlikely(-1 == fd)) {
  465. applog(LOG_ERR, "Failed to open Avalon on %s",
  466. avalon->device_path);
  467. return false;
  468. }
  469. avalon->device_fd = fd;
  470. applog(LOG_INFO, "Opened Avalon on %s", avalon->device_path);
  471. gettimeofday(&now, NULL);
  472. get_datestamp(avalon->init, &now);
  473. return true;
  474. }
  475. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  476. __maybe_unused int64_t max_nonce)
  477. {
  478. struct cgpu_info *avalon;
  479. int fd;
  480. int ret;
  481. struct AVALON_INFO *info;
  482. uint8_t ob_bin[64], nonce_bin[AVALON_READ_SIZE];
  483. char *ob_hex;
  484. uint32_t nonce;
  485. int64_t hash_count;
  486. struct timeval tv_start, tv_finish, elapsed;
  487. struct timeval tv_history_start, tv_history_finish;
  488. double Ti, Xi;
  489. int curr_hw_errors, i;
  490. bool was_hw_error;
  491. struct AVALON_HISTORY *history0, *history;
  492. int count;
  493. double Hs, W, fullnonce;
  494. int read_count;
  495. int64_t estimate_hashes;
  496. uint32_t values;
  497. int64_t hash_count_range;
  498. avalon = thr->cgpu;
  499. info = avalon_info[avalon->device_id];
  500. if (avalon->device_fd == -1)
  501. if (!avalon_prepare(thr)) {
  502. applog(LOG_ERR, "AVA%i: Comms error",
  503. avalon->device_id);
  504. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  505. // fail the device if the reopen attempt fails
  506. return -1;
  507. }
  508. fd = avalon->device_fd;
  509. #ifndef WIN32
  510. tcflush(fd, TCOFLUSH);
  511. #endif
  512. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  513. avalon_create_task(ob_bin, work[i]);
  514. ret = avalon_send_task(fd, ob_bin, sizeof(ob_bin));
  515. if (opt_debug) {
  516. ob_hex = bin2hex(ob_bin, sizeof(ob_bin));
  517. applog(LOG_DEBUG, "Avalon %d sent: %s",
  518. avalon->device_id, ob_hex);
  519. free(ob_hex);
  520. }
  521. if (ret) {
  522. do_avalon_close(thr);
  523. applog(LOG_ERR, "AVA%i: Comms error",
  524. avalon->device_id);
  525. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  526. return 0; /* This should never happen */
  527. }
  528. }
  529. elapsed.tv_sec = elapsed.tv_usec = 0;
  530. gettimeofday(&tv_start, NULL);
  531. /* FIXME: all read should be in another function
  532. Avalon return: reserved_nonce_midstate_data,
  533. count != AVALON_GET_WORK_COUNT */
  534. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  535. ret = avalon_read_work(nonce_bin, fd, &tv_finish, thr);
  536. if (ret == AVA_GETS_ERROR ) {
  537. do_avalon_close(thr);
  538. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  539. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  540. return 0;
  541. }
  542. work[0]->blk.nonce = 0xffffffff;
  543. }
  544. // aborted before becoming idle, get new work
  545. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  546. timersub(&tv_finish, &tv_start, &elapsed);
  547. // ONLY up to just when it aborted
  548. // We didn't read a reply so we don't subtract AVALON_READ_TIME
  549. estimate_hashes = ((double)(elapsed.tv_sec) +
  550. ((double)(elapsed.tv_usec)) /
  551. ((double)1000000)) / info->Hs;
  552. // If some Serial-USB delay allowed the full nonce range to
  553. // complete it can't have done more than a full nonce
  554. if (unlikely(estimate_hashes > 0xffffffff))
  555. estimate_hashes = 0xffffffff;
  556. if (opt_debug) {
  557. applog(LOG_DEBUG,
  558. "Avalon %d no nonce = 0x%08llx hashes "
  559. "(%ld.%06lds)",
  560. avalon->device_id, estimate_hashes,
  561. elapsed.tv_sec, elapsed.tv_usec);
  562. }
  563. return estimate_hashes;
  564. }
  565. memcpy((char *)&nonce, nonce_bin, sizeof(nonce_bin));
  566. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  567. nonce = swab32(nonce);
  568. #endif
  569. curr_hw_errors = avalon->hw_errors;
  570. submit_nonce(thr, work[0], nonce);
  571. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  572. // Force a USB close/reopen on any hw error
  573. if (was_hw_error)
  574. do_avalon_close(thr);
  575. hash_count = (nonce & info->nonce_mask);
  576. hash_count++;
  577. hash_count *= info->asic_count;
  578. if (opt_debug || info->do_avalon_timing)
  579. timersub(&tv_finish, &tv_start, &elapsed);
  580. if (opt_debug) {
  581. applog(LOG_DEBUG,
  582. "Avalon %d nonce = 0x%08x = 0x%08llx hashes "
  583. "(%ld.%06lds)",
  584. avalon->device_id, nonce, hash_count,
  585. elapsed.tv_sec, elapsed.tv_usec);
  586. }
  587. // ignore possible end condition values ... and hw errors
  588. if (info->do_avalon_timing
  589. && !was_hw_error
  590. && ((nonce & info->nonce_mask) > END_CONDITION)
  591. && ((nonce & info->nonce_mask) <
  592. (info->nonce_mask & ~END_CONDITION))) {
  593. gettimeofday(&tv_history_start, NULL);
  594. history0 = &(info->history[0]);
  595. if (history0->values == 0)
  596. timeradd(&tv_start, &history_sec, &(history0->finish));
  597. Ti = (double)(elapsed.tv_sec)
  598. + ((double)(elapsed.tv_usec))/((double)1000000)
  599. - ((double)AVALON_READ_TIME(info->baud));
  600. Xi = (double)hash_count;
  601. history0->sumXiTi += Xi * Ti;
  602. history0->sumXi += Xi;
  603. history0->sumTi += Ti;
  604. history0->sumXi2 += Xi * Xi;
  605. history0->values++;
  606. if (history0->hash_count_max < hash_count)
  607. history0->hash_count_max = hash_count;
  608. if (history0->hash_count_min > hash_count ||
  609. history0->hash_count_min == 0)
  610. history0->hash_count_min = hash_count;
  611. if (history0->values >= info->min_data_count
  612. && timercmp(&tv_start, &(history0->finish), >)) {
  613. for (i = INFO_HISTORY; i > 0; i--)
  614. memcpy(&(info->history[i]),
  615. &(info->history[i-1]),
  616. sizeof(struct AVALON_HISTORY));
  617. // Initialise history0 to zero for summary calculation
  618. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  619. // We just completed a history data set
  620. // So now recalc read_count based on the
  621. // whole history thus we will
  622. // initially get more accurate until it
  623. // completes INFO_HISTORY
  624. // total data sets
  625. count = 0;
  626. for (i = 1 ; i <= INFO_HISTORY; i++) {
  627. history = &(info->history[i]);
  628. if (history->values >= MIN_DATA_COUNT) {
  629. count++;
  630. history0->sumXiTi += history->sumXiTi;
  631. history0->sumXi += history->sumXi;
  632. history0->sumTi += history->sumTi;
  633. history0->sumXi2 += history->sumXi2;
  634. history0->values += history->values;
  635. if (history0->hash_count_max < history->hash_count_max)
  636. history0->hash_count_max = history->hash_count_max;
  637. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  638. history0->hash_count_min = history->hash_count_min;
  639. }
  640. }
  641. // All history data
  642. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  643. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  644. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  645. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  646. values = history0->values;
  647. // Initialise history0 to zero for next data set
  648. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  649. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  650. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  651. info->Hs = Hs;
  652. info->read_count = read_count;
  653. info->fullnonce = fullnonce;
  654. info->count = count;
  655. info->W = W;
  656. info->values = values;
  657. info->hash_count_range = hash_count_range;
  658. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  659. info->min_data_count *= 2;
  660. else if (info->timing_mode == MODE_SHORT)
  661. info->do_avalon_timing = false;
  662. // applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);
  663. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  664. avalon->device_id, Hs, W, read_count, fullnonce);
  665. }
  666. info->history_count++;
  667. gettimeofday(&tv_history_finish, NULL);
  668. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  669. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  670. }
  671. return hash_count;
  672. }
  673. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  674. {
  675. struct api_data *root = NULL;
  676. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  677. // Warning, access to these is not locked - but we don't really
  678. // care since hashing performance is way more important than
  679. // locking access to displaying API debug 'stats'
  680. // If locking becomes an issue for any of them, use copy_data=true also
  681. root = api_add_int(root, "read_count", &(info->read_count), false);
  682. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  683. root = api_add_int(root, "count", &(info->count), false);
  684. root = api_add_hs(root, "Hs", &(info->Hs), false);
  685. root = api_add_double(root, "W", &(info->W), false);
  686. root = api_add_uint(root, "total_values", &(info->values), false);
  687. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  688. root = api_add_uint64(root, "history_count", &(info->history_count),
  689. false);
  690. root = api_add_timeval(root, "history_time", &(info->history_time),
  691. false);
  692. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  693. false);
  694. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  695. false);
  696. root = api_add_const(root, "timing_mode",
  697. timing_mode_str(info->timing_mode), false);
  698. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  699. false);
  700. root = api_add_int(root, "baud", &(info->baud), false);
  701. root = api_add_int(root, "work_division", &(info->work_division),
  702. false);
  703. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  704. return root;
  705. }
  706. static void avalon_shutdown(struct thr_info *thr)
  707. {
  708. do_avalon_close(thr);
  709. }
  710. struct device_api avalon_api = {
  711. .dname = "avalon",
  712. .name = "AVA",
  713. .api_detect = avalon_detect,
  714. .get_api_stats = avalon_api_stats,
  715. .thread_prepare = avalon_prepare,
  716. .scanhash_queue = avalon_scanhash,
  717. .thread_shutdown = avalon_shutdown,
  718. };