driver-avalon.c 40 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #ifndef WIN32
  22. #include <sys/select.h>
  23. #include <termios.h>
  24. #include <sys/stat.h>
  25. #include <fcntl.h>
  26. #ifndef O_CLOEXEC
  27. #define O_CLOEXEC 0
  28. #endif
  29. #else
  30. #include "compat.h"
  31. #include <windows.h>
  32. #include <io.h>
  33. #endif
  34. #include "elist.h"
  35. #include "miner.h"
  36. #include "usbutils.h"
  37. #include "driver-avalon.h"
  38. #include "hexdump.c"
  39. #include "util.h"
  40. int opt_avalon_temp = AVALON_TEMP_TARGET;
  41. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  42. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  43. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  44. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  45. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  46. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  47. bool opt_avalon_auto;
  48. static int option_offset = -1;
  49. struct device_drv avalon_drv;
  50. static int avalon_init_task(struct avalon_task *at,
  51. uint8_t reset, uint8_t ff, uint8_t fan,
  52. uint8_t timeout, uint8_t asic_num,
  53. uint8_t miner_num, uint8_t nonce_elf,
  54. uint8_t gate_miner, int frequency)
  55. {
  56. uint16_t *lefreq16;
  57. uint8_t *buf;
  58. static bool first = true;
  59. if (unlikely(!at))
  60. return -1;
  61. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  62. return -1;
  63. memset(at, 0, sizeof(struct avalon_task));
  64. if (unlikely(reset)) {
  65. at->reset = 1;
  66. at->fan_eft = 1;
  67. at->timer_eft = 1;
  68. first = true;
  69. }
  70. at->flush_fifo = (ff ? 1 : 0);
  71. at->fan_eft = (fan ? 1 : 0);
  72. if (unlikely(first && !at->reset)) {
  73. at->fan_eft = 1;
  74. at->timer_eft = 1;
  75. first = false;
  76. }
  77. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  78. at->timeout_data = timeout;
  79. at->asic_num = asic_num;
  80. at->miner_num = miner_num;
  81. at->nonce_elf = nonce_elf;
  82. at->gate_miner_elf = 1;
  83. at->asic_pll = 1;
  84. if (unlikely(gate_miner)) {
  85. at-> gate_miner = 1;
  86. at->asic_pll = 0;
  87. }
  88. buf = (uint8_t *)at;
  89. buf[5] = 0x00;
  90. buf[8] = 0x74;
  91. buf[9] = 0x01;
  92. buf[10] = 0x00;
  93. buf[11] = 0x00;
  94. lefreq16 = (uint16_t *)&buf[6];
  95. *lefreq16 = htole16(frequency * 8);
  96. return 0;
  97. }
  98. static inline void avalon_create_task(struct avalon_task *at,
  99. struct work *work)
  100. {
  101. memcpy(at->midstate, work->midstate, 32);
  102. memcpy(at->data, work->data + 64, 12);
  103. }
  104. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  105. {
  106. int err, amount;
  107. err = usb_write(avalon, buf, len, &amount, ep);
  108. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  109. avalon->device_id, err);
  110. if (unlikely(err != 0)) {
  111. applog(LOG_WARNING, "usb_write error on avalon_write");
  112. return AVA_SEND_ERROR;
  113. }
  114. if (amount != len) {
  115. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  116. return AVA_SEND_ERROR;
  117. }
  118. return AVA_SEND_OK;
  119. }
  120. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  121. {
  122. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  123. int delay, ret, i, ep = C_AVALON_TASK;
  124. struct avalon_info *info;
  125. uint32_t nonce_range;
  126. size_t nr_len;
  127. if (at->nonce_elf)
  128. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  129. else
  130. nr_len = AVALON_WRITE_SIZE;
  131. memcpy(buf, at, AVALON_WRITE_SIZE);
  132. if (at->nonce_elf) {
  133. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  134. for (i = 0; i < at->asic_num; i++) {
  135. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  136. (i * nonce_range & 0xff000000) >> 24;
  137. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  138. (i * nonce_range & 0x00ff0000) >> 16;
  139. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  140. (i * nonce_range & 0x0000ff00) >> 8;
  141. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  142. (i * nonce_range & 0x000000ff) >> 0;
  143. }
  144. }
  145. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  146. uint8_t tt = 0;
  147. tt = (buf[0] & 0x0f) << 4;
  148. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  149. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  150. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  151. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  152. buf[0] = tt;
  153. tt = (buf[4] & 0x0f) << 4;
  154. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  155. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  156. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  157. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  158. buf[4] = tt;
  159. #endif
  160. info = avalon->device_data;
  161. delay = nr_len * 10 * 1000000;
  162. delay = delay / info->baud;
  163. if (at->reset) {
  164. ep = C_AVALON_RESET;
  165. nr_len = 1;
  166. }
  167. if (opt_debug) {
  168. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  169. hexdump(buf, nr_len);
  170. }
  171. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  172. delay += 4000;
  173. nusleep(delay);
  174. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  175. return ret;
  176. }
  177. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  178. struct avalon_info *info, struct avalon_result *ar,
  179. struct work *work)
  180. {
  181. uint32_t nonce;
  182. info = avalon->device_data;
  183. info->matching_work[work->subid]++;
  184. nonce = htole32(ar->nonce);
  185. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  186. return submit_nonce(thr, work, nonce);
  187. }
  188. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  189. static void wait_avalon_ready(struct cgpu_info *avalon)
  190. {
  191. while (avalon_buffer_full(avalon)) {
  192. nmsleep(40);
  193. }
  194. }
  195. #define AVALON_CTS (1 << 4)
  196. static inline bool avalon_cts(char c)
  197. {
  198. return (c & AVALON_CTS);
  199. }
  200. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  201. size_t bufsize, int timeout, int ep)
  202. {
  203. size_t total = 0, readsize = bufsize + 2;
  204. char readbuf[AVALON_READBUF_SIZE];
  205. int err, amount, ofs = 2, cp;
  206. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  207. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  208. avalon->drv->name, avalon->device_id, err);
  209. if (amount < 2)
  210. goto out;
  211. /* The first 2 of every 64 bytes are status on FTDIRL */
  212. while (amount > 2) {
  213. cp = amount - 2;
  214. if (cp > 62)
  215. cp = 62;
  216. memcpy(&buf[total], &readbuf[ofs], cp);
  217. total += cp;
  218. amount -= cp + 2;
  219. ofs += 64;
  220. }
  221. out:
  222. return total;
  223. }
  224. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  225. {
  226. struct avalon_result ar;
  227. int ret, i, spare;
  228. struct avalon_task at;
  229. uint8_t *buf, *tmp;
  230. struct timespec p;
  231. /* Send reset, then check for result */
  232. avalon_init_task(&at, 1, 0,
  233. AVALON_DEFAULT_FAN_MAX_PWM,
  234. AVALON_DEFAULT_TIMEOUT,
  235. AVALON_DEFAULT_ASIC_NUM,
  236. AVALON_DEFAULT_MINER_NUM,
  237. 0, 0,
  238. AVALON_DEFAULT_FREQUENCY);
  239. wait_avalon_ready(avalon);
  240. ret = avalon_send_task(&at, avalon);
  241. if (unlikely(ret == AVA_SEND_ERROR))
  242. return -1;
  243. if (!initial) {
  244. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  245. return 0;
  246. }
  247. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  248. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  249. /* What do these sleeps do?? */
  250. p.tv_sec = 0;
  251. p.tv_nsec = AVALON_RESET_PITCH;
  252. nanosleep(&p, NULL);
  253. /* Look for the first occurrence of 0xAA, the reset response should be:
  254. * AA 55 AA 55 00 00 00 00 00 00 */
  255. spare = ret - 10;
  256. buf = tmp = (uint8_t *)&ar;
  257. if (opt_debug) {
  258. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  259. hexdump(tmp, AVALON_READ_SIZE);
  260. }
  261. for (i = 0; i <= spare; i++) {
  262. buf = &tmp[i];
  263. if (buf[0] == 0xAA)
  264. break;
  265. }
  266. i = 0;
  267. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  268. buf[2] == 0xAA && buf[3] == 0x55) {
  269. for (i = 4; i < 11; i++)
  270. if (buf[i] != 0)
  271. break;
  272. }
  273. if (i != 11) {
  274. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  275. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  276. i, buf[0], buf[1], buf[2], buf[3]);
  277. /* FIXME: return 1; */
  278. } else
  279. applog(LOG_WARNING, "%s%d: Reset succeeded",
  280. avalon->drv->name, avalon->device_id);
  281. return 0;
  282. }
  283. static int avalon_calc_timeout(int frequency)
  284. {
  285. return AVALON_TIMEOUT_FACTOR / frequency;
  286. }
  287. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  288. int *asic_count, int *timeout, int *frequency)
  289. {
  290. char buf[BUFSIZ+1];
  291. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  292. bool timeout_default;
  293. size_t max;
  294. int i, tmp;
  295. if (opt_avalon_options == NULL)
  296. buf[0] = '\0';
  297. else {
  298. ptr = opt_avalon_options;
  299. for (i = 0; i < this_option_offset; i++) {
  300. comma = strchr(ptr, ',');
  301. if (comma == NULL)
  302. break;
  303. ptr = comma + 1;
  304. }
  305. comma = strchr(ptr, ',');
  306. if (comma == NULL)
  307. max = strlen(ptr);
  308. else
  309. max = comma - ptr;
  310. if (max > BUFSIZ)
  311. max = BUFSIZ;
  312. strncpy(buf, ptr, max);
  313. buf[max] = '\0';
  314. }
  315. if (!(*buf))
  316. return false;
  317. colon = strchr(buf, ':');
  318. if (colon)
  319. *(colon++) = '\0';
  320. tmp = atoi(buf);
  321. switch (tmp) {
  322. case 115200:
  323. *baud = 115200;
  324. break;
  325. case 57600:
  326. *baud = 57600;
  327. break;
  328. case 38400:
  329. *baud = 38400;
  330. break;
  331. case 19200:
  332. *baud = 19200;
  333. break;
  334. default:
  335. quit(1, "Invalid avalon-options for baud (%s) "
  336. "must be 115200, 57600, 38400 or 19200", buf);
  337. }
  338. if (colon && *colon) {
  339. colon2 = strchr(colon, ':');
  340. if (colon2)
  341. *(colon2++) = '\0';
  342. if (*colon) {
  343. tmp = atoi(colon);
  344. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  345. *miner_count = tmp;
  346. } else {
  347. quit(1, "Invalid avalon-options for "
  348. "miner_count (%s) must be 1 ~ %d",
  349. colon, AVALON_DEFAULT_MINER_NUM);
  350. }
  351. }
  352. if (colon2 && *colon2) {
  353. colon3 = strchr(colon2, ':');
  354. if (colon3)
  355. *(colon3++) = '\0';
  356. tmp = atoi(colon2);
  357. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  358. *asic_count = tmp;
  359. else {
  360. quit(1, "Invalid avalon-options for "
  361. "asic_count (%s) must be 1 ~ %d",
  362. colon2, AVALON_DEFAULT_ASIC_NUM);
  363. }
  364. timeout_default = false;
  365. if (colon3 && *colon3) {
  366. colon4 = strchr(colon3, ':');
  367. if (colon4)
  368. *(colon4++) = '\0';
  369. if (tolower(*colon3) == 'd')
  370. timeout_default = true;
  371. else {
  372. tmp = atoi(colon3);
  373. if (tmp > 0 && tmp <= 0xff)
  374. *timeout = tmp;
  375. else {
  376. quit(1, "Invalid avalon-options for "
  377. "timeout (%s) must be 1 ~ %d",
  378. colon3, 0xff);
  379. }
  380. }
  381. if (colon4 && *colon4) {
  382. tmp = atoi(colon4);
  383. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  384. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  385. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  386. }
  387. *frequency = tmp;
  388. if (timeout_default)
  389. *timeout = avalon_calc_timeout(*frequency);
  390. }
  391. }
  392. }
  393. }
  394. return true;
  395. }
  396. char *set_avalon_fan(char *arg)
  397. {
  398. int val1, val2, ret;
  399. ret = sscanf(arg, "%d-%d", &val1, &val2);
  400. if (ret < 1)
  401. return "No values passed to avalon-fan";
  402. if (ret == 1)
  403. val2 = val1;
  404. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  405. return "Invalid value passed to avalon-fan";
  406. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  407. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  408. return NULL;
  409. }
  410. char *set_avalon_freq(char *arg)
  411. {
  412. int val1, val2, ret;
  413. ret = sscanf(arg, "%d-%d", &val1, &val2);
  414. if (ret < 1)
  415. return "No values passed to avalon-freq";
  416. if (ret == 1)
  417. val2 = val1;
  418. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  419. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  420. val2 < val1)
  421. return "Invalid value passed to avalon-freq";
  422. opt_avalon_freq_min = val1;
  423. opt_avalon_freq_max = val2;
  424. return NULL;
  425. }
  426. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  427. {
  428. int i;
  429. wait_avalon_ready(avalon);
  430. /* Send idle to all miners */
  431. for (i = 0; i < info->miner_count; i++) {
  432. struct avalon_task at;
  433. if (unlikely(avalon_buffer_full(avalon)))
  434. break;
  435. info->idle++;
  436. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  437. info->asic_count, info->miner_count, 1, 1,
  438. info->frequency);
  439. avalon_send_task(&at, avalon);
  440. }
  441. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  442. wait_avalon_ready(avalon);
  443. }
  444. static void avalon_initialise(struct cgpu_info *avalon)
  445. {
  446. int err, interface;
  447. if (avalon->usbinfo.nodev)
  448. return;
  449. interface = avalon->usbdev->found->interface;
  450. // Reset
  451. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  452. FTDI_VALUE_RESET, interface, C_RESET);
  453. applog(LOG_DEBUG, "%s%i: reset got err %d",
  454. avalon->drv->name, avalon->device_id, err);
  455. if (avalon->usbinfo.nodev)
  456. return;
  457. // Set latency
  458. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  459. AVALON_LATENCY, interface, C_LATENCY);
  460. applog(LOG_DEBUG, "%s%i: latency got err %d",
  461. avalon->drv->name, avalon->device_id, err);
  462. if (avalon->usbinfo.nodev)
  463. return;
  464. // Set data
  465. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  466. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  467. applog(LOG_DEBUG, "%s%i: data got err %d",
  468. avalon->drv->name, avalon->device_id, err);
  469. if (avalon->usbinfo.nodev)
  470. return;
  471. // Set the baud
  472. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  473. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  474. C_SETBAUD);
  475. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  476. avalon->drv->name, avalon->device_id, err);
  477. if (avalon->usbinfo.nodev)
  478. return;
  479. // Set Modem Control
  480. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  481. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  482. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  483. avalon->drv->name, avalon->device_id, err);
  484. if (avalon->usbinfo.nodev)
  485. return;
  486. // Set Flow Control
  487. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  488. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  489. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  490. avalon->drv->name, avalon->device_id, err);
  491. if (avalon->usbinfo.nodev)
  492. return;
  493. /* Avalon repeats the following */
  494. // Set Modem Control
  495. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  496. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  497. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  498. avalon->drv->name, avalon->device_id, err);
  499. if (avalon->usbinfo.nodev)
  500. return;
  501. // Set Flow Control
  502. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  503. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  504. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  505. avalon->drv->name, avalon->device_id, err);
  506. }
  507. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  508. {
  509. uint8_t buf[2];
  510. int err;
  511. if (usb_ident(avalon) == IDENT_BTB) {
  512. buf[0] = (uint8_t)core_voltage;
  513. buf[1] = (uint8_t)(core_voltage >> 8);
  514. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  515. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  516. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  517. if (unlikely(err < 0)) {
  518. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  519. avalon->drv->name, avalon->device_id, err);
  520. return false;
  521. } else {
  522. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  523. avalon->drv->name, avalon->device_id,
  524. core_voltage);
  525. }
  526. return true;
  527. }
  528. return false;
  529. }
  530. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  531. {
  532. uint8_t buf[2];
  533. int err;
  534. int amount;
  535. if (usb_ident(avalon) == IDENT_BTB) {
  536. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  537. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  538. (char *)buf, sizeof(buf), &amount,
  539. C_BB_GET_VOLTAGE);
  540. if (unlikely(err != 0 || amount != 2)) {
  541. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  542. avalon->drv->name, avalon->device_id, err, amount);
  543. return 0;
  544. } else {
  545. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  546. }
  547. } else {
  548. return 0;
  549. }
  550. }
  551. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  552. {
  553. int baud, miner_count, asic_count, timeout, frequency;
  554. int this_option_offset = ++option_offset;
  555. struct avalon_info *info;
  556. struct cgpu_info *avalon;
  557. bool configured;
  558. int ret;
  559. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  560. baud = AVALON_IO_SPEED;
  561. miner_count = AVALON_DEFAULT_MINER_NUM;
  562. asic_count = AVALON_DEFAULT_ASIC_NUM;
  563. timeout = AVALON_DEFAULT_TIMEOUT;
  564. frequency = AVALON_DEFAULT_FREQUENCY;
  565. configured = get_options(this_option_offset, &baud, &miner_count,
  566. &asic_count, &timeout, &frequency);
  567. if (!usb_init(avalon, dev, found))
  568. goto shin;
  569. /* Even though this is an FTDI type chip, we want to do the parsing
  570. * all ourselves so set it to std usb type */
  571. avalon->usbdev->usb_type = USB_TYPE_STD;
  572. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  573. /* We have a real Avalon! */
  574. avalon_initialise(avalon);
  575. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  576. if (unlikely(!(avalon->device_data)))
  577. quit(1, "Failed to calloc avalon_info data");
  578. info = avalon->device_data;
  579. if (configured) {
  580. info->baud = baud;
  581. info->miner_count = miner_count;
  582. info->asic_count = asic_count;
  583. info->timeout = timeout;
  584. info->frequency = frequency;
  585. } else {
  586. info->baud = AVALON_IO_SPEED;
  587. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  588. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  589. info->timeout = AVALON_DEFAULT_TIMEOUT;
  590. info->frequency = AVALON_DEFAULT_FREQUENCY;
  591. }
  592. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  593. info->temp_max = 0;
  594. /* This is for check the temp/fan every 3~4s */
  595. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  596. if (info->temp_history_count <= 0)
  597. info->temp_history_count = 1;
  598. info->temp_history_index = 0;
  599. info->temp_sum = 0;
  600. info->temp_old = 0;
  601. if (!add_cgpu(avalon))
  602. goto unshin;
  603. ret = avalon_reset(avalon, true);
  604. if (ret && !configured)
  605. goto unshin;
  606. update_usb_stats(avalon);
  607. avalon_idle(avalon, info);
  608. applog(LOG_DEBUG, "Avalon Detected: %s "
  609. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  610. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  611. info->frequency);
  612. if (usb_ident(avalon) == IDENT_BTB) {
  613. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  614. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  615. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  616. opt_bitburner_core_voltage,
  617. BITBURNER_MIN_COREMV,
  618. BITBURNER_MAX_COREMV);
  619. } else
  620. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  621. }
  622. return true;
  623. unshin:
  624. usb_uninit(avalon);
  625. shin:
  626. free(avalon->device_data);
  627. avalon->device_data = NULL;
  628. avalon = usb_free_cgpu(avalon);
  629. return false;
  630. }
  631. static void avalon_detect(void)
  632. {
  633. usb_detect(&avalon_drv, avalon_detect_one);
  634. }
  635. static void avalon_init(struct cgpu_info *avalon)
  636. {
  637. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  638. }
  639. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  640. {
  641. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  642. (char *)ar->data, 64, 12);
  643. }
  644. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  645. struct avalon_result *ar);
  646. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  647. {
  648. applog(LOG_INFO, "%s%d: No matching work - HW error",
  649. thr->cgpu->drv->name, thr->cgpu->device_id);
  650. inc_hw_errors(thr);
  651. info->no_matching_work++;
  652. }
  653. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  654. struct thr_info *thr, char *buf, int *offset)
  655. {
  656. int i, spare = *offset - AVALON_READ_SIZE;
  657. bool found = false;
  658. for (i = 0; i <= spare; i++) {
  659. struct avalon_result *ar;
  660. struct work *work;
  661. ar = (struct avalon_result *)&buf[i];
  662. work = avalon_valid_result(avalon, ar);
  663. if (work) {
  664. bool gettemp = false;
  665. found = true;
  666. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  667. mutex_lock(&info->lock);
  668. if (!info->nonces++)
  669. gettemp = true;
  670. info->auto_nonces++;
  671. mutex_unlock(&info->lock);
  672. } else if (opt_avalon_auto) {
  673. mutex_lock(&info->lock);
  674. info->auto_hw++;
  675. mutex_unlock(&info->lock);
  676. }
  677. free_work(work);
  678. if (gettemp)
  679. avalon_update_temps(avalon, info, ar);
  680. break;
  681. }
  682. }
  683. if (!found) {
  684. spare = *offset - AVALON_READ_SIZE;
  685. /* We are buffering and haven't accumulated one more corrupt
  686. * work result. */
  687. if (spare < (int)AVALON_READ_SIZE)
  688. return;
  689. avalon_inc_nvw(info, thr);
  690. } else {
  691. spare = AVALON_READ_SIZE + i;
  692. if (i) {
  693. if (i >= (int)AVALON_READ_SIZE)
  694. avalon_inc_nvw(info, thr);
  695. else
  696. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  697. }
  698. }
  699. *offset -= spare;
  700. memmove(buf, buf + spare, *offset);
  701. }
  702. static void avalon_running_reset(struct cgpu_info *avalon,
  703. struct avalon_info *info)
  704. {
  705. avalon_reset(avalon, false);
  706. avalon_idle(avalon, info);
  707. avalon->results = 0;
  708. info->reset = false;
  709. }
  710. static void *avalon_get_results(void *userdata)
  711. {
  712. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  713. struct avalon_info *info = avalon->device_data;
  714. int offset = 0, read_delay = 0, ret = 0;
  715. const int rsize = AVALON_FTDI_READSIZE;
  716. char readbuf[AVALON_READBUF_SIZE];
  717. struct thr_info *thr = info->thr;
  718. struct timeval tv_start, tv_end;
  719. char threadname[24];
  720. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  721. RenameThread(threadname);
  722. while (likely(!avalon->shutdown)) {
  723. unsigned char buf[rsize];
  724. struct timeval tv_diff;
  725. int us_diff;
  726. if (offset >= (int)AVALON_READ_SIZE)
  727. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  728. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  729. /* This should never happen */
  730. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  731. offset = 0;
  732. }
  733. if (unlikely(info->reset)) {
  734. avalon_running_reset(avalon, info);
  735. /* Discard anything in the buffer */
  736. offset = 0;
  737. }
  738. /* As the usb read returns after just 1ms, sleep long enough
  739. * to leave the interface idle for writes to occur, but do not
  740. * sleep if we have been receiving data, and we do not yet have
  741. * a full result as more may be coming. */
  742. if (ret < 1 || offset == 0) {
  743. cgtime(&tv_end);
  744. timersub(&tv_end, &tv_start, &tv_diff);
  745. /* Assume it has not been > 1 second so ignore tv_sec */
  746. us_diff = tv_diff.tv_usec;
  747. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  748. if (likely(read_delay >= 1000))
  749. nusleep(read_delay);
  750. }
  751. cgtime(&tv_start);
  752. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  753. C_AVALON_READ);
  754. if (ret < 1)
  755. continue;
  756. if (opt_debug) {
  757. applog(LOG_DEBUG, "Avalon: get:");
  758. hexdump((uint8_t *)buf, ret);
  759. }
  760. memcpy(&readbuf[offset], &buf, ret);
  761. offset += ret;
  762. }
  763. return NULL;
  764. }
  765. static void avalon_rotate_array(struct cgpu_info *avalon)
  766. {
  767. avalon->queued = 0;
  768. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  769. avalon->work_array = 0;
  770. }
  771. static void bitburner_rotate_array(struct cgpu_info *avalon)
  772. {
  773. avalon->queued = 0;
  774. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  775. avalon->work_array = 0;
  776. }
  777. static void avalon_set_timeout(struct avalon_info *info)
  778. {
  779. info->timeout = avalon_calc_timeout(info->frequency);
  780. }
  781. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  782. {
  783. struct avalon_info *info = avalon->device_data;
  784. info->frequency = frequency;
  785. if (info->frequency > opt_avalon_freq_max)
  786. info->frequency = opt_avalon_freq_max;
  787. if (info->frequency < opt_avalon_freq_min)
  788. info->frequency = opt_avalon_freq_min;
  789. avalon_set_timeout(info);
  790. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  791. avalon->drv->name, avalon->device_id,
  792. info->frequency, info->timeout);
  793. }
  794. static void avalon_inc_freq(struct avalon_info *info)
  795. {
  796. info->frequency += 2;
  797. if (info->frequency > opt_avalon_freq_max)
  798. info->frequency = opt_avalon_freq_max;
  799. avalon_set_timeout(info);
  800. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  801. info->frequency, info->timeout);
  802. }
  803. static void avalon_dec_freq(struct avalon_info *info)
  804. {
  805. info->frequency -= 1;
  806. if (info->frequency < opt_avalon_freq_min)
  807. info->frequency = opt_avalon_freq_min;
  808. avalon_set_timeout(info);
  809. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  810. info->frequency, info->timeout);
  811. }
  812. static void avalon_reset_auto(struct avalon_info *info)
  813. {
  814. info->auto_queued =
  815. info->auto_nonces =
  816. info->auto_hw = 0;
  817. }
  818. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  819. {
  820. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  821. mutex_lock(&info->lock);
  822. if (!info->optimal) {
  823. if (info->fan_pwm >= opt_avalon_fan_max) {
  824. applog(LOG_WARNING,
  825. "%s%i: Above optimal temperature, throttling",
  826. avalon->drv->name, avalon->device_id);
  827. avalon_dec_freq(info);
  828. }
  829. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  830. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  831. int total = info->auto_nonces + info->auto_hw;
  832. /* Try to keep hw errors < 2% */
  833. if (info->auto_hw * 100 < total)
  834. avalon_inc_freq(info);
  835. else if (info->auto_hw * 66 > total)
  836. avalon_dec_freq(info);
  837. }
  838. avalon_reset_auto(info);
  839. mutex_unlock(&info->lock);
  840. }
  841. }
  842. static void *avalon_send_tasks(void *userdata)
  843. {
  844. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  845. struct avalon_info *info = avalon->device_data;
  846. const int avalon_get_work_count = info->miner_count;
  847. char threadname[24];
  848. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  849. RenameThread(threadname);
  850. while (likely(!avalon->shutdown)) {
  851. int start_count, end_count, i, j, ret;
  852. struct avalon_task at;
  853. bool idled = false;
  854. while (avalon_buffer_full(avalon))
  855. nmsleep(40);
  856. avalon_adjust_freq(info, avalon);
  857. mutex_lock(&info->qlock);
  858. start_count = avalon->work_array * avalon_get_work_count;
  859. end_count = start_count + avalon_get_work_count;
  860. for (i = start_count, j = 0; i < end_count; i++, j++) {
  861. if (avalon_buffer_full(avalon)) {
  862. applog(LOG_INFO,
  863. "%s%i: Buffer full after only %d of %d work queued",
  864. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  865. break;
  866. }
  867. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  868. avalon_init_task(&at, 0, 0, info->fan_pwm,
  869. info->timeout, info->asic_count,
  870. info->miner_count, 1, 0, info->frequency);
  871. avalon_create_task(&at, avalon->works[i]);
  872. info->auto_queued++;
  873. } else {
  874. int idle_freq = info->frequency;
  875. if (!info->idle++)
  876. idled = true;
  877. if (unlikely(info->overheat && opt_avalon_auto))
  878. idle_freq = AVALON_MIN_FREQUENCY;
  879. avalon_init_task(&at, 0, 0, info->fan_pwm,
  880. info->timeout, info->asic_count,
  881. info->miner_count, 1, 1, idle_freq);
  882. /* Reset the auto_queued count if we end up
  883. * idling any miners. */
  884. avalon_reset_auto(info);
  885. }
  886. ret = avalon_send_task(&at, avalon);
  887. if (unlikely(ret == AVA_SEND_ERROR)) {
  888. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  889. avalon->drv->name, avalon->device_id);
  890. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  891. info->reset = true;
  892. break;
  893. }
  894. }
  895. avalon_rotate_array(avalon);
  896. pthread_cond_signal(&info->qcond);
  897. mutex_unlock(&info->qlock);
  898. if (unlikely(idled)) {
  899. applog(LOG_WARNING, "%s%i: Idled %d miners",
  900. avalon->drv->name, avalon->device_id, idled);
  901. }
  902. }
  903. return NULL;
  904. }
  905. static void *bitburner_send_tasks(void *userdata)
  906. {
  907. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  908. struct avalon_info *info = avalon->device_data;
  909. const int avalon_get_work_count = info->miner_count;
  910. char threadname[24];
  911. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  912. RenameThread(threadname);
  913. while (likely(!avalon->shutdown)) {
  914. int start_count, end_count, i, j, ret;
  915. struct avalon_task at;
  916. bool idled = false;
  917. while (avalon_buffer_full(avalon))
  918. nmsleep(40);
  919. avalon_adjust_freq(info, avalon);
  920. /* Give other threads a chance to acquire qlock. */
  921. i = 0;
  922. do {
  923. nmsleep(40);
  924. } while (!avalon->shutdown && i++ < 15
  925. && avalon->queued < avalon_get_work_count);
  926. mutex_lock(&info->qlock);
  927. start_count = avalon->work_array * avalon_get_work_count;
  928. end_count = start_count + avalon_get_work_count;
  929. for (i = start_count, j = 0; i < end_count; i++, j++) {
  930. while (avalon_buffer_full(avalon))
  931. nmsleep(40);
  932. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  933. avalon_init_task(&at, 0, 0, info->fan_pwm,
  934. info->timeout, info->asic_count,
  935. info->miner_count, 1, 0, info->frequency);
  936. avalon_create_task(&at, avalon->works[i]);
  937. info->auto_queued++;
  938. } else {
  939. int idle_freq = info->frequency;
  940. if (!info->idle++)
  941. idled = true;
  942. if (unlikely(info->overheat && opt_avalon_auto))
  943. idle_freq = AVALON_MIN_FREQUENCY;
  944. avalon_init_task(&at, 0, 0, info->fan_pwm,
  945. info->timeout, info->asic_count,
  946. info->miner_count, 1, 1, idle_freq);
  947. /* Reset the auto_queued count if we end up
  948. * idling any miners. */
  949. avalon_reset_auto(info);
  950. }
  951. ret = avalon_send_task(&at, avalon);
  952. if (unlikely(ret == AVA_SEND_ERROR)) {
  953. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  954. avalon->drv->name, avalon->device_id);
  955. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  956. info->reset = true;
  957. break;
  958. }
  959. }
  960. bitburner_rotate_array(avalon);
  961. pthread_cond_signal(&info->qcond);
  962. mutex_unlock(&info->qlock);
  963. if (unlikely(idled)) {
  964. applog(LOG_WARNING, "%s%i: Idled %d miners",
  965. avalon->drv->name, avalon->device_id, idled);
  966. }
  967. }
  968. return NULL;
  969. }
  970. static bool avalon_prepare(struct thr_info *thr)
  971. {
  972. struct cgpu_info *avalon = thr->cgpu;
  973. struct avalon_info *info = avalon->device_data;
  974. int array_size = AVALON_ARRAY_SIZE;
  975. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  976. if (usb_ident(avalon) == IDENT_BTB) {
  977. array_size = BITBURNER_ARRAY_SIZE;
  978. write_thread_fn = bitburner_send_tasks;
  979. }
  980. free(avalon->works);
  981. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  982. array_size);
  983. if (!avalon->works)
  984. quit(1, "Failed to calloc avalon works in avalon_prepare");
  985. info->thr = thr;
  986. mutex_init(&info->lock);
  987. mutex_init(&info->qlock);
  988. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  989. quit(1, "Failed to pthread_cond_init avalon qcond");
  990. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  991. quit(1, "Failed to create avalon read_thr");
  992. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  993. quit(1, "Failed to create avalon write_thr");
  994. avalon_init(avalon);
  995. return true;
  996. }
  997. static void do_avalon_close(struct thr_info *thr)
  998. {
  999. struct cgpu_info *avalon = thr->cgpu;
  1000. struct avalon_info *info = avalon->device_data;
  1001. pthread_join(info->read_thr, NULL);
  1002. pthread_join(info->write_thr, NULL);
  1003. avalon_running_reset(avalon, info);
  1004. info->no_matching_work = 0;
  1005. }
  1006. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  1007. {
  1008. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1009. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1010. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1011. info->temp0 = ar->temp0;
  1012. info->temp1 = ar->temp1;
  1013. info->temp2 = ar->temp2;
  1014. if (ar->temp0 & 0x80) {
  1015. ar->temp0 &= 0x7f;
  1016. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1017. }
  1018. if (ar->temp1 & 0x80) {
  1019. ar->temp1 &= 0x7f;
  1020. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1021. }
  1022. if (ar->temp2 & 0x80) {
  1023. ar->temp2 &= 0x7f;
  1024. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1025. }
  1026. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  1027. if (info->temp0 > info->temp_max)
  1028. info->temp_max = info->temp0;
  1029. if (info->temp1 > info->temp_max)
  1030. info->temp_max = info->temp1;
  1031. if (info->temp2 > info->temp_max)
  1032. info->temp_max = info->temp2;
  1033. }
  1034. static void temp_rise(struct avalon_info *info, int temp)
  1035. {
  1036. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1037. info->fan_pwm = AVALON_PWM_MAX;
  1038. return;
  1039. }
  1040. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1041. info->fan_pwm += 10;
  1042. else if (temp > opt_avalon_temp)
  1043. info->fan_pwm += 5;
  1044. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1045. info->fan_pwm += 1;
  1046. else
  1047. return;
  1048. if (info->fan_pwm > opt_avalon_fan_max)
  1049. info->fan_pwm = opt_avalon_fan_max;
  1050. }
  1051. static void temp_drop(struct avalon_info *info, int temp)
  1052. {
  1053. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1054. info->fan_pwm = opt_avalon_fan_min;
  1055. return;
  1056. }
  1057. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1058. info->fan_pwm -= 10;
  1059. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1060. info->fan_pwm -= 5;
  1061. else if (temp < opt_avalon_temp)
  1062. info->fan_pwm -= 1;
  1063. if (info->fan_pwm < opt_avalon_fan_min)
  1064. info->fan_pwm = opt_avalon_fan_min;
  1065. }
  1066. static inline void adjust_fan(struct avalon_info *info)
  1067. {
  1068. int temp_new;
  1069. temp_new = info->temp_sum / info->temp_history_count;
  1070. if (temp_new > info->temp_old)
  1071. temp_rise(info, temp_new);
  1072. else if (temp_new < info->temp_old)
  1073. temp_drop(info, temp_new);
  1074. else {
  1075. /* temp_new == info->temp_old */
  1076. if (temp_new > opt_avalon_temp)
  1077. temp_rise(info, temp_new);
  1078. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1079. temp_drop(info, temp_new);
  1080. }
  1081. info->temp_old = temp_new;
  1082. if (info->temp_old <= opt_avalon_temp)
  1083. info->optimal = true;
  1084. else
  1085. info->optimal = false;
  1086. }
  1087. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1088. struct avalon_result *ar)
  1089. {
  1090. record_temp_fan(info, ar, &(avalon->temp));
  1091. applog(LOG_INFO,
  1092. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1093. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1094. info->fan0, info->fan1, info->fan2,
  1095. info->temp0, info->temp1, info->temp2, info->temp_max);
  1096. info->temp_history_index++;
  1097. info->temp_sum += avalon->temp;
  1098. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1099. info->temp_history_index, info->temp_history_count, info->temp_old);
  1100. if (usb_ident(avalon) == IDENT_BTB) {
  1101. info->core_voltage = bitburner_get_core_voltage(avalon);
  1102. }
  1103. if (info->temp_history_index == info->temp_history_count) {
  1104. adjust_fan(info);
  1105. info->temp_history_index = 0;
  1106. info->temp_sum = 0;
  1107. }
  1108. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1109. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1110. info->overheat = true;
  1111. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1112. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1113. info->overheat = false;
  1114. }
  1115. }
  1116. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1117. {
  1118. struct avalon_info *info = avalon->device_data;
  1119. int lowfan = 10000;
  1120. if (usb_ident(avalon) == IDENT_BTB) {
  1121. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1122. } else {
  1123. /* Find the lowest fan speed of the ASIC cooling fans. */
  1124. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1125. lowfan = info->fan1;
  1126. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1127. lowfan = info->fan2;
  1128. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1129. }
  1130. }
  1131. /* We use a replacement algorithm to only remove references to work done from
  1132. * the buffer when we need the extra space for new work. */
  1133. static bool avalon_fill(struct cgpu_info *avalon)
  1134. {
  1135. struct avalon_info *info = avalon->device_data;
  1136. int subid, slot, mc;
  1137. struct work *work;
  1138. bool ret = true;
  1139. mc = info->miner_count;
  1140. mutex_lock(&info->qlock);
  1141. if (avalon->queued >= mc)
  1142. goto out_unlock;
  1143. work = get_queued(avalon);
  1144. if (unlikely(!work)) {
  1145. ret = false;
  1146. goto out_unlock;
  1147. }
  1148. subid = avalon->queued++;
  1149. work->subid = subid;
  1150. slot = avalon->work_array * mc + subid;
  1151. if (likely(avalon->works[slot]))
  1152. work_completed(avalon, avalon->works[slot]);
  1153. avalon->works[slot] = work;
  1154. if (avalon->queued < mc)
  1155. ret = false;
  1156. out_unlock:
  1157. mutex_unlock(&info->qlock);
  1158. return ret;
  1159. }
  1160. static int64_t avalon_scanhash(struct thr_info *thr)
  1161. {
  1162. struct cgpu_info *avalon = thr->cgpu;
  1163. struct avalon_info *info = avalon->device_data;
  1164. const int miner_count = info->miner_count;
  1165. struct timeval now, then, tdiff;
  1166. int64_t hash_count, us_timeout;
  1167. struct timespec abstime;
  1168. /* Half nonce range */
  1169. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1170. tdiff.tv_sec = us_timeout / 1000000;
  1171. tdiff.tv_usec = us_timeout - (tdiff.tv_sec * 1000000);
  1172. cgtime(&now);
  1173. timeradd(&now, &tdiff, &then);
  1174. abstime.tv_sec = then.tv_sec;
  1175. abstime.tv_nsec = then.tv_usec * 1000;
  1176. /* Wait until avalon_send_tasks signals us that it has completed
  1177. * sending its work or a full nonce range timeout has occurred */
  1178. mutex_lock(&info->qlock);
  1179. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1180. mutex_unlock(&info->qlock);
  1181. mutex_lock(&info->lock);
  1182. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1183. avalon->results += info->nonces + info->idle;
  1184. if (avalon->results > miner_count)
  1185. avalon->results = miner_count;
  1186. if (!info->reset)
  1187. avalon->results--;
  1188. info->nonces = info->idle = 0;
  1189. mutex_unlock(&info->lock);
  1190. /* Check for nothing but consecutive bad results or consistently less
  1191. * results than we should be getting and reset the FPGA if necessary */
  1192. if (usb_ident(avalon) != IDENT_BTB) {
  1193. if (avalon->results < -miner_count && !info->reset) {
  1194. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1195. avalon->drv->name, avalon->device_id);
  1196. info->reset = true;
  1197. }
  1198. }
  1199. if (unlikely(avalon->usbinfo.nodev)) {
  1200. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1201. avalon->drv->name, avalon->device_id);
  1202. avalon->shutdown = true;
  1203. }
  1204. /* This hashmeter is just a utility counter based on returned shares */
  1205. return hash_count;
  1206. }
  1207. static void avalon_flush_work(struct cgpu_info *avalon)
  1208. {
  1209. struct avalon_info *info = avalon->device_data;
  1210. mutex_lock(&info->qlock);
  1211. /* Will overwrite any work queued */
  1212. avalon->queued = 0;
  1213. pthread_cond_signal(&info->qcond);
  1214. mutex_unlock(&info->qlock);
  1215. }
  1216. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1217. {
  1218. struct api_data *root = NULL;
  1219. struct avalon_info *info = cgpu->device_data;
  1220. int i;
  1221. root = api_add_int(root, "baud", &(info->baud), false);
  1222. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1223. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1224. root = api_add_int(root, "timeout", &(info->timeout), false);
  1225. root = api_add_int(root, "frequency", &(info->frequency), false);
  1226. root = api_add_int(root, "fan1", &(info->fan0), false);
  1227. root = api_add_int(root, "fan2", &(info->fan1), false);
  1228. root = api_add_int(root, "fan3", &(info->fan2), false);
  1229. root = api_add_int(root, "temp1", &(info->temp0), false);
  1230. root = api_add_int(root, "temp2", &(info->temp1), false);
  1231. root = api_add_int(root, "temp3", &(info->temp2), false);
  1232. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1233. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1234. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1235. for (i = 0; i < info->miner_count; i++) {
  1236. char mcw[24];
  1237. sprintf(mcw, "match_work_count%d", i + 1);
  1238. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1239. }
  1240. return root;
  1241. }
  1242. static void avalon_shutdown(struct thr_info *thr)
  1243. {
  1244. do_avalon_close(thr);
  1245. }
  1246. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1247. {
  1248. int val;
  1249. if (strcasecmp(option, "help") == 0) {
  1250. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1251. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1252. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1253. return replybuf;
  1254. }
  1255. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1256. if (usb_ident(avalon) != IDENT_BTB) {
  1257. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1258. return replybuf;
  1259. }
  1260. if (!setting || !*setting) {
  1261. sprintf(replybuf, "missing millivolts setting");
  1262. return replybuf;
  1263. }
  1264. val = atoi(setting);
  1265. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1266. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1267. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1268. return replybuf;
  1269. }
  1270. if (bitburner_set_core_voltage(avalon, val))
  1271. return NULL;
  1272. else {
  1273. sprintf(replybuf, "Set millivolts failed");
  1274. return replybuf;
  1275. }
  1276. }
  1277. if (strcasecmp(option, "freq") == 0) {
  1278. if (!setting || !*setting) {
  1279. sprintf(replybuf, "missing freq setting");
  1280. return replybuf;
  1281. }
  1282. val = atoi(setting);
  1283. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1284. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1285. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1286. return replybuf;
  1287. }
  1288. avalon_set_freq(avalon, val);
  1289. return NULL;
  1290. }
  1291. sprintf(replybuf, "Unknown option: %s", option);
  1292. return replybuf;
  1293. }
  1294. struct device_drv avalon_drv = {
  1295. .drv_id = DRIVER_AVALON,
  1296. .dname = "avalon",
  1297. .name = "AVA",
  1298. .drv_detect = avalon_detect,
  1299. .thread_prepare = avalon_prepare,
  1300. .hash_work = hash_queued_work,
  1301. .queue_full = avalon_fill,
  1302. .scanwork = avalon_scanhash,
  1303. .flush_work = avalon_flush_work,
  1304. .get_api_stats = avalon_api_stats,
  1305. .get_statline_before = get_avalon_statline_before,
  1306. .set_device = avalon_set_device,
  1307. .reinit_device = avalon_init,
  1308. .thread_shutdown = avalon_shutdown,
  1309. };