driver-avalon.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937
  1. /*
  2. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Luke Dashjr
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static int option_offset = -1;
  36. struct avalon_info **avalon_info;
  37. struct device_api avalon_api;
  38. static inline uint8_t rev8(uint8_t d)
  39. {
  40. int i;
  41. uint8_t out = 0;
  42. /* (from left to right) */
  43. for (i = 0; i < 8; i++)
  44. if (d & (1 << i))
  45. out |= (1 << (7 - i));
  46. return out;
  47. }
  48. static int avalon_init_task(struct avalon_task *at,
  49. uint8_t reset, uint8_t ff, uint8_t fan,
  50. uint8_t timeout, uint8_t asic_num,
  51. uint8_t miner_num, uint8_t nonce_elf)
  52. {
  53. static bool first = true;
  54. if (unlikely(!at))
  55. return -1;
  56. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  57. return -1;
  58. memset(at, 0, sizeof(struct avalon_task));
  59. if (unlikely(reset)) {
  60. at->reset = 1;
  61. at->fan_eft = 1;
  62. at->timer_eft = 1;
  63. first = true;
  64. }
  65. at->flush_fifo = (ff ? 1 : 0);
  66. at->fan_eft = (fan ? 1 : 0);
  67. if (unlikely(first && !at->reset)) {
  68. at->fan_eft = 1;
  69. at->timer_eft = 1;
  70. first = false;
  71. }
  72. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  73. at->timeout_data = timeout;
  74. at->asic_num = asic_num;
  75. at->miner_num = miner_num;
  76. at->nonce_elf = nonce_elf;
  77. return 0;
  78. }
  79. static inline void avalon_create_task(struct avalon_task *at,
  80. struct work *work)
  81. {
  82. memcpy(at->midstate, work->midstate, 32);
  83. memcpy(at->data, work->data + 64, 12);
  84. }
  85. static int avalon_send_task(int fd, const struct avalon_task *at,
  86. struct thr_info *thr)
  87. {
  88. size_t ret;
  89. int full;
  90. struct timespec p;
  91. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  92. size_t nr_len;
  93. struct cgpu_info *avalon;
  94. struct avalon_info *info;
  95. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  96. uint32_t nonce_range;
  97. int i;
  98. if (at->nonce_elf)
  99. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  100. else
  101. nr_len = AVALON_WRITE_SIZE;
  102. memcpy(buf, at, AVALON_WRITE_SIZE);
  103. if (at->nonce_elf) {
  104. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  105. for (i = 0; i < at->asic_num; i++) {
  106. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  107. (i * nonce_range & 0xff000000) >> 24;
  108. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  109. (i * nonce_range & 0x00ff0000) >> 16;
  110. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  111. (i * nonce_range & 0x0000ff00) >> 8;
  112. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  113. (i * nonce_range & 0x000000ff) >> 0;
  114. }
  115. }
  116. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  117. uint8_t tt = 0;
  118. tt = (buf[0] & 0x0f) << 4;
  119. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  120. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  121. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  122. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  123. buf[0] = tt;
  124. buf[4] = rev8(buf[4]);
  125. #endif
  126. if (likely(thr)) {
  127. avalon = thr->cgpu;
  128. info = avalon_info[avalon->device_id];
  129. delay = nr_len * 10 * 1000000000ULL;
  130. delay = delay / info->baud;
  131. if (info->frequency == 256) {
  132. buf[4] = 0x07;
  133. buf[5] = 0x00;
  134. buf[6] = 0x03;
  135. buf[7] = 0x08;
  136. buf[8] = 0x74;
  137. buf[9] = 0x01;
  138. buf[10] = 0x00;
  139. buf[11] = 0x00;
  140. } else if (info->frequency == 270) {
  141. buf[4] = 0x07;
  142. buf[5] = 0x00;
  143. buf[6] = 0x73;
  144. buf[7] = 0x08;
  145. buf[8] = 0x74;
  146. buf[9] = 0x01;
  147. buf[10] = 0x00;
  148. buf[11] = 0x00;
  149. } else if (info->frequency == 282) {
  150. buf[4] = 0x07;
  151. buf[5] = 0x00;
  152. buf[6] = 0xd3;
  153. buf[7] = 0x08;
  154. buf[8] = 0x74;
  155. buf[9] = 0x01;
  156. buf[10] = 0x00;
  157. buf[11] = 0x00;
  158. } else if (info->frequency == 300) {
  159. buf[4] = 0x07;
  160. buf[5] = 0x00;
  161. buf[6] = 0x63;
  162. buf[7] = 0x09;
  163. buf[8] = 0x74;
  164. buf[9] = 0x01;
  165. buf[10] = 0x00;
  166. buf[11] = 0x00;
  167. }
  168. }
  169. if (at->reset)
  170. nr_len = 1;
  171. if (opt_debug) {
  172. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  173. hexdump((uint8_t *)buf, nr_len);
  174. }
  175. ret = write(fd, buf, nr_len);
  176. if (unlikely(ret != nr_len))
  177. return AVA_SEND_ERROR;
  178. p.tv_sec = 0;
  179. p.tv_nsec = (long)delay + 4000000;
  180. nanosleep(&p, NULL);
  181. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  182. full = avalon_buffer_full(fd);
  183. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  184. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  185. if (unlikely(full == AVA_BUFFER_FULL))
  186. return AVA_SEND_BUFFER_FULL;
  187. return AVA_SEND_BUFFER_EMPTY;
  188. }
  189. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  190. struct thr_info *thr, struct timeval *tv_finish)
  191. {
  192. ssize_t ret = 0;
  193. int rc = 0;
  194. int read_amount = AVALON_READ_SIZE;
  195. bool first = true;
  196. /* Read reply 1 byte at a time to get earliest tv_finish */
  197. while (true) {
  198. ret = read(fd, buf, 1);
  199. if (ret < 0)
  200. return AVA_GETS_ERROR;
  201. if (first && tv_finish != NULL)
  202. gettimeofday(tv_finish, NULL);
  203. if (ret >= read_amount)
  204. return AVA_GETS_OK;
  205. if (ret > 0) {
  206. buf += ret;
  207. read_amount -= ret;
  208. first = false;
  209. continue;
  210. }
  211. rc++;
  212. if (rc >= read_count) {
  213. if (opt_debug) {
  214. applog(LOG_WARNING,
  215. "Avalon: No data in %.2f seconds",
  216. (float)rc/(float)AVALON_TIME_FACTOR);
  217. }
  218. return AVA_GETS_TIMEOUT;
  219. }
  220. if (thr && thr->work_restart) {
  221. if (opt_debug) {
  222. applog(LOG_WARNING,
  223. "Avalon: Work restart at %.2f seconds",
  224. (float)(rc)/(float)AVALON_TIME_FACTOR);
  225. }
  226. return AVA_GETS_RESTART;
  227. }
  228. }
  229. }
  230. static int avalon_get_result(int fd, struct avalon_result *ar,
  231. struct thr_info *thr, struct timeval *tv_finish)
  232. {
  233. struct cgpu_info *avalon;
  234. struct avalon_info *info;
  235. uint8_t result[AVALON_READ_SIZE];
  236. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  237. if (likely(thr)) {
  238. avalon = thr->cgpu;
  239. info = avalon_info[avalon->device_id];
  240. read_count = info->read_count;
  241. }
  242. memset(result, 0, AVALON_READ_SIZE);
  243. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  244. if (ret == AVA_GETS_OK) {
  245. if (opt_debug) {
  246. applog(LOG_DEBUG, "Avalon: get:");
  247. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  248. }
  249. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  250. }
  251. return ret;
  252. }
  253. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  254. struct avalon_result *ar, uint32_t *nonce)
  255. {
  256. struct cgpu_info *avalon;
  257. struct avalon_info *info;
  258. int avalon_get_work_count, i;
  259. if (unlikely(!work))
  260. return -1;
  261. avalon = thr->cgpu;
  262. info = avalon_info[avalon->device_id];
  263. avalon_get_work_count = info->miner_count;
  264. for (i = 0; i < avalon_get_work_count; i++) {
  265. if (work[i] &&
  266. !memcmp(ar->data, work[i]->data + 64, 12) &&
  267. !memcmp(ar->midstate, work[i]->midstate, 32))
  268. break;
  269. }
  270. if (i == avalon_get_work_count)
  271. return -1;
  272. ++info->matching_work[i];
  273. *nonce = ar->nonce;
  274. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  275. *nonce = swab32(*nonce);
  276. #endif
  277. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  278. info->matching_work[i]);
  279. return i;
  280. }
  281. static int avalon_reset(int fd, struct avalon_result *ar)
  282. {
  283. struct avalon_task at;
  284. uint8_t *buf;
  285. int ret, i = 0;
  286. struct timespec p;
  287. avalon_init_task(&at, 1, 0,
  288. AVALON_DEFAULT_FAN_MAX_PWM,
  289. AVALON_DEFAULT_TIMEOUT,
  290. AVALON_DEFAULT_ASIC_NUM,
  291. AVALON_DEFAULT_MINER_NUM,
  292. 0);
  293. ret = avalon_send_task(fd, &at, NULL);
  294. if (ret == AVA_SEND_ERROR)
  295. return 1;
  296. avalon_get_result(fd, ar, NULL, NULL);
  297. buf = (uint8_t *)ar;
  298. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  299. buf[2] == 0xAA && buf[3] == 0x55) {
  300. for (i = 4; i < 11; i++)
  301. if (buf[i] != 0)
  302. break;
  303. }
  304. if (i != 11) {
  305. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  306. " (%d: %02x %02x %02x %02x)",
  307. i, buf[0], buf[1], buf[2], buf[3]);
  308. /* FIXME: return 1; */
  309. }
  310. p.tv_sec = 0;
  311. p.tv_nsec = AVALON_RESET_PITCH;
  312. nanosleep(&p, NULL);
  313. applog(LOG_WARNING, "Avalon: Reset succeeded");
  314. return 0;
  315. }
  316. static void get_options(int this_option_offset, int *baud, int *miner_count,
  317. int *asic_count, int *timeout, int *frequency)
  318. {
  319. char err_buf[BUFSIZ+1];
  320. char buf[BUFSIZ+1];
  321. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  322. size_t max;
  323. int i, tmp;
  324. if (opt_avalon_options == NULL)
  325. buf[0] = '\0';
  326. else {
  327. ptr = opt_avalon_options;
  328. for (i = 0; i < this_option_offset; i++) {
  329. comma = strchr(ptr, ',');
  330. if (comma == NULL)
  331. break;
  332. ptr = comma + 1;
  333. }
  334. comma = strchr(ptr, ',');
  335. if (comma == NULL)
  336. max = strlen(ptr);
  337. else
  338. max = comma - ptr;
  339. if (max > BUFSIZ)
  340. max = BUFSIZ;
  341. strncpy(buf, ptr, max);
  342. buf[max] = '\0';
  343. }
  344. *baud = AVALON_IO_SPEED;
  345. *miner_count = AVALON_DEFAULT_MINER_NUM;
  346. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  347. *timeout = AVALON_DEFAULT_TIMEOUT;
  348. if (!(*buf))
  349. return;
  350. colon = strchr(buf, ':');
  351. if (colon)
  352. *(colon++) = '\0';
  353. tmp = atoi(buf);
  354. switch (tmp) {
  355. case 115200:
  356. *baud = 115200;
  357. break;
  358. case 57600:
  359. *baud = 57600;
  360. break;
  361. case 38400:
  362. *baud = 38400;
  363. break;
  364. case 19200:
  365. *baud = 19200;
  366. break;
  367. default:
  368. sprintf(err_buf,
  369. "Invalid avalon-options for baud (%s) "
  370. "must be 115200, 57600, 38400 or 19200", buf);
  371. quit(1, err_buf);
  372. }
  373. if (colon && *colon) {
  374. colon2 = strchr(colon, ':');
  375. if (colon2)
  376. *(colon2++) = '\0';
  377. if (*colon) {
  378. tmp = atoi(colon);
  379. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  380. *miner_count = tmp;
  381. } else {
  382. sprintf(err_buf,
  383. "Invalid avalon-options for "
  384. "miner_count (%s) must be 1 ~ %d",
  385. colon, AVALON_DEFAULT_MINER_NUM);
  386. quit(1, err_buf);
  387. }
  388. }
  389. if (colon2 && *colon2) {
  390. colon3 = strchr(colon2, ':');
  391. if (colon3)
  392. *(colon3++) = '\0';
  393. tmp = atoi(colon2);
  394. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  395. *asic_count = tmp;
  396. else {
  397. sprintf(err_buf,
  398. "Invalid avalon-options for "
  399. "asic_count (%s) must be 1 ~ %d",
  400. colon2, AVALON_DEFAULT_ASIC_NUM);
  401. quit(1, err_buf);
  402. }
  403. if (colon3 && *colon3) {
  404. colon4 = strchr(colon3, ':');
  405. if (colon4)
  406. *(colon4++) = '\0';
  407. tmp = atoi(colon3);
  408. if (tmp > 0 && tmp <= 0xff)
  409. *timeout = tmp;
  410. else {
  411. sprintf(err_buf,
  412. "Invalid avalon-options for "
  413. "timeout (%s) must be 1 ~ %d",
  414. colon3, 0xff);
  415. quit(1, err_buf);
  416. }
  417. if (colon4 && *colon4) {
  418. tmp = atoi(colon4);
  419. switch (tmp) {
  420. case 256:
  421. case 270:
  422. case 282:
  423. case 300:
  424. *frequency = tmp;
  425. break;
  426. default:
  427. sprintf(err_buf,
  428. "Invalid avalon-options for "
  429. "frequency must be 256/270/282/300");
  430. quit(1, err_buf);
  431. }
  432. }
  433. }
  434. }
  435. }
  436. }
  437. static bool avalon_detect_one(const char *devpath)
  438. {
  439. struct avalon_info *info;
  440. struct avalon_result ar;
  441. int fd, ret;
  442. int baud, miner_count, asic_count, timeout, frequency = 0;
  443. int this_option_offset = ++option_offset;
  444. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  445. &timeout, &frequency);
  446. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  447. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  448. devpath, baud, miner_count, asic_count, timeout, frequency);
  449. fd = avalon_open2(devpath, baud, true);
  450. if (unlikely(fd == -1)) {
  451. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  452. return false;
  453. }
  454. ret = avalon_reset(fd, &ar);
  455. avalon_close(fd);
  456. if (ret) {
  457. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  458. }
  459. /* We have a real Avalon! */
  460. struct cgpu_info *avalon;
  461. avalon = calloc(1, sizeof(struct cgpu_info));
  462. avalon->api = &avalon_api;
  463. avalon->device_path = strdup(devpath);
  464. avalon->device_fd = -1;
  465. avalon->threads = AVALON_MINER_THREADS;
  466. add_cgpu(avalon);
  467. avalon_info = realloc(avalon_info,
  468. sizeof(struct avalon_info *) *
  469. (total_devices + 1));
  470. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  471. devpath, avalon->device_id);
  472. avalon_info[avalon->device_id] = (struct avalon_info *)
  473. malloc(sizeof(struct avalon_info));
  474. if (unlikely(!(avalon_info[avalon->device_id])))
  475. quit(1, "Failed to malloc avalon_info");
  476. info = avalon_info[avalon->device_id];
  477. memset(info, 0, sizeof(struct avalon_info));
  478. info->baud = baud;
  479. info->miner_count = miner_count;
  480. info->asic_count = asic_count;
  481. info->timeout = timeout;
  482. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  483. AVALON_TIME_FACTOR) / (float)info->miner_count;
  484. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  485. info->temp_max = 0;
  486. info->temp_history_count = (4 / (float)(0x3c * ((float)1.67/0x32))) + 1;
  487. if (info->temp_history_count <= 0)
  488. info->temp_history_count = 1;
  489. info->temp_history_index = 0;
  490. info->temp_sum = 0;
  491. info->temp_old = 0;
  492. info->frequency = frequency;
  493. return true;
  494. }
  495. static inline void avalon_detect()
  496. {
  497. serial_detect(&avalon_api, avalon_detect_one);
  498. }
  499. static bool avalon_prepare(struct thr_info *thr)
  500. {
  501. struct avalon_result ar;
  502. struct cgpu_info *avalon = thr->cgpu;
  503. struct timeval now;
  504. int fd, ret;
  505. avalon->device_fd = -1;
  506. fd = avalon_open(avalon->device_path,
  507. avalon_info[avalon->device_id]->baud);
  508. if (unlikely(fd == -1)) {
  509. applog(LOG_ERR, "Avalon: Failed to open on %s",
  510. avalon->device_path);
  511. return false;
  512. }
  513. ret = avalon_reset(fd, &ar);
  514. if (ret)
  515. return false;
  516. avalon->device_fd = fd;
  517. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  518. gettimeofday(&now, NULL);
  519. get_datestamp(avalon->init, &now);
  520. return true;
  521. }
  522. static void avalon_free_work(struct thr_info *thr, struct work **work)
  523. {
  524. struct cgpu_info *avalon;
  525. struct avalon_info *info;
  526. int i;
  527. if (unlikely(!work))
  528. return;
  529. avalon = thr->cgpu;
  530. info = avalon_info[avalon->device_id];
  531. for (i = 0; i < info->miner_count; i++)
  532. if (likely(work[i])) {
  533. free_work(work[i]);
  534. work[i] = NULL;
  535. }
  536. }
  537. static void do_avalon_close(struct thr_info *thr)
  538. {
  539. struct cgpu_info *avalon = thr->cgpu;
  540. struct avalon_info *info = avalon_info[avalon->device_id];
  541. avalon_close(avalon->device_fd);
  542. avalon->device_fd = -1;
  543. info->no_matching_work = 0;
  544. avalon_free_work(thr, info->bulk0);
  545. avalon_free_work(thr, info->bulk1);
  546. avalon_free_work(thr, info->bulk2);
  547. avalon_free_work(thr, info->bulk3);
  548. }
  549. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  550. {
  551. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  552. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  553. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  554. info->temp0 = ar->temp0;
  555. info->temp1 = ar->temp1;
  556. info->temp2 = ar->temp2;
  557. if (ar->temp0 & 0x80) {
  558. ar->temp0 &= 0x7f;
  559. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  560. }
  561. if (ar->temp1 & 0x80) {
  562. ar->temp1 &= 0x7f;
  563. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  564. }
  565. if (ar->temp2 & 0x80) {
  566. ar->temp2 &= 0x7f;
  567. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  568. }
  569. if (info->temp0 > info->temp_max)
  570. info->temp_max = info->temp0;
  571. if (info->temp1 > info->temp_max)
  572. info->temp_max = info->temp1;
  573. if (info->temp2 > info->temp_max)
  574. info->temp_max = info->temp2;
  575. *temp_avg = info->temp2;
  576. }
  577. static inline void adjust_fan(struct avalon_info *info)
  578. {
  579. int temp_new;
  580. temp_new = info->temp_sum / info->temp_history_count;
  581. if (temp_new < 35) {
  582. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  583. info->temp_old = temp_new;
  584. } else if (temp_new > 55) {
  585. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  586. info->temp_old = temp_new;
  587. } else if (abs(temp_new - info->temp_old) >= 2) {
  588. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  589. info->temp_old = temp_new;
  590. }
  591. }
  592. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  593. __maybe_unused int64_t max_nonce)
  594. {
  595. struct cgpu_info *avalon;
  596. int fd, ret, full;
  597. struct avalon_info *info;
  598. struct avalon_task at;
  599. struct avalon_result ar;
  600. int i, work_i0, work_i1, work_i2, work_i3;
  601. int avalon_get_work_count;
  602. struct timeval tv_start, tv_finish, elapsed;
  603. uint32_t nonce;
  604. int64_t hash_count;
  605. static int first_try = 0;
  606. avalon = thr->cgpu;
  607. info = avalon_info[avalon->device_id];
  608. avalon_get_work_count = info->miner_count;
  609. if (unlikely(avalon->device_fd == -1))
  610. if (!avalon_prepare(thr)) {
  611. applog(LOG_ERR, "AVA%i: Comms error(open)",
  612. avalon->device_id);
  613. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  614. /* fail the device if the reopen attempt fails */
  615. return -1;
  616. }
  617. fd = avalon->device_fd;
  618. #ifndef WIN32
  619. tcflush(fd, TCOFLUSH);
  620. #endif
  621. for (i = 0; i < avalon_get_work_count; i++) {
  622. info->bulk0[i] = info->bulk1[i];
  623. info->bulk1[i] = info->bulk2[i];
  624. info->bulk2[i] = info->bulk3[i];
  625. info->bulk3[i] = work[i];
  626. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  627. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  628. }
  629. i = 0;
  630. while (true) {
  631. avalon_init_task(&at, 0, 0, info->fan_pwm,
  632. info->timeout, info->asic_count,
  633. info->miner_count, 1);
  634. avalon_create_task(&at, work[i]);
  635. ret = avalon_send_task(fd, &at, thr);
  636. if (unlikely(ret == AVA_SEND_ERROR ||
  637. (ret == AVA_SEND_BUFFER_EMPTY &&
  638. (i + 1 == avalon_get_work_count) &&
  639. first_try))) {
  640. avalon_free_work(thr, info->bulk0);
  641. avalon_free_work(thr, info->bulk1);
  642. avalon_free_work(thr, info->bulk2);
  643. avalon_free_work(thr, info->bulk3);
  644. do_avalon_close(thr);
  645. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  646. avalon->device_id);
  647. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  648. first_try = 0;
  649. sleep(1);
  650. return 0; /* This should never happen */
  651. }
  652. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  653. first_try = 1;
  654. return 0xffffffff;
  655. }
  656. work[i]->blk.nonce = 0xffffffff;
  657. if (ret == AVA_SEND_BUFFER_FULL)
  658. break;
  659. i++;
  660. }
  661. if (unlikely(first_try))
  662. first_try = 0;
  663. elapsed.tv_sec = elapsed.tv_usec = 0;
  664. gettimeofday(&tv_start, NULL);
  665. hash_count = 0;
  666. while (true) {
  667. work_i0 = work_i1 = work_i2 = -1;
  668. full = avalon_buffer_full(fd);
  669. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  670. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  671. if (unlikely(full == AVA_BUFFER_EMPTY))
  672. break;
  673. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  674. if (unlikely(ret == AVA_GETS_ERROR)) {
  675. avalon_free_work(thr, info->bulk0);
  676. avalon_free_work(thr, info->bulk1);
  677. avalon_free_work(thr, info->bulk2);
  678. avalon_free_work(thr, info->bulk3);
  679. do_avalon_close(thr);
  680. applog(LOG_ERR,
  681. "AVA%i: Comms error(read)", avalon->device_id);
  682. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  683. return 0;
  684. }
  685. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  686. timersub(&tv_finish, &tv_start, &elapsed);
  687. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  688. elapsed.tv_sec, elapsed.tv_usec);
  689. continue;
  690. }
  691. if (unlikely(ret == AVA_GETS_RESTART)) {
  692. avalon_free_work(thr, info->bulk0);
  693. avalon_free_work(thr, info->bulk1);
  694. avalon_free_work(thr, info->bulk2);
  695. avalon_free_work(thr, info->bulk3);
  696. continue;
  697. }
  698. record_temp_fan(info, &ar, &(avalon->temp));
  699. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  700. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  701. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  702. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  703. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  704. if (opt_debug) {
  705. timersub(&tv_finish, &tv_start, &elapsed);
  706. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  707. " (%ld.%06lds)", ++info->no_matching_work,
  708. elapsed.tv_sec, elapsed.tv_usec);
  709. }
  710. continue;
  711. }
  712. if (work_i0 >= 0)
  713. submit_nonce(thr, info->bulk0[work_i0], nonce);
  714. if (work_i1 >= 0)
  715. submit_nonce(thr, info->bulk1[work_i1], nonce);
  716. if (work_i2 >= 0)
  717. submit_nonce(thr, info->bulk2[work_i2], nonce);
  718. if (work_i3 >= 0)
  719. submit_nonce(thr, info->bulk3[work_i3], nonce);
  720. hash_count += nonce;
  721. if (opt_debug) {
  722. timersub(&tv_finish, &tv_start, &elapsed);
  723. applog(LOG_DEBUG,
  724. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  725. "(%ld.%06lds)", nonce, hash_count,
  726. elapsed.tv_sec, elapsed.tv_usec);
  727. }
  728. }
  729. avalon_free_work(thr, info->bulk0);
  730. applog(LOG_WARNING,
  731. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  732. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  733. info->fan0, info->fan1, info->fan2,
  734. info->temp0, info->temp1, info->temp2, info->temp_max);
  735. info->temp_history_index++;
  736. info->temp_sum += info->temp2;
  737. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  738. info->temp_history_index, info->temp_history_count, info->temp_old);
  739. if (info->temp_history_index == info->temp_history_count) {
  740. adjust_fan(info);
  741. info->temp_history_index = 0;
  742. info->temp_sum = 0;
  743. }
  744. /*
  745. * FIXME: Each work split to 10 pieces, each piece send to a
  746. * asic(256MHs). one work can be mulit-nonce back. it is not
  747. * easy calculate correct hash on such situation. so I simplely
  748. * add each nonce to hash_count. base on Utility/m hash_count*2
  749. * give a very good result.
  750. *
  751. * Any patch will be great.
  752. */
  753. return (hash_count * 2);
  754. }
  755. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  756. {
  757. struct api_data *root = NULL;
  758. struct avalon_info *info = avalon_info[cgpu->device_id];
  759. root = api_add_int(root, "read_count", &(info->read_count), false);
  760. root = api_add_int(root, "baud", &(info->baud), false);
  761. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  762. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  763. root = api_add_int(root, "fan1", &(info->fan0), false);
  764. root = api_add_int(root, "fan2", &(info->fan1), false);
  765. root = api_add_int(root, "fan3", &(info->fan2), false);
  766. root = api_add_int(root, "temp1", &(info->temp0), false);
  767. root = api_add_int(root, "temp2", &(info->temp1), false);
  768. root = api_add_int(root, "temp3", &(info->temp2), false);
  769. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  770. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  771. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  772. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  773. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  774. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  775. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  776. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  777. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  778. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  779. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  780. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  781. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  782. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  783. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  784. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  785. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  786. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  787. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  788. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  789. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  790. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  791. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  792. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  793. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  794. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  795. return root;
  796. }
  797. static void avalon_shutdown(struct thr_info *thr)
  798. {
  799. do_avalon_close(thr);
  800. }
  801. struct device_api avalon_api = {
  802. .dname = "avalon",
  803. .name = "AVA",
  804. .api_detect = avalon_detect,
  805. .thread_prepare = avalon_prepare,
  806. .scanhash_queue = avalon_scanhash,
  807. .get_api_stats = avalon_api_stats,
  808. .thread_shutdown = avalon_shutdown,
  809. };