driver-avalon.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011
  1. /*
  2. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Luke Dashjr
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static int option_offset = -1;
  36. struct avalon_info **avalon_info;
  37. struct device_api avalon_api;
  38. static int avalon_init_task(struct avalon_task *at,
  39. uint8_t reset, uint8_t ff, uint8_t fan,
  40. uint8_t timeout, uint8_t asic_num,
  41. uint8_t miner_num, uint8_t nonce_elf,
  42. uint8_t gate_miner, int frequency)
  43. {
  44. uint8_t *buf;
  45. static bool first = true;
  46. if (unlikely(!at))
  47. return -1;
  48. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  49. return -1;
  50. memset(at, 0, sizeof(struct avalon_task));
  51. if (unlikely(reset)) {
  52. at->reset = 1;
  53. at->fan_eft = 1;
  54. at->timer_eft = 1;
  55. first = true;
  56. }
  57. at->flush_fifo = (ff ? 1 : 0);
  58. at->fan_eft = (fan ? 1 : 0);
  59. if (unlikely(first && !at->reset)) {
  60. at->fan_eft = 1;
  61. at->timer_eft = 1;
  62. first = false;
  63. }
  64. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  65. at->timeout_data = timeout;
  66. at->asic_num = asic_num;
  67. at->miner_num = miner_num;
  68. at->nonce_elf = nonce_elf;
  69. at->gate_miner_elf = 1;
  70. at->asic_pll = 1;
  71. if (unlikely(gate_miner)) {
  72. at-> gate_miner = 1;
  73. at->asic_pll = 0;
  74. }
  75. buf = (uint8_t *)at;
  76. buf[5] = 0x00;
  77. buf[8] = 0x74;
  78. buf[9] = 0x01;
  79. buf[10] = 0x00;
  80. buf[11] = 0x00;
  81. if (frequency == 256) {
  82. buf[6] = 0x03;
  83. buf[7] = 0x08;
  84. } else if (frequency == 270) {
  85. buf[6] = 0x73;
  86. buf[7] = 0x08;
  87. } else if (frequency == 282) {
  88. buf[6] = 0xd3;
  89. buf[7] = 0x08;
  90. } else if (frequency == 300) {
  91. buf[6] = 0x63;
  92. buf[7] = 0x09;
  93. }
  94. return 0;
  95. }
  96. static inline void avalon_create_task(struct avalon_task *at,
  97. struct work *work)
  98. {
  99. memcpy(at->midstate, work->midstate, 32);
  100. memcpy(at->data, work->data + 64, 12);
  101. }
  102. static int avalon_send_task(int fd, const struct avalon_task *at,
  103. struct cgpu_info *avalon)
  104. {
  105. size_t ret;
  106. int full;
  107. struct timespec p;
  108. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  109. size_t nr_len;
  110. struct avalon_info *info;
  111. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  112. uint32_t nonce_range;
  113. int i;
  114. if (at->nonce_elf)
  115. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  116. else
  117. nr_len = AVALON_WRITE_SIZE;
  118. memcpy(buf, at, AVALON_WRITE_SIZE);
  119. if (at->nonce_elf) {
  120. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  121. for (i = 0; i < at->asic_num; i++) {
  122. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  123. (i * nonce_range & 0xff000000) >> 24;
  124. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  125. (i * nonce_range & 0x00ff0000) >> 16;
  126. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  127. (i * nonce_range & 0x0000ff00) >> 8;
  128. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  129. (i * nonce_range & 0x000000ff) >> 0;
  130. }
  131. }
  132. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  133. uint8_t tt = 0;
  134. tt = (buf[0] & 0x0f) << 4;
  135. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  136. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  137. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  138. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  139. buf[0] = tt;
  140. tt = (buf[4] & 0x0f) << 4;
  141. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  142. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  143. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  144. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  145. buf[4] = tt;
  146. #endif
  147. if (likely(avalon)) {
  148. info = avalon_info[avalon->device_id];
  149. delay = nr_len * 10 * 1000000000ULL;
  150. delay = delay / info->baud;
  151. }
  152. if (at->reset)
  153. nr_len = 1;
  154. if (opt_debug) {
  155. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  156. hexdump((uint8_t *)buf, nr_len);
  157. }
  158. ret = write(fd, buf, nr_len);
  159. if (unlikely(ret != nr_len))
  160. return AVA_SEND_ERROR;
  161. p.tv_sec = 0;
  162. p.tv_nsec = (long)delay + 4000000;
  163. nanosleep(&p, NULL);
  164. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  165. full = avalon_buffer_full(fd);
  166. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  167. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  168. if (unlikely(full == AVA_BUFFER_FULL))
  169. return AVA_SEND_BUFFER_FULL;
  170. return AVA_SEND_BUFFER_EMPTY;
  171. }
  172. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  173. struct thr_info *thr, struct timeval *tv_finish)
  174. {
  175. ssize_t ret = 0;
  176. int rc = 0;
  177. int read_amount = AVALON_READ_SIZE;
  178. bool first = true;
  179. /* Read reply 1 byte at a time to get earliest tv_finish */
  180. while (true) {
  181. ret = read(fd, buf, 1);
  182. if (ret < 0)
  183. return AVA_GETS_ERROR;
  184. if (first && tv_finish != NULL)
  185. gettimeofday(tv_finish, NULL);
  186. if (ret >= read_amount)
  187. return AVA_GETS_OK;
  188. if (ret > 0) {
  189. buf += ret;
  190. read_amount -= ret;
  191. first = false;
  192. continue;
  193. }
  194. rc++;
  195. if (rc >= read_count) {
  196. if (opt_debug) {
  197. applog(LOG_WARNING,
  198. "Avalon: No data in %.2f seconds",
  199. (float)rc/(float)AVALON_TIME_FACTOR);
  200. }
  201. return AVA_GETS_TIMEOUT;
  202. }
  203. if (thr && thr->work_restart) {
  204. if (opt_debug) {
  205. applog(LOG_WARNING,
  206. "Avalon: Work restart at %.2f seconds",
  207. (float)(rc)/(float)AVALON_TIME_FACTOR);
  208. }
  209. return AVA_GETS_RESTART;
  210. }
  211. }
  212. }
  213. static int avalon_get_result(int fd, struct avalon_result *ar,
  214. struct thr_info *thr, struct timeval *tv_finish)
  215. {
  216. struct cgpu_info *avalon;
  217. struct avalon_info *info;
  218. uint8_t result[AVALON_READ_SIZE];
  219. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  220. if (likely(thr)) {
  221. avalon = thr->cgpu;
  222. info = avalon_info[avalon->device_id];
  223. read_count = info->read_count;
  224. }
  225. memset(result, 0, AVALON_READ_SIZE);
  226. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  227. if (ret == AVA_GETS_OK) {
  228. if (opt_debug) {
  229. applog(LOG_DEBUG, "Avalon: get:");
  230. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  231. }
  232. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  233. }
  234. return ret;
  235. }
  236. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  237. struct avalon_result *ar, uint32_t *nonce)
  238. {
  239. struct cgpu_info *avalon;
  240. struct avalon_info *info;
  241. int avalon_get_work_count, i;
  242. if (unlikely(!work))
  243. return -1;
  244. avalon = thr->cgpu;
  245. info = avalon_info[avalon->device_id];
  246. avalon_get_work_count = info->miner_count;
  247. for (i = 0; i < avalon_get_work_count; i++) {
  248. if (work[i] &&
  249. !memcmp(ar->data, work[i]->data + 64, 12) &&
  250. !memcmp(ar->midstate, work[i]->midstate, 32))
  251. break;
  252. }
  253. if (i == avalon_get_work_count)
  254. return -1;
  255. info->matching_work[i]++;
  256. *nonce = htole32(ar->nonce);
  257. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  258. info->matching_work[i]);
  259. return i;
  260. }
  261. static int avalon_reset(int fd, struct avalon_result *ar)
  262. {
  263. struct avalon_task at;
  264. uint8_t *buf;
  265. int ret, i = 0;
  266. struct timespec p;
  267. avalon_init_task(&at, 1, 0,
  268. AVALON_DEFAULT_FAN_MAX_PWM,
  269. AVALON_DEFAULT_TIMEOUT,
  270. AVALON_DEFAULT_ASIC_NUM,
  271. AVALON_DEFAULT_MINER_NUM,
  272. 0, 0,
  273. AVALON_DEFAULT_FREQUENCY);
  274. ret = avalon_send_task(fd, &at, NULL);
  275. if (ret == AVA_SEND_ERROR)
  276. return 1;
  277. avalon_get_result(fd, ar, NULL, NULL);
  278. buf = (uint8_t *)ar;
  279. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  280. buf[2] == 0xAA && buf[3] == 0x55) {
  281. for (i = 4; i < 11; i++)
  282. if (buf[i] != 0)
  283. break;
  284. }
  285. if (i != 11) {
  286. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  287. " (%d: %02x %02x %02x %02x)",
  288. i, buf[0], buf[1], buf[2], buf[3]);
  289. /* FIXME: return 1; */
  290. }
  291. p.tv_sec = 0;
  292. p.tv_nsec = AVALON_RESET_PITCH;
  293. nanosleep(&p, NULL);
  294. applog(LOG_WARNING, "Avalon: Reset succeeded");
  295. return 0;
  296. }
  297. static void avalon_idle(struct cgpu_info *avalon)
  298. {
  299. int i, ret;
  300. struct avalon_task at;
  301. int fd = avalon->device_fd;
  302. struct avalon_info *info = avalon_info[avalon->device_id];
  303. int avalon_get_work_count = info->miner_count;
  304. i = 0;
  305. while (true) {
  306. avalon_init_task(&at, 0, 0, info->fan_pwm,
  307. info->timeout, info->asic_count,
  308. info->miner_count, 1, 1, info->frequency);
  309. ret = avalon_send_task(fd, &at, avalon);
  310. if (unlikely(ret == AVA_SEND_ERROR ||
  311. (ret == AVA_SEND_BUFFER_EMPTY &&
  312. (i + 1 == avalon_get_work_count * 2)))) {
  313. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  314. return;
  315. }
  316. if (i + 1 == avalon_get_work_count * 2)
  317. break;
  318. if (ret == AVA_SEND_BUFFER_FULL)
  319. break;
  320. i++;
  321. }
  322. applog(LOG_ERR, "Avalon: Goto idle mode");
  323. }
  324. static void get_options(int this_option_offset, int *baud, int *miner_count,
  325. int *asic_count, int *timeout, int *frequency)
  326. {
  327. char err_buf[BUFSIZ+1];
  328. char buf[BUFSIZ+1];
  329. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  330. size_t max;
  331. int i, tmp;
  332. if (opt_avalon_options == NULL)
  333. buf[0] = '\0';
  334. else {
  335. ptr = opt_avalon_options;
  336. for (i = 0; i < this_option_offset; i++) {
  337. comma = strchr(ptr, ',');
  338. if (comma == NULL)
  339. break;
  340. ptr = comma + 1;
  341. }
  342. comma = strchr(ptr, ',');
  343. if (comma == NULL)
  344. max = strlen(ptr);
  345. else
  346. max = comma - ptr;
  347. if (max > BUFSIZ)
  348. max = BUFSIZ;
  349. strncpy(buf, ptr, max);
  350. buf[max] = '\0';
  351. }
  352. *baud = AVALON_IO_SPEED;
  353. *miner_count = AVALON_DEFAULT_MINER_NUM - 8;
  354. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  355. *timeout = AVALON_DEFAULT_TIMEOUT;
  356. *frequency = AVALON_DEFAULT_FREQUENCY;
  357. if (!(*buf))
  358. return;
  359. colon = strchr(buf, ':');
  360. if (colon)
  361. *(colon++) = '\0';
  362. tmp = atoi(buf);
  363. switch (tmp) {
  364. case 115200:
  365. *baud = 115200;
  366. break;
  367. case 57600:
  368. *baud = 57600;
  369. break;
  370. case 38400:
  371. *baud = 38400;
  372. break;
  373. case 19200:
  374. *baud = 19200;
  375. break;
  376. default:
  377. sprintf(err_buf,
  378. "Invalid avalon-options for baud (%s) "
  379. "must be 115200, 57600, 38400 or 19200", buf);
  380. quit(1, err_buf);
  381. }
  382. if (colon && *colon) {
  383. colon2 = strchr(colon, ':');
  384. if (colon2)
  385. *(colon2++) = '\0';
  386. if (*colon) {
  387. tmp = atoi(colon);
  388. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  389. *miner_count = tmp;
  390. } else {
  391. sprintf(err_buf,
  392. "Invalid avalon-options for "
  393. "miner_count (%s) must be 1 ~ %d",
  394. colon, AVALON_DEFAULT_MINER_NUM);
  395. quit(1, err_buf);
  396. }
  397. }
  398. if (colon2 && *colon2) {
  399. colon3 = strchr(colon2, ':');
  400. if (colon3)
  401. *(colon3++) = '\0';
  402. tmp = atoi(colon2);
  403. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  404. *asic_count = tmp;
  405. else {
  406. sprintf(err_buf,
  407. "Invalid avalon-options for "
  408. "asic_count (%s) must be 1 ~ %d",
  409. colon2, AVALON_DEFAULT_ASIC_NUM);
  410. quit(1, err_buf);
  411. }
  412. if (colon3 && *colon3) {
  413. colon4 = strchr(colon3, ':');
  414. if (colon4)
  415. *(colon4++) = '\0';
  416. tmp = atoi(colon3);
  417. if (tmp > 0 && tmp <= 0xff)
  418. *timeout = tmp;
  419. else {
  420. sprintf(err_buf,
  421. "Invalid avalon-options for "
  422. "timeout (%s) must be 1 ~ %d",
  423. colon3, 0xff);
  424. quit(1, err_buf);
  425. }
  426. if (colon4 && *colon4) {
  427. tmp = atoi(colon4);
  428. switch (tmp) {
  429. case 256:
  430. case 270:
  431. case 282:
  432. case 300:
  433. *frequency = tmp;
  434. break;
  435. default:
  436. sprintf(err_buf,
  437. "Invalid avalon-options for "
  438. "frequency must be 256/270/282/300");
  439. quit(1, err_buf);
  440. }
  441. }
  442. }
  443. }
  444. }
  445. }
  446. static bool avalon_detect_one(const char *devpath)
  447. {
  448. struct avalon_info *info;
  449. struct avalon_result ar;
  450. int fd, ret;
  451. int baud, miner_count, asic_count, timeout, frequency = 0;
  452. int this_option_offset = ++option_offset;
  453. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  454. &timeout, &frequency);
  455. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  456. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  457. devpath, baud, miner_count, asic_count, timeout, frequency);
  458. fd = avalon_open2(devpath, baud, true);
  459. if (unlikely(fd == -1)) {
  460. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  461. return false;
  462. }
  463. ret = avalon_reset(fd, &ar);
  464. if (ret) {
  465. ; /* FIXME: I think IT IS avalon and wait on reset;
  466. * avalon_close(fd);
  467. * return false; */
  468. }
  469. /* We have a real Avalon! */
  470. struct cgpu_info *avalon;
  471. avalon = calloc(1, sizeof(struct cgpu_info));
  472. avalon->api = &avalon_api;
  473. avalon->device_path = strdup(devpath);
  474. avalon->device_fd = fd;
  475. avalon->threads = AVALON_MINER_THREADS;
  476. add_cgpu(avalon);
  477. avalon_info = realloc(avalon_info,
  478. sizeof(struct avalon_info *) *
  479. (total_devices + 1));
  480. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  481. devpath, avalon->device_id);
  482. avalon_info[avalon->device_id] = (struct avalon_info *)
  483. malloc(sizeof(struct avalon_info));
  484. if (unlikely(!(avalon_info[avalon->device_id])))
  485. quit(1, "Failed to malloc avalon_info");
  486. info = avalon_info[avalon->device_id];
  487. memset(info, 0, sizeof(struct avalon_info));
  488. info->baud = baud;
  489. info->miner_count = miner_count;
  490. info->asic_count = asic_count;
  491. info->timeout = timeout;
  492. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  493. AVALON_TIME_FACTOR) / (float)info->miner_count;
  494. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  495. info->temp_max = 0;
  496. /* This is for check the temp/fan every 3~4s */
  497. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  498. if (info->temp_history_count <= 0)
  499. info->temp_history_count = 1;
  500. info->temp_history_index = 0;
  501. info->temp_sum = 0;
  502. info->temp_old = 0;
  503. info->frequency = frequency;
  504. /* Set asic to idle mode after detect */
  505. avalon_idle(avalon);
  506. avalon->device_fd = -1;
  507. avalon_close(fd);
  508. return true;
  509. }
  510. static inline void avalon_detect()
  511. {
  512. serial_detect(&avalon_api, avalon_detect_one);
  513. }
  514. static void avalon_init(struct cgpu_info *avalon)
  515. {
  516. struct avalon_result ar;
  517. int fd, ret;
  518. avalon->device_fd = -1;
  519. fd = avalon_open(avalon->device_path,
  520. avalon_info[avalon->device_id]->baud);
  521. if (unlikely(fd == -1)) {
  522. applog(LOG_ERR, "Avalon: Failed to open on %s",
  523. avalon->device_path);
  524. return;
  525. }
  526. ret = avalon_reset(fd, &ar);
  527. if (ret) {
  528. avalon_close(fd);
  529. return;
  530. }
  531. avalon->device_fd = fd;
  532. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  533. return;
  534. }
  535. static bool avalon_prepare(struct thr_info *thr)
  536. {
  537. struct cgpu_info *avalon = thr->cgpu;
  538. struct timeval now;
  539. avalon_init(avalon);
  540. if (avalon->device_fd == -1)
  541. return false;
  542. gettimeofday(&now, NULL);
  543. get_datestamp(avalon->init, &now);
  544. return true;
  545. }
  546. static void avalon_free_work(struct thr_info *thr, struct work **work)
  547. {
  548. struct cgpu_info *avalon;
  549. struct avalon_info *info;
  550. int i;
  551. if (unlikely(!work))
  552. return;
  553. avalon = thr->cgpu;
  554. info = avalon_info[avalon->device_id];
  555. for (i = 0; i < info->miner_count; i++)
  556. if (likely(work[i])) {
  557. free_work(work[i]);
  558. work[i] = NULL;
  559. }
  560. }
  561. static void do_avalon_close(struct thr_info *thr)
  562. {
  563. struct avalon_result ar;
  564. struct cgpu_info *avalon = thr->cgpu;
  565. struct avalon_info *info = avalon_info[avalon->device_id];
  566. sleep(1);
  567. avalon_reset(avalon->device_fd, &ar);
  568. avalon_idle(avalon);
  569. avalon_close(avalon->device_fd);
  570. avalon->device_fd = -1;
  571. info->no_matching_work = 0;
  572. avalon_free_work(thr, info->bulk0);
  573. avalon_free_work(thr, info->bulk1);
  574. avalon_free_work(thr, info->bulk2);
  575. avalon_free_work(thr, info->bulk3);
  576. }
  577. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  578. {
  579. int max;
  580. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  581. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  582. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  583. info->temp0 = ar->temp0;
  584. info->temp1 = ar->temp1;
  585. info->temp2 = ar->temp2;
  586. if (ar->temp0 & 0x80) {
  587. ar->temp0 &= 0x7f;
  588. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  589. }
  590. if (ar->temp1 & 0x80) {
  591. ar->temp1 &= 0x7f;
  592. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  593. }
  594. if (ar->temp2 & 0x80) {
  595. ar->temp2 &= 0x7f;
  596. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  597. }
  598. *temp_avg = info->temp2;
  599. max = info->temp_max;
  600. if (info->temp0 > max)
  601. max = info->temp0;
  602. if (info->temp1 > max)
  603. max = info->temp1;
  604. if (info->temp2 > max)
  605. max = info->temp2;
  606. if (max >= 100) { /* FIXME: fix the root cause on fpga controller firmware */
  607. if (opt_debug) {
  608. applog(LOG_DEBUG, "Avalon: temp_max: %d", max);
  609. hexdump((uint8_t *)ar, AVALON_READ_SIZE);
  610. }
  611. return;
  612. }
  613. info->temp_max = max;
  614. }
  615. static inline void adjust_fan(struct avalon_info *info)
  616. {
  617. int temp_new;
  618. temp_new = info->temp_sum / info->temp_history_count;
  619. if (temp_new < 35) {
  620. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  621. info->temp_old = temp_new;
  622. } else if (temp_new > 55) {
  623. info->fan_pwm = AVALON_DEFAULT_FAN_MAX_PWM;
  624. info->temp_old = temp_new;
  625. } else if (abs(temp_new - info->temp_old) >= 2) {
  626. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM + (temp_new - 35) * 6.4;
  627. info->temp_old = temp_new;
  628. }
  629. }
  630. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  631. __maybe_unused int64_t max_nonce)
  632. {
  633. struct cgpu_info *avalon;
  634. int fd, ret, full;
  635. struct avalon_info *info;
  636. struct avalon_task at;
  637. struct avalon_result ar;
  638. int i, work_i0, work_i1, work_i2, work_i3;
  639. int avalon_get_work_count;
  640. struct timeval tv_start, tv_finish, elapsed;
  641. uint32_t nonce;
  642. int64_t hash_count;
  643. static int first_try = 0;
  644. int result_count, result_wrong;
  645. avalon = thr->cgpu;
  646. info = avalon_info[avalon->device_id];
  647. avalon_get_work_count = info->miner_count;
  648. if (unlikely(avalon->device_fd == -1))
  649. if (!avalon_prepare(thr)) {
  650. applog(LOG_ERR, "AVA%i: Comms error(open)",
  651. avalon->device_id);
  652. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  653. /* fail the device if the reopen attempt fails */
  654. return -1;
  655. }
  656. fd = avalon->device_fd;
  657. #ifndef WIN32
  658. tcflush(fd, TCOFLUSH);
  659. #endif
  660. for (i = 0; i < avalon_get_work_count; i++) {
  661. info->bulk0[i] = info->bulk1[i];
  662. info->bulk1[i] = info->bulk2[i];
  663. info->bulk2[i] = info->bulk3[i];
  664. info->bulk3[i] = work[i];
  665. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  666. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  667. }
  668. i = 0;
  669. while (true) {
  670. avalon_init_task(&at, 0, 0, info->fan_pwm,
  671. info->timeout, info->asic_count,
  672. info->miner_count, 1, 0, info->frequency);
  673. avalon_create_task(&at, work[i]);
  674. ret = avalon_send_task(fd, &at, avalon);
  675. if (unlikely(ret == AVA_SEND_ERROR ||
  676. (ret == AVA_SEND_BUFFER_EMPTY &&
  677. (i + 1 == avalon_get_work_count) &&
  678. first_try))) {
  679. avalon_free_work(thr, info->bulk0);
  680. avalon_free_work(thr, info->bulk1);
  681. avalon_free_work(thr, info->bulk2);
  682. avalon_free_work(thr, info->bulk3);
  683. do_avalon_close(thr);
  684. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  685. avalon->device_id);
  686. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  687. first_try = 0;
  688. sleep(1);
  689. return 0; /* This should never happen */
  690. }
  691. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  692. first_try = 1;
  693. return 0xffffffff;
  694. }
  695. work[i]->blk.nonce = 0xffffffff;
  696. if (ret == AVA_SEND_BUFFER_FULL)
  697. break;
  698. i++;
  699. }
  700. if (unlikely(first_try))
  701. first_try = 0;
  702. elapsed.tv_sec = elapsed.tv_usec = 0;
  703. gettimeofday(&tv_start, NULL);
  704. result_count = 0;
  705. result_wrong = 0;
  706. hash_count = 0;
  707. while (true) {
  708. work_i0 = work_i1 = work_i2 = work_i3 = -1;
  709. full = avalon_buffer_full(fd);
  710. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  711. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  712. if (unlikely(full == AVA_BUFFER_EMPTY))
  713. break;
  714. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  715. if (unlikely(ret == AVA_GETS_ERROR)) {
  716. avalon_free_work(thr, info->bulk0);
  717. avalon_free_work(thr, info->bulk1);
  718. avalon_free_work(thr, info->bulk2);
  719. avalon_free_work(thr, info->bulk3);
  720. do_avalon_close(thr);
  721. applog(LOG_ERR,
  722. "AVA%i: Comms error(read)", avalon->device_id);
  723. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  724. return 0;
  725. }
  726. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  727. timersub(&tv_finish, &tv_start, &elapsed);
  728. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  729. elapsed.tv_sec, elapsed.tv_usec);
  730. continue;
  731. }
  732. if (unlikely(ret == AVA_GETS_RESTART)) {
  733. avalon_free_work(thr, info->bulk0);
  734. avalon_free_work(thr, info->bulk1);
  735. avalon_free_work(thr, info->bulk2);
  736. avalon_free_work(thr, info->bulk3);
  737. continue;
  738. }
  739. result_count++;
  740. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  741. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  742. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  743. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  744. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  745. info->no_matching_work++;
  746. result_wrong++;
  747. if (opt_debug) {
  748. timersub(&tv_finish, &tv_start, &elapsed);
  749. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  750. " (%ld.%06lds)", info->no_matching_work,
  751. elapsed.tv_sec, elapsed.tv_usec);
  752. }
  753. continue;
  754. }
  755. if (work_i0 >= 0)
  756. submit_nonce(thr, info->bulk0[work_i0], nonce);
  757. if (work_i1 >= 0)
  758. submit_nonce(thr, info->bulk1[work_i1], nonce);
  759. if (work_i2 >= 0)
  760. submit_nonce(thr, info->bulk2[work_i2], nonce);
  761. if (work_i3 >= 0)
  762. submit_nonce(thr, info->bulk3[work_i3], nonce);
  763. hash_count += nonce;
  764. if (opt_debug) {
  765. timersub(&tv_finish, &tv_start, &elapsed);
  766. applog(LOG_DEBUG,
  767. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  768. "(%ld.%06lds)", nonce, hash_count,
  769. elapsed.tv_sec, elapsed.tv_usec);
  770. }
  771. }
  772. if (result_count == result_wrong) {
  773. /* This mean FPGA controller give all wrong result
  774. * try to reset the Avalon */
  775. avalon_free_work(thr, info->bulk0);
  776. avalon_free_work(thr, info->bulk1);
  777. avalon_free_work(thr, info->bulk2);
  778. avalon_free_work(thr, info->bulk3);
  779. do_avalon_close(thr);
  780. applog(LOG_ERR,
  781. "AVA%i: FPGA controller mess up", avalon->device_id);
  782. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  783. return 0;
  784. }
  785. avalon_free_work(thr, info->bulk0);
  786. record_temp_fan(info, &ar, &(avalon->temp));
  787. applog(LOG_INFO,
  788. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  789. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  790. info->fan0, info->fan1, info->fan2,
  791. info->temp0, info->temp1, info->temp2, info->temp_max);
  792. info->temp_history_index++;
  793. info->temp_sum += info->temp2;
  794. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  795. info->temp_history_index, info->temp_history_count, info->temp_old);
  796. if (info->temp_history_index == info->temp_history_count) {
  797. adjust_fan(info);
  798. info->temp_history_index = 0;
  799. info->temp_sum = 0;
  800. }
  801. /*
  802. * FIXME: Each work split to 10 pieces, each piece send to a
  803. * asic(256MHs). one work can be mulit-nonce back. it is not
  804. * easy calculate correct hash on such situation. so I simplely
  805. * add each nonce to hash_count. base on Utility/m hash_count*2
  806. * give a very good result.
  807. *
  808. * Any patch will be great.
  809. */
  810. return (hash_count * 2);
  811. }
  812. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  813. {
  814. struct api_data *root = NULL;
  815. struct avalon_info *info = avalon_info[cgpu->device_id];
  816. root = api_add_int(root, "baud", &(info->baud), false);
  817. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  818. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  819. root = api_add_int(root, "read_count", &(info->read_count), false);
  820. root = api_add_int(root, "timeout", &(info->timeout), false);
  821. root = api_add_int(root, "frequency", &(info->frequency), false);
  822. root = api_add_int(root, "fan1", &(info->fan0), false);
  823. root = api_add_int(root, "fan2", &(info->fan1), false);
  824. root = api_add_int(root, "fan3", &(info->fan2), false);
  825. root = api_add_int(root, "temp1", &(info->temp0), false);
  826. root = api_add_int(root, "temp2", &(info->temp1), false);
  827. root = api_add_int(root, "temp3", &(info->temp2), false);
  828. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  829. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  830. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  831. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  832. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  833. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  834. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  835. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  836. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  837. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  838. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  839. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  840. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  841. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  842. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  843. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  844. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  845. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  846. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  847. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  848. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  849. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  850. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  851. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  852. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  853. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  854. return root;
  855. }
  856. static void avalon_shutdown(struct thr_info *thr)
  857. {
  858. do_avalon_close(thr);
  859. }
  860. struct device_api avalon_api = {
  861. .dname = "avalon",
  862. .name = "AVA",
  863. .api_detect = avalon_detect,
  864. .thread_prepare = avalon_prepare,
  865. .scanhash_queue = avalon_scanhash,
  866. .get_api_stats = avalon_api_stats,
  867. .reinit_device = avalon_init,
  868. .thread_shutdown = avalon_shutdown,
  869. };