driver-avalon.c 23 KB

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  1. /*
  2. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  3. * Copyright 2012 Andrew Smith
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include "config.h"
  11. #include <limits.h>
  12. #include <pthread.h>
  13. #include <stdio.h>
  14. #include <sys/time.h>
  15. #include <sys/types.h>
  16. #include <dirent.h>
  17. #include <unistd.h>
  18. #ifndef WIN32
  19. #include <termios.h>
  20. #include <sys/stat.h>
  21. #include <fcntl.h>
  22. #ifndef O_CLOEXEC
  23. #define O_CLOEXEC 0
  24. #endif
  25. #else
  26. #include <windows.h>
  27. #include <io.h>
  28. #endif
  29. #include "elist.h"
  30. #include "miner.h"
  31. #include "fpgautils.h"
  32. #include "driver-avalon.h"
  33. #include "hexdump.c"
  34. static struct timeval history_sec = { HISTORY_SEC, 0 };
  35. static const char *MODE_DEFAULT_STR = "default";
  36. static const char *MODE_SHORT_STR = "short";
  37. static const char *MODE_LONG_STR = "long";
  38. static const char *MODE_VALUE_STR = "value";
  39. static const char *MODE_UNKNOWN_STR = "unknown";
  40. static int option_offset = -1;
  41. static struct AVALON_INFO **avalon_info;
  42. struct device_api avalon_api;
  43. static int avalon_init_task(struct avalon_task *at, uint8_t reset, uint8_t ff,
  44. uint8_t fan, uint8_t timeout, uint8_t chip_num,
  45. uint8_t miner_num)
  46. {
  47. static bool first = true;
  48. if (!at)
  49. return -1;
  50. memset(at, 0, sizeof(struct avalon_task));
  51. if (reset) {
  52. at->reset = 1;
  53. first = true;
  54. }
  55. at->flush_fifo = (ff ? 1 : 0);
  56. at->fan_eft = (fan ? 1 : 0);
  57. if (timeout || chip_num || miner_num) {
  58. at->timer_eft = 1;
  59. }
  60. if (first && !at->reset) {
  61. at->fan_eft = 1;
  62. at->timer_eft = 1;
  63. first = false;
  64. }
  65. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  66. at->timeout_data = (timeout ? timeout : AVALON_DEFAULT_TIMEOUT);
  67. at->chip_num = (chip_num ? chip_num : AVALON_DEFAULT_CHIP_NUM);
  68. at->miner_num = (miner_num ? miner_num : AVALON_DEFAULT_MINER_NUM);
  69. at->nonce_elf = 1;
  70. return 0;
  71. }
  72. static inline void avalon_create_task(struct avalon_task *at,
  73. struct work *work)
  74. {
  75. memcpy(at->midstate, work->midstate, 32);
  76. memcpy(at->data, work->data + 64, 12);
  77. }
  78. static int avalon_send_task(int fd, const struct avalon_task *at)
  79. {
  80. size_t ret;
  81. int full;
  82. struct timespec p;
  83. uint8_t *buf;
  84. int nr_len;
  85. nr_len = AVALON_WRITE_SIZE + 4 * at->chip_num;
  86. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  87. if (!buf)
  88. return AVA_SEND_ERROR;
  89. memcpy(buf, at, AVALON_WRITE_SIZE);
  90. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  91. uint8_t tt = 0;
  92. tt = (buf[0] & 0x0f) << 4;
  93. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  94. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  95. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  96. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  97. buf[0] = tt;
  98. buf[4] = rev8(buf[4]);
  99. #endif
  100. if (opt_debug) {
  101. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  102. hexdump((uint8_t *)buf, nr_len);
  103. }
  104. ret = write(fd, buf, nr_len);
  105. free(buf);
  106. if (unlikely(ret != nr_len))
  107. return AVA_SEND_ERROR;
  108. p.tv_sec = 0;
  109. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  110. nanosleep(&p, NULL);
  111. full = avalon_buffer_full(fd);
  112. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  113. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  114. if (full == AVA_BUFFER_EMPTY)
  115. return AVA_SEND_BUFFER_EMPTY;
  116. return AVA_SEND_BUFFER_FULL;
  117. }
  118. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  119. struct thr_info *thr, struct timeval *tv_finish)
  120. {
  121. ssize_t ret = 0;
  122. int rc = 0;
  123. int read_amount = AVALON_READ_SIZE;
  124. bool first = true;
  125. /* Read reply 1 byte at a time to get earliest tv_finish */
  126. while (true) {
  127. ret = read(fd, buf, 1);
  128. if (ret < 0)
  129. return AVA_GETS_ERROR;
  130. if (first && tv_finish != NULL)
  131. gettimeofday(tv_finish, NULL);
  132. if (ret >= read_amount)
  133. return AVA_GETS_OK;
  134. if (ret > 0) {
  135. buf += ret;
  136. read_amount -= ret;
  137. first = false;
  138. continue;
  139. }
  140. rc++;
  141. if (rc >= read_count) {
  142. if (opt_debug) {
  143. applog(LOG_ERR,
  144. "Avalon: No data in %.2f seconds",
  145. (float)rc/(float)TIME_FACTOR);
  146. }
  147. return AVA_GETS_TIMEOUT;
  148. }
  149. if (thr && thr->work_restart) {
  150. if (opt_debug) {
  151. applog(LOG_ERR,
  152. "Avalon: Work restart at %.2f seconds",
  153. (float)(rc)/(float)TIME_FACTOR);
  154. }
  155. return AVA_GETS_RESTART;
  156. }
  157. }
  158. }
  159. static int avalon_get_result(int fd, struct avalon_result *ar,
  160. struct thr_info *thr, struct timeval *tv_finish)
  161. {
  162. struct cgpu_info *avalon;
  163. struct AVALON_INFO *info;
  164. uint8_t result[AVALON_READ_SIZE];
  165. int ret, read_count = 16;
  166. if (thr) {
  167. avalon = thr->cgpu;
  168. info = avalon_info[avalon->device_id];
  169. read_count = info->read_count;
  170. }
  171. memset(result, 0, AVALON_READ_SIZE);
  172. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  173. if (ret == AVA_GETS_OK) {
  174. if (opt_debug) {
  175. applog(LOG_DEBUG, "Avalon: get:");
  176. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  177. }
  178. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  179. }
  180. return ret;
  181. }
  182. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  183. uint32_t *nonce)
  184. {
  185. int i;
  186. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  187. if (!work || !work[i])
  188. return -1;
  189. }
  190. *nonce = ar->nonce;
  191. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  192. *nonce = swab32(*nonce);
  193. #endif
  194. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  195. if (!memcmp(ar->data, work[i]->data + 64, 12) &&
  196. !memcmp(ar->midstate, work[i]->midstate, 32))
  197. break;
  198. }
  199. if (i == AVALON_GET_WORK_COUNT)
  200. return -1;
  201. applog(LOG_DEBUG, "Avalon: match to work: %d", i);
  202. return i;
  203. }
  204. static int avalon_reset(int fd)
  205. {
  206. struct avalon_task at;
  207. struct avalon_result ar;
  208. uint8_t *buf;
  209. int ret, i;
  210. struct timespec p;
  211. avalon_init_task(&at,
  212. 1,
  213. 0,
  214. AVALON_DEFAULT_FAN_PWM,
  215. AVALON_DEFAULT_TIMEOUT,
  216. AVALON_DEFAULT_CHIP_NUM,
  217. AVALON_DEFAULT_MINER_NUM);
  218. ret = avalon_send_task(fd, &at);
  219. if (ret == AVA_SEND_ERROR)
  220. return 1;
  221. avalon_get_result(fd, &ar, NULL, NULL);
  222. buf = (uint8_t *)&ar;
  223. for (i = 0; i < 11; i++)
  224. if (buf[i] != 0)
  225. break;
  226. /* FIXME: add more avalon info base on return */
  227. if (i != 11) {
  228. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  229. return 1;
  230. }
  231. p.tv_sec = 1;
  232. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  233. nanosleep(&p, NULL);
  234. applog(LOG_ERR, "Avalon: Reset succeeded");
  235. return 0;
  236. }
  237. static void do_avalon_close(struct thr_info *thr)
  238. {
  239. struct cgpu_info *avalon = thr->cgpu;
  240. avalon_close(avalon->device_fd);
  241. avalon->device_fd = -1;
  242. }
  243. static const char *timing_mode_str(enum timing_mode timing_mode)
  244. {
  245. switch(timing_mode) {
  246. case MODE_DEFAULT:
  247. return MODE_DEFAULT_STR;
  248. case MODE_SHORT:
  249. return MODE_SHORT_STR;
  250. case MODE_LONG:
  251. return MODE_LONG_STR;
  252. case MODE_VALUE:
  253. return MODE_VALUE_STR;
  254. default:
  255. return MODE_UNKNOWN_STR;
  256. }
  257. }
  258. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  259. {
  260. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  261. double Hs;
  262. char buf[BUFSIZ+1];
  263. char *ptr, *comma, *eq;
  264. size_t max;
  265. int i;
  266. if (opt_icarus_timing == NULL)
  267. buf[0] = '\0';
  268. else {
  269. ptr = opt_icarus_timing;
  270. for (i = 0; i < this_option_offset; i++) {
  271. comma = strchr(ptr, ',');
  272. if (comma == NULL)
  273. break;
  274. ptr = comma + 1;
  275. }
  276. comma = strchr(ptr, ',');
  277. if (comma == NULL)
  278. max = strlen(ptr);
  279. else
  280. max = comma - ptr;
  281. if (max > BUFSIZ)
  282. max = BUFSIZ;
  283. strncpy(buf, ptr, max);
  284. buf[max] = '\0';
  285. }
  286. info->Hs = 0;
  287. info->read_count = 0;
  288. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  289. info->Hs = AVALON_HASH_TIME;
  290. info->read_count = AVALON_READ_COUNT_TIMING;
  291. info->timing_mode = MODE_SHORT;
  292. info->do_avalon_timing = true;
  293. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  294. info->Hs = AVALON_HASH_TIME;
  295. info->read_count = AVALON_READ_COUNT_TIMING;
  296. info->timing_mode = MODE_LONG;
  297. info->do_avalon_timing = true;
  298. } else if ((Hs = atof(buf)) != 0) {
  299. info->Hs = Hs / NANOSEC;
  300. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  301. if ((eq = strchr(buf, '=')) != NULL)
  302. info->read_count = atoi(eq+1);
  303. if (info->read_count < 1)
  304. info->read_count =
  305. (int)(info->fullnonce * TIME_FACTOR) - 1;
  306. if (unlikely(info->read_count < 1))
  307. info->read_count = 1;
  308. info->timing_mode = MODE_VALUE;
  309. info->do_avalon_timing = false;
  310. } else {
  311. /* Anything else in buf just uses DEFAULT mode */
  312. info->Hs = AVALON_HASH_TIME;
  313. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  314. if ((eq = strchr(buf, '=')) != NULL)
  315. info->read_count = atoi(eq+1);
  316. if (info->read_count < 1)
  317. info->read_count =
  318. (int)(info->fullnonce * TIME_FACTOR) - 1;
  319. info->timing_mode = MODE_DEFAULT;
  320. info->do_avalon_timing = false;
  321. }
  322. info->min_data_count = MIN_DATA_COUNT;
  323. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  324. avalon->device_id, timing_mode_str(info->timing_mode),
  325. info->read_count, info->Hs);
  326. }
  327. static uint32_t mask(int work_division)
  328. {
  329. char err_buf[BUFSIZ+1];
  330. uint32_t nonce_mask = 0x7fffffff;
  331. switch (work_division) {
  332. case 1:
  333. nonce_mask = 0xffffffff;
  334. break;
  335. case 2:
  336. nonce_mask = 0x7fffffff;
  337. break;
  338. case 4:
  339. nonce_mask = 0x3fffffff;
  340. break;
  341. case 8:
  342. nonce_mask = 0x1fffffff;
  343. break;
  344. default:
  345. sprintf(err_buf,
  346. "Invalid2 avalon-options for work_division (%d)"
  347. " must be 1, 2, 4 or 8", work_division);
  348. quit(1, err_buf);
  349. }
  350. return nonce_mask;
  351. }
  352. static void get_options(int this_option_offset, int *baud, int *work_division,
  353. int *asic_count)
  354. {
  355. char err_buf[BUFSIZ+1];
  356. char buf[BUFSIZ+1];
  357. char *ptr, *comma, *colon, *colon2;
  358. size_t max;
  359. int i, tmp;
  360. if (opt_icarus_options == NULL)
  361. buf[0] = '\0';
  362. else {
  363. ptr = opt_icarus_options;
  364. for (i = 0; i < this_option_offset; i++) {
  365. comma = strchr(ptr, ',');
  366. if (comma == NULL)
  367. break;
  368. ptr = comma + 1;
  369. }
  370. comma = strchr(ptr, ',');
  371. if (comma == NULL)
  372. max = strlen(ptr);
  373. else
  374. max = comma - ptr;
  375. if (max > BUFSIZ)
  376. max = BUFSIZ;
  377. strncpy(buf, ptr, max);
  378. buf[max] = '\0';
  379. }
  380. *baud = AVALON_IO_SPEED;
  381. *work_division = 2;
  382. *asic_count = 2;
  383. if (*buf) {
  384. colon = strchr(buf, ':');
  385. if (colon)
  386. *(colon++) = '\0';
  387. if (*buf) {
  388. tmp = atoi(buf);
  389. switch (tmp) {
  390. case 115200:
  391. *baud = 115200;
  392. break;
  393. case 57600:
  394. *baud = 57600;
  395. break;
  396. default:
  397. sprintf(err_buf,
  398. "Invalid avalon-options for baud (%s) "
  399. "must be 115200 or 57600", buf);
  400. quit(1, err_buf);
  401. }
  402. }
  403. if (colon && *colon) {
  404. colon2 = strchr(colon, ':');
  405. if (colon2)
  406. *(colon2++) = '\0';
  407. if (*colon) {
  408. tmp = atoi(colon);
  409. if (tmp == 1 || tmp == 2 ||
  410. tmp == 4 || tmp == 8) {
  411. *work_division = tmp;
  412. *asic_count = tmp;
  413. } else {
  414. sprintf(err_buf,
  415. "Invalid avalon-options for "
  416. "work_division (%s) must be 1,"
  417. " 2, 4 or 8", colon);
  418. quit(1, err_buf);
  419. }
  420. }
  421. if (colon2 && *colon2) {
  422. tmp = atoi(colon2);
  423. if (tmp > 0 && tmp <= *work_division)
  424. *asic_count = tmp;
  425. else {
  426. sprintf(err_buf,
  427. "Invalid avalon-options for "
  428. "asic_count (%s) must be >0 "
  429. "and <=work_division (%d)",
  430. colon2, *work_division);
  431. quit(1, err_buf);
  432. }
  433. }
  434. }
  435. }
  436. }
  437. static bool avalon_detect_one(const char *devpath)
  438. {
  439. struct AVALON_INFO *info;
  440. int fd, ret;
  441. int baud, work_division, asic_count;
  442. int this_option_offset = ++option_offset;
  443. get_options(this_option_offset, &baud, &work_division, &asic_count);
  444. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  445. fd = avalon_open2(devpath, baud, true);
  446. if (unlikely(fd == -1)) {
  447. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  448. return false;
  449. }
  450. ret = avalon_reset(fd);
  451. avalon_close(fd);
  452. if (ret)
  453. return false;
  454. /* We have a real Avalon! */
  455. struct cgpu_info *avalon;
  456. avalon = calloc(1, sizeof(struct cgpu_info));
  457. avalon->api = &avalon_api;
  458. avalon->device_path = strdup(devpath);
  459. avalon->device_fd = -1;
  460. avalon->threads = AVALON_MINER_THREADS;
  461. add_cgpu(avalon);
  462. avalon_info = realloc(avalon_info,
  463. sizeof(struct AVALON_INFO *) *
  464. (total_devices + 1));
  465. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  466. devpath, avalon->device_id);
  467. applog(LOG_DEBUG,
  468. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  469. avalon->device_id, baud, work_division, asic_count);
  470. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  471. malloc(sizeof(struct AVALON_INFO));
  472. if (unlikely(!(avalon_info[avalon->device_id])))
  473. quit(1, "Failed to malloc AVALON_INFO");
  474. info = avalon_info[avalon->device_id];
  475. memset(info, 0, sizeof(struct AVALON_INFO));
  476. info->baud = baud;
  477. info->work_division = work_division;
  478. info->asic_count = asic_count;
  479. info->nonce_mask = mask(work_division);
  480. set_timing_mode(this_option_offset, avalon);
  481. return true;
  482. }
  483. static inline void avalon_detect()
  484. {
  485. serial_detect(&avalon_api, avalon_detect_one);
  486. }
  487. static bool avalon_prepare(struct thr_info *thr)
  488. {
  489. struct cgpu_info *avalon = thr->cgpu;
  490. struct timeval now;
  491. int fd;
  492. avalon->device_fd = -1;
  493. fd = avalon_open(avalon->device_path,
  494. avalon_info[avalon->device_id]->baud);
  495. if (unlikely(fd == -1)) {
  496. applog(LOG_ERR, "Avalon: Failed to open on %s",
  497. avalon->device_path);
  498. return false;
  499. }
  500. avalon_reset(fd);
  501. avalon->device_fd = fd;
  502. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  503. gettimeofday(&now, NULL);
  504. get_datestamp(avalon->init, &now);
  505. return true;
  506. }
  507. static void avalon_free_work(struct work **work)
  508. {
  509. int i;
  510. if (!work)
  511. return;
  512. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  513. if (work[i])
  514. free_work(work[i++]);
  515. }
  516. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  517. __maybe_unused int64_t max_nonce)
  518. {
  519. struct cgpu_info *avalon;
  520. int fd;
  521. int ret;
  522. int full;
  523. struct AVALON_INFO *info;
  524. struct avalon_task at;
  525. struct avalon_result ar;
  526. static struct work *bulk0[3] = {NULL, NULL, NULL};
  527. static struct work *bulk1[3] = {NULL, NULL, NULL};
  528. static struct work *bulk2[3] = {NULL, NULL, NULL};
  529. struct work **work = NULL;
  530. int i, work_i0, work_i1, work_i2;
  531. uint32_t nonce;
  532. int64_t hash_count;
  533. int read_count;
  534. int count;
  535. struct timeval tv_start, tv_finish, elapsed;
  536. struct timeval tv_history_start, tv_history_finish;
  537. double Ti, Xi;
  538. int curr_hw_errors;
  539. bool was_hw_error;
  540. struct AVALON_HISTORY *history0, *history;
  541. double Hs, W, fullnonce;
  542. int64_t estimate_hashes;
  543. uint32_t values;
  544. int64_t hash_count_range;
  545. avalon = thr->cgpu;
  546. info = avalon_info[avalon->device_id];
  547. if (avalon->device_fd == -1)
  548. if (!avalon_prepare(thr)) {
  549. applog(LOG_ERR, "AVA%i: Comms error",
  550. avalon->device_id);
  551. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  552. /* fail the device if the reopen attempt fails */
  553. return -1;
  554. }
  555. fd = avalon->device_fd;
  556. #ifndef WIN32
  557. tcflush(fd, TCOFLUSH);
  558. #endif
  559. work = bulk_work;
  560. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  561. bulk0[i] = bulk1[i];
  562. bulk1[i] = bulk2[i];
  563. bulk2[i] = bulk_work[i];
  564. }
  565. i = 0;
  566. while (true) {
  567. avalon_init_default_task(&at);
  568. avalon_create_task(&at, work[i]);
  569. ret = avalon_send_task(fd, &at);
  570. if (ret == AVA_SEND_ERROR) {
  571. avalon_free_work(bulk0);
  572. avalon_free_work(bulk1);
  573. avalon_free_work(bulk2);
  574. do_avalon_close(thr);
  575. applog(LOG_ERR, "AVA%i: Comms error",
  576. avalon->device_id);
  577. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  578. return 0; /* This should never happen */
  579. }
  580. work[i]->blk.nonce = 0xffffffff;
  581. if (ret == AVA_SEND_BUFFER_FULL)
  582. break;
  583. i++;
  584. if (i == AVALON_GET_WORK_COUNT &&
  585. ret != AVA_SEND_BUFFER_FULL) {
  586. return 0xffffffff;
  587. }
  588. }
  589. elapsed.tv_sec = elapsed.tv_usec = 0;
  590. gettimeofday(&tv_start, NULL);
  591. /* count may != AVALON_GET_WORK_COUNT */
  592. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  593. work_i0 = work_i1 = work_i2 = -1;
  594. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  595. if (ret == AVA_GETS_ERROR) {
  596. avalon_free_work(bulk0);
  597. avalon_free_work(bulk1);
  598. avalon_free_work(bulk2);
  599. do_avalon_close(thr);
  600. applog(LOG_ERR,
  601. "AVA%i: Comms error", avalon->device_id);
  602. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  603. return 0;
  604. }
  605. /* aborted before becoming idle, get new work */
  606. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  607. timersub(&tv_finish, &tv_start, &elapsed);
  608. estimate_hashes = ((double)(elapsed.tv_sec) +
  609. ((double)(elapsed.tv_usec)) /
  610. ((double)1000000)) / info->Hs;
  611. /* If Serial-USB delay allowed the full nonce range to
  612. * complete it can't have done more than a full nonce
  613. */
  614. if (unlikely(estimate_hashes > 0xffffffff))
  615. estimate_hashes = 0xffffffff;
  616. applog(LOG_DEBUG,
  617. "Avalon: no nonce = 0x%08llx hashes "
  618. "(%ld.%06lds)",
  619. estimate_hashes, elapsed.tv_sec,
  620. elapsed.tv_usec);
  621. continue;
  622. //return estimate_hashes;
  623. }
  624. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  625. if (work_i0 < 0)
  626. applog(LOG_DEBUG,
  627. "Avalon: can not match nonce to bulk0");
  628. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  629. if (work_i1 < 0)
  630. applog(LOG_DEBUG,
  631. "Avalon: can not match nonce to bulk1");
  632. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  633. if (work_i2 < 0)
  634. applog(LOG_DEBUG,
  635. "Avalon: can not match nonce to bulk2");
  636. curr_hw_errors = avalon->hw_errors;
  637. if (work_i0 >= 0)
  638. submit_nonce(thr, bulk0[work_i0], nonce);
  639. if (work_i1 >= 0)
  640. submit_nonce(thr, bulk1[work_i1], nonce);
  641. if (work_i2 >= 0)
  642. submit_nonce(thr, bulk2[work_i2], nonce);
  643. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  644. /* Force a USB close/reopen on any hw error */
  645. if (was_hw_error)
  646. do_avalon_close(thr);
  647. hash_count = (nonce & info->nonce_mask);
  648. hash_count++;
  649. hash_count *= info->asic_count;
  650. full = avalon_buffer_full(fd);
  651. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  652. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  653. if (full == AVA_BUFFER_EMPTY) {
  654. applog(LOG_DEBUG, "Avalon: Finished bulk task!");
  655. avalon_free_work(bulk0);
  656. break;
  657. }
  658. }
  659. avalon_free_work(bulk0);
  660. if (opt_debug || info->do_avalon_timing)
  661. timersub(&tv_finish, &tv_start, &elapsed);
  662. if (opt_debug) {
  663. applog(LOG_DEBUG,
  664. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  665. "(%ld.%06lds)",
  666. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  667. }
  668. /* ignore possible end condition values ... and hw errors */
  669. if (info->do_avalon_timing
  670. && !was_hw_error
  671. && ((nonce & info->nonce_mask) > END_CONDITION)
  672. && ((nonce & info->nonce_mask) <
  673. (info->nonce_mask & ~END_CONDITION))) {
  674. gettimeofday(&tv_history_start, NULL);
  675. history0 = &(info->history[0]);
  676. if (history0->values == 0)
  677. timeradd(&tv_start, &history_sec, &(history0->finish));
  678. Ti = (double)(elapsed.tv_sec)
  679. + ((double)(elapsed.tv_usec))/((double)1000000)
  680. - ((double)AVALON_READ_TIME(info->baud));
  681. Xi = (double)hash_count;
  682. history0->sumXiTi += Xi * Ti;
  683. history0->sumXi += Xi;
  684. history0->sumTi += Ti;
  685. history0->sumXi2 += Xi * Xi;
  686. history0->values++;
  687. if (history0->hash_count_max < hash_count)
  688. history0->hash_count_max = hash_count;
  689. if (history0->hash_count_min > hash_count ||
  690. history0->hash_count_min == 0)
  691. history0->hash_count_min = hash_count;
  692. if (history0->values >= info->min_data_count
  693. && timercmp(&tv_start, &(history0->finish), >)) {
  694. for (i = INFO_HISTORY; i > 0; i--)
  695. memcpy(&(info->history[i]),
  696. &(info->history[i-1]),
  697. sizeof(struct AVALON_HISTORY));
  698. /* Init history0 to zero for summary calculation */
  699. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  700. /* We just completed a history data set
  701. * So now recalc read_count based on the
  702. * whole history thus we will
  703. * initially get more accurate until it
  704. * completes INFO_HISTORY
  705. * total data sets */
  706. count = 0;
  707. for (i = 1 ; i <= INFO_HISTORY; i++) {
  708. history = &(info->history[i]);
  709. if (history->values >= MIN_DATA_COUNT) {
  710. count++;
  711. history0->sumXiTi += history->sumXiTi;
  712. history0->sumXi += history->sumXi;
  713. history0->sumTi += history->sumTi;
  714. history0->sumXi2 += history->sumXi2;
  715. history0->values += history->values;
  716. if (history0->hash_count_max < history->hash_count_max)
  717. history0->hash_count_max = history->hash_count_max;
  718. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  719. history0->hash_count_min = history->hash_count_min;
  720. }
  721. }
  722. /* All history data */
  723. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  724. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  725. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  726. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  727. values = history0->values;
  728. /* Initialise history0 to zero for next data set */
  729. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  730. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  731. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  732. info->Hs = Hs;
  733. info->read_count = read_count;
  734. info->fullnonce = fullnonce;
  735. info->count = count;
  736. info->W = W;
  737. info->values = values;
  738. info->hash_count_range = hash_count_range;
  739. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  740. info->min_data_count *= 2;
  741. else if (info->timing_mode == MODE_SHORT)
  742. info->do_avalon_timing = false;
  743. /* applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);*/
  744. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  745. avalon->device_id, Hs, W, read_count, fullnonce);
  746. }
  747. info->history_count++;
  748. gettimeofday(&tv_history_finish, NULL);
  749. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  750. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  751. }
  752. return hash_count;
  753. }
  754. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  755. {
  756. struct api_data *root = NULL;
  757. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  758. /* Warning, access to these is not locked - but we don't really
  759. * care since hashing performance is way more important than
  760. * locking access to displaying API debug 'stats'
  761. * If locking becomes an issue for any of them, use copy_data=true also */
  762. root = api_add_int(root, "read_count", &(info->read_count), false);
  763. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  764. root = api_add_int(root, "count", &(info->count), false);
  765. root = api_add_hs(root, "Hs", &(info->Hs), false);
  766. root = api_add_double(root, "W", &(info->W), false);
  767. root = api_add_uint(root, "total_values", &(info->values), false);
  768. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  769. root = api_add_uint64(root, "history_count", &(info->history_count),
  770. false);
  771. root = api_add_timeval(root, "history_time", &(info->history_time),
  772. false);
  773. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  774. false);
  775. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  776. false);
  777. root = api_add_const(root, "timing_mode",
  778. timing_mode_str(info->timing_mode), false);
  779. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  780. false);
  781. root = api_add_int(root, "baud", &(info->baud), false);
  782. root = api_add_int(root, "work_division", &(info->work_division),
  783. false);
  784. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  785. return root;
  786. }
  787. static void avalon_shutdown(struct thr_info *thr)
  788. {
  789. do_avalon_close(thr);
  790. }
  791. struct device_api avalon_api = {
  792. .dname = "avalon",
  793. .name = "AVA",
  794. .api_detect = avalon_detect,
  795. .thread_prepare = avalon_prepare,
  796. .scanhash_queue = avalon_scanhash,
  797. .get_api_stats = avalon_api_stats,
  798. .thread_shutdown = avalon_shutdown,
  799. };