driver-avalon.c 24 KB

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  1. /*
  2. * Copyright 2013 Avalon project
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 3 of the License, or (at your option)
  7. * any later version. See COPYING for more details.
  8. */
  9. #include "config.h"
  10. #include <limits.h>
  11. #include <pthread.h>
  12. #include <stdio.h>
  13. #include <sys/time.h>
  14. #include <sys/types.h>
  15. #include <dirent.h>
  16. #include <unistd.h>
  17. #ifndef WIN32
  18. #include <termios.h>
  19. #include <sys/stat.h>
  20. #include <fcntl.h>
  21. #ifndef O_CLOEXEC
  22. #define O_CLOEXEC 0
  23. #endif
  24. #else
  25. #include <windows.h>
  26. #include <io.h>
  27. #endif
  28. #include "elist.h"
  29. #include "miner.h"
  30. #include "fpgautils.h"
  31. #include "driver-avalon.h"
  32. #include "hexdump.c"
  33. static int option_offset = -1;
  34. struct avalon_info **avalon_info;
  35. struct device_api avalon_api;
  36. static inline uint8_t rev8(uint8_t d)
  37. {
  38. int i;
  39. uint8_t out = 0;
  40. /* (from left to right) */
  41. for (i = 0; i < 8; i++)
  42. if (d & (1 << i))
  43. out |= (1 << (7 - i));
  44. return out;
  45. }
  46. static int avalon_init_task(struct avalon_task *at,
  47. uint8_t reset, uint8_t ff, uint8_t fan,
  48. uint8_t timeout, uint8_t asic_num,
  49. uint8_t miner_num, uint8_t nonce_elf)
  50. {
  51. static bool first = true;
  52. if (unlikely(!at))
  53. return -1;
  54. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  55. return -1;
  56. memset(at, 0, sizeof(struct avalon_task));
  57. if (unlikely(reset)) {
  58. at->reset = 1;
  59. at->fan_eft = 1;
  60. at->timer_eft = 1;
  61. first = true;
  62. }
  63. at->flush_fifo = (ff ? 1 : 0);
  64. at->fan_eft = (fan ? 1 : 0);
  65. if (unlikely(first && !at->reset)) {
  66. at->fan_eft = 1;
  67. at->timer_eft = 1;
  68. first = false;
  69. }
  70. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  71. at->timeout_data = timeout;
  72. at->asic_num = asic_num;
  73. at->miner_num = miner_num;
  74. at->nonce_elf = nonce_elf;
  75. return 0;
  76. }
  77. static inline void avalon_create_task(struct avalon_task *at,
  78. struct work *work)
  79. {
  80. memcpy(at->midstate, work->midstate, 32);
  81. memcpy(at->data, work->data + 64, 12);
  82. }
  83. static int avalon_send_task(int fd, const struct avalon_task *at,
  84. struct thr_info *thr)
  85. {
  86. size_t ret;
  87. int full;
  88. struct timespec p;
  89. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  90. size_t nr_len;
  91. struct cgpu_info *avalon;
  92. struct avalon_info *info;
  93. uint64_t delay = 32000000; /* Default 32ms for B19200 */
  94. uint32_t nonce_range;
  95. int i;
  96. if (at->nonce_elf)
  97. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  98. else
  99. nr_len = AVALON_WRITE_SIZE;
  100. memcpy(buf, at, AVALON_WRITE_SIZE);
  101. if (at->nonce_elf) {
  102. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  103. for (i = 0; i < at->asic_num; i++) {
  104. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  105. (i * nonce_range & 0xff000000) >> 24;
  106. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  107. (i * nonce_range & 0x00ff0000) >> 16;
  108. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  109. (i * nonce_range & 0x0000ff00) >> 8;
  110. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  111. (i * nonce_range & 0x000000ff) >> 0;
  112. }
  113. }
  114. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  115. uint8_t tt = 0;
  116. tt = (buf[0] & 0x0f) << 4;
  117. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  118. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  119. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  120. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  121. buf[0] = tt;
  122. buf[4] = rev8(buf[4]);
  123. #endif
  124. if (likely(thr)) {
  125. avalon = thr->cgpu;
  126. info = avalon_info[avalon->device_id];
  127. delay = nr_len * 10 * 1000000000ULL;
  128. delay = delay / info->baud;
  129. if (info->frequency == 256) {
  130. buf[4] = 0x07;
  131. buf[5] = 0x00;
  132. buf[6] = 0x03;
  133. buf[7] = 0x08;
  134. buf[8] = 0x74;
  135. buf[9] = 0x01;
  136. buf[10] = 0x00;
  137. buf[11] = 0x00;
  138. }
  139. if (info->frequency == 270) {
  140. buf[4] = 0x07;
  141. buf[5] = 0x00;
  142. buf[6] = 0x73;
  143. buf[7] = 0x08;
  144. buf[8] = 0x74;
  145. buf[9] = 0x01;
  146. buf[10] = 0x00;
  147. buf[11] = 0x00;
  148. }
  149. if (info->frequency == 282) {
  150. buf[4] = 0x07;
  151. buf[5] = 0x00;
  152. buf[6] = 0xd3;
  153. buf[7] = 0x08;
  154. buf[8] = 0x74;
  155. buf[9] = 0x01;
  156. buf[10] = 0x00;
  157. buf[11] = 0x00;
  158. }
  159. if (info->frequency == 300) {
  160. buf[4] = 0x07;
  161. buf[5] = 0x00;
  162. buf[6] = 0x63;
  163. buf[7] = 0x09;
  164. buf[8] = 0x74;
  165. buf[9] = 0x01;
  166. buf[10] = 0x00;
  167. buf[11] = 0x00;
  168. }
  169. }
  170. if (at->reset)
  171. nr_len = 1;
  172. if (opt_debug) {
  173. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  174. hexdump((uint8_t *)buf, nr_len);
  175. }
  176. ret = write(fd, buf, nr_len);
  177. if (unlikely(ret != nr_len))
  178. return AVA_SEND_ERROR;
  179. p.tv_sec = 0;
  180. p.tv_nsec = (long)delay + 4000000;
  181. nanosleep(&p, NULL);
  182. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %ld", p.tv_nsec);
  183. full = avalon_buffer_full(fd);
  184. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  185. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  186. if (unlikely(full == AVA_BUFFER_FULL))
  187. return AVA_SEND_BUFFER_FULL;
  188. return AVA_SEND_BUFFER_EMPTY;
  189. }
  190. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  191. struct thr_info *thr, struct timeval *tv_finish)
  192. {
  193. ssize_t ret = 0;
  194. int rc = 0;
  195. int read_amount = AVALON_READ_SIZE;
  196. bool first = true;
  197. /* Read reply 1 byte at a time to get earliest tv_finish */
  198. while (true) {
  199. ret = read(fd, buf, 1);
  200. if (ret < 0)
  201. return AVA_GETS_ERROR;
  202. if (first && tv_finish != NULL)
  203. gettimeofday(tv_finish, NULL);
  204. if (ret >= read_amount)
  205. return AVA_GETS_OK;
  206. if (ret > 0) {
  207. buf += ret;
  208. read_amount -= ret;
  209. first = false;
  210. continue;
  211. }
  212. rc++;
  213. if (rc >= read_count) {
  214. if (opt_debug) {
  215. applog(LOG_WARNING,
  216. "Avalon: No data in %.2f seconds",
  217. (float)rc/(float)AVALON_TIME_FACTOR);
  218. }
  219. return AVA_GETS_TIMEOUT;
  220. }
  221. if (thr && thr->work_restart) {
  222. if (opt_debug) {
  223. applog(LOG_WARNING,
  224. "Avalon: Work restart at %.2f seconds",
  225. (float)(rc)/(float)AVALON_TIME_FACTOR);
  226. }
  227. return AVA_GETS_RESTART;
  228. }
  229. }
  230. }
  231. static int avalon_get_result(int fd, struct avalon_result *ar,
  232. struct thr_info *thr, struct timeval *tv_finish)
  233. {
  234. struct cgpu_info *avalon;
  235. struct avalon_info *info;
  236. uint8_t result[AVALON_READ_SIZE];
  237. int ret, read_count = AVALON_RESET_FAULT_DECISECONDS * AVALON_TIME_FACTOR;
  238. if (likely(thr)) {
  239. avalon = thr->cgpu;
  240. info = avalon_info[avalon->device_id];
  241. read_count = info->read_count;
  242. }
  243. memset(result, 0, AVALON_READ_SIZE);
  244. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  245. if (ret == AVA_GETS_OK) {
  246. if (opt_debug) {
  247. applog(LOG_DEBUG, "Avalon: get:");
  248. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  249. }
  250. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  251. }
  252. return ret;
  253. }
  254. static int avalon_decode_nonce(struct thr_info *thr, struct work **work,
  255. struct avalon_result *ar, uint32_t *nonce)
  256. {
  257. struct cgpu_info *avalon;
  258. struct avalon_info *info;
  259. int avalon_get_work_count, i;
  260. if (unlikely(!work))
  261. return -1;
  262. avalon = thr->cgpu;
  263. info = avalon_info[avalon->device_id];
  264. avalon_get_work_count = info->miner_count;
  265. for (i = 0; i < avalon_get_work_count; i++) {
  266. if (work[i] &&
  267. !memcmp(ar->data, work[i]->data + 64, 12) &&
  268. !memcmp(ar->midstate, work[i]->midstate, 32))
  269. break;
  270. }
  271. if (i == avalon_get_work_count)
  272. return -1;
  273. ++info->matching_work[i];
  274. *nonce = ar->nonce;
  275. #if defined (__BIG_ENDIAN__) || defined(MIPSEB)
  276. *nonce = swab32(*nonce);
  277. #endif
  278. applog(LOG_DEBUG, "Avalon: match to work[%d](%p): %d",i, work[i],
  279. info->matching_work[i]);
  280. return i;
  281. }
  282. static int avalon_reset(int fd, struct avalon_result *ar)
  283. {
  284. struct avalon_task at;
  285. uint8_t *buf;
  286. int ret, i = 0;
  287. struct timespec p;
  288. avalon_init_task(&at, 1, 0,
  289. AVALON_DEFAULT_FAN_PWM,
  290. AVALON_DEFAULT_TIMEOUT,
  291. AVALON_DEFAULT_ASIC_NUM,
  292. AVALON_DEFAULT_MINER_NUM,
  293. 0);
  294. ret = avalon_send_task(fd, &at, NULL);
  295. if (ret == AVA_SEND_ERROR)
  296. return 1;
  297. avalon_get_result(fd, ar, NULL, NULL);
  298. buf = (uint8_t *)ar;
  299. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  300. buf[2] == 0xAA && buf[3] == 0x55) {
  301. for (i = 4; i < 11; i++)
  302. if (buf[i] != 0)
  303. break;
  304. }
  305. if (i != 11) {
  306. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?"
  307. " (%d: %02x %02x %02x %02x)",
  308. i, buf[0], buf[1], buf[2], buf[3]);
  309. /* FIXME: return 1; */
  310. }
  311. p.tv_sec = 1;
  312. p.tv_nsec = AVALON_RESET_PITCH;
  313. nanosleep(&p, NULL);
  314. applog(LOG_WARNING, "Avalon: Reset succeeded");
  315. return 0;
  316. }
  317. static void get_options(int this_option_offset, int *baud, int *miner_count,
  318. int *asic_count, int *timeout, int *frequency)
  319. {
  320. char err_buf[BUFSIZ+1];
  321. char buf[BUFSIZ+1];
  322. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  323. size_t max;
  324. int i, tmp;
  325. if (opt_avalon_options == NULL)
  326. buf[0] = '\0';
  327. else {
  328. ptr = opt_avalon_options;
  329. for (i = 0; i < this_option_offset; i++) {
  330. comma = strchr(ptr, ',');
  331. if (comma == NULL)
  332. break;
  333. ptr = comma + 1;
  334. }
  335. comma = strchr(ptr, ',');
  336. if (comma == NULL)
  337. max = strlen(ptr);
  338. else
  339. max = comma - ptr;
  340. if (max > BUFSIZ)
  341. max = BUFSIZ;
  342. strncpy(buf, ptr, max);
  343. buf[max] = '\0';
  344. }
  345. *baud = AVALON_IO_SPEED;
  346. *miner_count = AVALON_DEFAULT_MINER_NUM;
  347. *asic_count = AVALON_DEFAULT_ASIC_NUM;
  348. *timeout = AVALON_DEFAULT_TIMEOUT;
  349. if (!(*buf))
  350. return;
  351. colon = strchr(buf, ':');
  352. if (colon)
  353. *(colon++) = '\0';
  354. tmp = atoi(buf);
  355. switch (tmp) {
  356. case 115200:
  357. *baud = 115200;
  358. break;
  359. case 57600:
  360. *baud = 57600;
  361. break;
  362. case 38400:
  363. *baud = 38400;
  364. break;
  365. case 19200:
  366. *baud = 19200;
  367. break;
  368. default:
  369. sprintf(err_buf,
  370. "Invalid avalon-options for baud (%s) "
  371. "must be 115200, 57600, 38400 or 19200", buf);
  372. quit(1, err_buf);
  373. }
  374. if (colon && *colon) {
  375. colon2 = strchr(colon, ':');
  376. if (colon2)
  377. *(colon2++) = '\0';
  378. if (*colon) {
  379. tmp = atoi(colon);
  380. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  381. *miner_count = tmp;
  382. } else {
  383. sprintf(err_buf,
  384. "Invalid avalon-options for "
  385. "miner_count (%s) must be 1 ~ %d",
  386. colon, AVALON_DEFAULT_MINER_NUM);
  387. quit(1, err_buf);
  388. }
  389. }
  390. if (colon2 && *colon2) {
  391. colon3 = strchr(colon2, ':');
  392. if (colon3)
  393. *(colon3++) = '\0';
  394. tmp = atoi(colon2);
  395. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  396. *asic_count = tmp;
  397. else {
  398. sprintf(err_buf,
  399. "Invalid avalon-options for "
  400. "asic_count (%s) must be 1 ~ %d",
  401. colon2, AVALON_DEFAULT_ASIC_NUM);
  402. quit(1, err_buf);
  403. }
  404. if (colon3 && *colon3) {
  405. colon4 = strchr(colon3, ':');
  406. if (colon4)
  407. *(colon4++) = '\0';
  408. tmp = atoi(colon3);
  409. if (tmp > 0 && tmp <= 0xff)
  410. *timeout = tmp;
  411. else {
  412. sprintf(err_buf,
  413. "Invalid avalon-options for "
  414. "timeout (%s) must be 1 ~ %d",
  415. colon3, 0xff);
  416. quit(1, err_buf);
  417. }
  418. if (colon4 && *colon4) {
  419. tmp = atoi(colon4);
  420. switch (tmp) {
  421. case 256:
  422. case 270:
  423. case 282:
  424. case 300:
  425. *frequency = tmp;
  426. break;
  427. default:
  428. sprintf(err_buf,
  429. "Invalid avalon-options for "
  430. "frequency must be 256/270/282/300");
  431. quit(1, err_buf);
  432. }
  433. }
  434. }
  435. }
  436. }
  437. }
  438. static bool avalon_detect_one(const char *devpath)
  439. {
  440. struct avalon_info *info;
  441. struct avalon_result ar;
  442. int fd, ret;
  443. int baud, miner_count, asic_count, timeout, frequency = 0;
  444. int this_option_offset = ++option_offset;
  445. get_options(this_option_offset, &baud, &miner_count, &asic_count,
  446. &timeout, &frequency);
  447. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s "
  448. "(baud=%d miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  449. devpath, baud, miner_count, asic_count, timeout, frequency);
  450. fd = avalon_open2(devpath, baud, true);
  451. if (unlikely(fd == -1)) {
  452. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  453. return false;
  454. }
  455. ret = avalon_reset(fd, &ar);
  456. avalon_close(fd);
  457. if (ret) {
  458. ; /* FIXME: I think IT IS avalon and wait on reset; return false; */
  459. }
  460. /* We have a real Avalon! */
  461. struct cgpu_info *avalon;
  462. avalon = calloc(1, sizeof(struct cgpu_info));
  463. avalon->api = &avalon_api;
  464. avalon->device_path = strdup(devpath);
  465. avalon->device_fd = -1;
  466. avalon->threads = AVALON_MINER_THREADS;
  467. add_cgpu(avalon);
  468. avalon_info = realloc(avalon_info,
  469. sizeof(struct avalon_info *) *
  470. (total_devices + 1));
  471. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  472. devpath, avalon->device_id);
  473. avalon_info[avalon->device_id] = (struct avalon_info *)
  474. malloc(sizeof(struct avalon_info));
  475. if (unlikely(!(avalon_info[avalon->device_id])))
  476. quit(1, "Failed to malloc avalon_info");
  477. info = avalon_info[avalon->device_id];
  478. memset(info, 0, sizeof(struct avalon_info));
  479. info->baud = baud;
  480. info->miner_count = miner_count;
  481. info->asic_count = asic_count;
  482. info->timeout = timeout;
  483. info->read_count = ((float)info->timeout * AVALON_HASH_TIME_FACTOR *
  484. AVALON_TIME_FACTOR) / (float)info->miner_count;
  485. info->fan_pwm = AVALON_DEFAULT_FAN_PWM;
  486. info->temp_max = 0;
  487. info->temp_history_count = (4 / (float)(0x3c * ((float)1.67/0x32))) + 1;
  488. if (info->temp_history_count <= 0)
  489. info->temp_history_count = 1;
  490. info->temp_history_index = 0;
  491. info->temp_sum = 0;
  492. info->temp_old = 0;
  493. info->frequency = frequency;
  494. return true;
  495. }
  496. static inline void avalon_detect()
  497. {
  498. serial_detect(&avalon_api, avalon_detect_one);
  499. }
  500. static bool avalon_prepare(struct thr_info *thr)
  501. {
  502. struct avalon_result ar;
  503. struct cgpu_info *avalon = thr->cgpu;
  504. struct timeval now;
  505. int fd, ret;
  506. avalon->device_fd = -1;
  507. fd = avalon_open(avalon->device_path,
  508. avalon_info[avalon->device_id]->baud);
  509. if (unlikely(fd == -1)) {
  510. applog(LOG_ERR, "Avalon: Failed to open on %s",
  511. avalon->device_path);
  512. return false;
  513. }
  514. ret = avalon_reset(fd, &ar);
  515. if (ret)
  516. return false;
  517. avalon->device_fd = fd;
  518. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  519. gettimeofday(&now, NULL);
  520. get_datestamp(avalon->init, &now);
  521. return true;
  522. }
  523. static void avalon_free_work(struct thr_info *thr, struct work **work)
  524. {
  525. struct cgpu_info *avalon;
  526. struct avalon_info *info;
  527. int i;
  528. if (unlikely(!work))
  529. return;
  530. avalon = thr->cgpu;
  531. info = avalon_info[avalon->device_id];
  532. for (i = 0; i < info->miner_count; i++)
  533. if (likely(work[i])) {
  534. free_work(work[i]);
  535. work[i] = NULL;
  536. }
  537. }
  538. static void do_avalon_close(struct thr_info *thr)
  539. {
  540. struct cgpu_info *avalon = thr->cgpu;
  541. struct avalon_info *info = avalon_info[avalon->device_id];
  542. avalon_close(avalon->device_fd);
  543. avalon->device_fd = -1;
  544. info->no_matching_work = 0;
  545. avalon_free_work(thr, info->bulk0);
  546. avalon_free_work(thr, info->bulk1);
  547. avalon_free_work(thr, info->bulk2);
  548. avalon_free_work(thr, info->bulk3);
  549. }
  550. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  551. {
  552. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  553. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  554. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  555. info->temp0 = ar->temp0;
  556. info->temp1 = ar->temp1;
  557. info->temp2 = ar->temp2;
  558. if (ar->temp0 & 0x80) {
  559. ar->temp0 &= 0x7f;
  560. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  561. }
  562. if (ar->temp1 & 0x80) {
  563. ar->temp1 &= 0x7f;
  564. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  565. }
  566. if (ar->temp2 & 0x80) {
  567. ar->temp2 &= 0x7f;
  568. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  569. }
  570. if (info->temp0 > info->temp_max)
  571. info->temp_max = info->temp0;
  572. if (info->temp1 > info->temp_max)
  573. info->temp_max = info->temp1;
  574. if (info->temp2 > info->temp_max)
  575. info->temp_max = info->temp2;
  576. *temp_avg = info->temp2;
  577. }
  578. static inline void adjust_temp(struct avalon_info *info)
  579. {
  580. int temp_new;
  581. temp_new = info->temp_sum / info->temp_history_count;
  582. if (temp_new < 40)
  583. info->fan_pwm = 0xA;
  584. else if (temp_new > 60)
  585. info->fan_pwm = AVALON_DEFAULT_FAN_PWM;
  586. else if (abs(temp_new - info->temp_old) >= 2) {
  587. info->fan_pwm = (temp_new - 40) * 9 + 10;
  588. info->temp_old = temp_new;
  589. }
  590. }
  591. static int64_t avalon_scanhash(struct thr_info *thr, struct work **work,
  592. __maybe_unused int64_t max_nonce)
  593. {
  594. struct cgpu_info *avalon;
  595. int fd, ret, full;
  596. struct avalon_info *info;
  597. struct avalon_task at;
  598. struct avalon_result ar;
  599. int i, work_i0, work_i1, work_i2, work_i3;
  600. int avalon_get_work_count;
  601. struct timeval tv_start, tv_finish, elapsed;
  602. uint32_t nonce;
  603. int64_t hash_count;
  604. static int first_try = 0;
  605. avalon = thr->cgpu;
  606. info = avalon_info[avalon->device_id];
  607. avalon_get_work_count = info->miner_count;
  608. if (unlikely(avalon->device_fd == -1))
  609. if (!avalon_prepare(thr)) {
  610. applog(LOG_ERR, "AVA%i: Comms error(open)",
  611. avalon->device_id);
  612. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  613. /* fail the device if the reopen attempt fails */
  614. return -1;
  615. }
  616. fd = avalon->device_fd;
  617. #ifndef WIN32
  618. tcflush(fd, TCOFLUSH);
  619. #endif
  620. for (i = 0; i < avalon_get_work_count; i++) {
  621. info->bulk0[i] = info->bulk1[i];
  622. info->bulk1[i] = info->bulk2[i];
  623. info->bulk2[i] = info->bulk3[i];
  624. info->bulk3[i] = work[i];
  625. applog(LOG_DEBUG, "Avalon: bulk0/1/2 buffer [%d]: %p, %p, %p, %p",
  626. i, info->bulk0[i], info->bulk1[i], info->bulk2[i], info->bulk3[i]);
  627. }
  628. i = 0;
  629. while (true) {
  630. avalon_init_task(&at, 0, 0, info->fan_pwm,
  631. info->timeout, info->asic_count,
  632. info->miner_count, 1);
  633. avalon_create_task(&at, work[i]);
  634. ret = avalon_send_task(fd, &at, thr);
  635. if (unlikely(ret == AVA_SEND_ERROR ||
  636. (ret == AVA_SEND_BUFFER_EMPTY &&
  637. (i + 1 == avalon_get_work_count) &&
  638. first_try))) {
  639. avalon_free_work(thr, info->bulk0);
  640. avalon_free_work(thr, info->bulk1);
  641. avalon_free_work(thr, info->bulk2);
  642. avalon_free_work(thr, info->bulk3);
  643. do_avalon_close(thr);
  644. applog(LOG_ERR, "AVA%i: Comms error(buffer)",
  645. avalon->device_id);
  646. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  647. first_try = 0;
  648. sleep(1);
  649. return 0; /* This should never happen */
  650. }
  651. if (ret == AVA_SEND_BUFFER_EMPTY && (i + 1 == avalon_get_work_count)) {
  652. first_try = 1;
  653. return 0xffffffff;
  654. }
  655. work[i]->blk.nonce = 0xffffffff;
  656. if (ret == AVA_SEND_BUFFER_FULL)
  657. break;
  658. i++;
  659. }
  660. if (unlikely(first_try))
  661. first_try = 0;
  662. elapsed.tv_sec = elapsed.tv_usec = 0;
  663. gettimeofday(&tv_start, NULL);
  664. hash_count = 0;
  665. while (true) {
  666. work_i0 = work_i1 = work_i2 = -1;
  667. full = avalon_buffer_full(fd);
  668. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  669. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  670. if (unlikely(full == AVA_BUFFER_EMPTY))
  671. break;
  672. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  673. if (unlikely(ret == AVA_GETS_ERROR)) {
  674. avalon_free_work(thr, info->bulk0);
  675. avalon_free_work(thr, info->bulk1);
  676. avalon_free_work(thr, info->bulk2);
  677. avalon_free_work(thr, info->bulk3);
  678. do_avalon_close(thr);
  679. applog(LOG_ERR,
  680. "AVA%i: Comms error(read)", avalon->device_id);
  681. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  682. return 0;
  683. }
  684. if (unlikely(ret == AVA_GETS_TIMEOUT)) {
  685. timersub(&tv_finish, &tv_start, &elapsed);
  686. applog(LOG_DEBUG, "Avalon: no nonce in (%ld.%06lds)",
  687. elapsed.tv_sec, elapsed.tv_usec);
  688. continue;
  689. }
  690. if (unlikely(ret == AVA_GETS_RESTART)) {
  691. avalon_free_work(thr, info->bulk0);
  692. avalon_free_work(thr, info->bulk1);
  693. avalon_free_work(thr, info->bulk2);
  694. avalon_free_work(thr, info->bulk3);
  695. continue;
  696. }
  697. record_temp_fan(info, &ar, &(avalon->temp));
  698. work_i0 = avalon_decode_nonce(thr, info->bulk0, &ar, &nonce);
  699. work_i1 = avalon_decode_nonce(thr, info->bulk1, &ar, &nonce);
  700. work_i2 = avalon_decode_nonce(thr, info->bulk2, &ar, &nonce);
  701. work_i3 = avalon_decode_nonce(thr, info->bulk3, &ar, &nonce);
  702. if ((work_i0 < 0) && (work_i1 < 0) && (work_i2 < 0) && (work_i3 < 0)) {
  703. if (opt_debug) {
  704. timersub(&tv_finish, &tv_start, &elapsed);
  705. applog(LOG_DEBUG,"Avalon: no matching work: %d"
  706. " (%ld.%06lds)", ++info->no_matching_work,
  707. elapsed.tv_sec, elapsed.tv_usec);
  708. }
  709. continue;
  710. }
  711. if (work_i0 >= 0)
  712. submit_nonce(thr, info->bulk0[work_i0], nonce);
  713. if (work_i1 >= 0)
  714. submit_nonce(thr, info->bulk1[work_i1], nonce);
  715. if (work_i2 >= 0)
  716. submit_nonce(thr, info->bulk2[work_i2], nonce);
  717. if (work_i3 >= 0)
  718. submit_nonce(thr, info->bulk3[work_i3], nonce);
  719. hash_count += nonce;
  720. if (opt_debug) {
  721. timersub(&tv_finish, &tv_start, &elapsed);
  722. applog(LOG_DEBUG,
  723. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  724. "(%ld.%06lds)", nonce, hash_count,
  725. elapsed.tv_sec, elapsed.tv_usec);
  726. }
  727. }
  728. avalon_free_work(thr, info->bulk0);
  729. applog(LOG_WARNING,
  730. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  731. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  732. info->fan0, info->fan1, info->fan2,
  733. info->temp0, info->temp1, info->temp2, info->temp_max);
  734. info->temp_history_index++;
  735. info->temp_sum += info->temp2;
  736. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  737. info->temp_history_index, info->temp_history_count, info->temp_old);
  738. if (info->temp_history_index == info->temp_history_count) {
  739. adjust_temp(info);
  740. info->temp_history_index = 0;
  741. info->temp_sum = 0;
  742. }
  743. /*
  744. * FIXME: Each work split to 10 pieces, each piece send to a
  745. * asic(256MHs). one work can be mulit-nonce back. it is not
  746. * easy calculate correct hash on such situation. so I simplely
  747. * add each nonce to hash_count. base on Utility/m hash_count*2
  748. * give a very good result.
  749. *
  750. * Any patch will be great.
  751. */
  752. return (hash_count * 2);
  753. }
  754. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  755. {
  756. struct api_data *root = NULL;
  757. struct avalon_info *info = avalon_info[cgpu->device_id];
  758. root = api_add_int(root, "read_count", &(info->read_count), false);
  759. root = api_add_int(root, "baud", &(info->baud), false);
  760. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  761. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  762. root = api_add_int(root, "fan1", &(info->fan0), false);
  763. root = api_add_int(root, "fan2", &(info->fan1), false);
  764. root = api_add_int(root, "fan3", &(info->fan2), false);
  765. root = api_add_int(root, "temp1", &(info->temp0), false);
  766. root = api_add_int(root, "temp2", &(info->temp1), false);
  767. root = api_add_int(root, "temp3", &(info->temp2), false);
  768. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  769. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  770. root = api_add_int(root, "matching_work_count1", &(info->matching_work[0]), false);
  771. root = api_add_int(root, "matching_work_count2", &(info->matching_work[1]), false);
  772. root = api_add_int(root, "matching_work_count3", &(info->matching_work[2]), false);
  773. root = api_add_int(root, "matching_work_count4", &(info->matching_work[3]), false);
  774. root = api_add_int(root, "matching_work_count5", &(info->matching_work[4]), false);
  775. root = api_add_int(root, "matching_work_count6", &(info->matching_work[5]), false);
  776. root = api_add_int(root, "matching_work_count7", &(info->matching_work[6]), false);
  777. root = api_add_int(root, "matching_work_count8", &(info->matching_work[7]), false);
  778. root = api_add_int(root, "matching_work_count9", &(info->matching_work[8]), false);
  779. root = api_add_int(root, "matching_work_count10", &(info->matching_work[9]), false);
  780. root = api_add_int(root, "matching_work_count11", &(info->matching_work[10]), false);
  781. root = api_add_int(root, "matching_work_count12", &(info->matching_work[11]), false);
  782. root = api_add_int(root, "matching_work_count13", &(info->matching_work[12]), false);
  783. root = api_add_int(root, "matching_work_count14", &(info->matching_work[13]), false);
  784. root = api_add_int(root, "matching_work_count15", &(info->matching_work[14]), false);
  785. root = api_add_int(root, "matching_work_count16", &(info->matching_work[15]), false);
  786. root = api_add_int(root, "matching_work_count17", &(info->matching_work[16]), false);
  787. root = api_add_int(root, "matching_work_count18", &(info->matching_work[17]), false);
  788. root = api_add_int(root, "matching_work_count19", &(info->matching_work[18]), false);
  789. root = api_add_int(root, "matching_work_count20", &(info->matching_work[19]), false);
  790. root = api_add_int(root, "matching_work_count21", &(info->matching_work[20]), false);
  791. root = api_add_int(root, "matching_work_count22", &(info->matching_work[21]), false);
  792. root = api_add_int(root, "matching_work_count23", &(info->matching_work[22]), false);
  793. root = api_add_int(root, "matching_work_count24", &(info->matching_work[23]), false);
  794. return root;
  795. }
  796. static void avalon_shutdown(struct thr_info *thr)
  797. {
  798. do_avalon_close(thr);
  799. }
  800. struct device_api avalon_api = {
  801. .dname = "avalon",
  802. .name = "AVA",
  803. .api_detect = avalon_detect,
  804. .thread_prepare = avalon_prepare,
  805. .scanhash_queue = avalon_scanhash,
  806. .get_api_stats = avalon_api_stats,
  807. .thread_shutdown = avalon_shutdown,
  808. };