driver-avalon.c 24 KB

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  1. /*
  2. * Copyright 2012 Luke Dashjr
  3. * Copyright 2012 2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Andrew Smith
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include "config.h"
  12. #include <limits.h>
  13. #include <pthread.h>
  14. #include <stdio.h>
  15. #include <sys/time.h>
  16. #include <sys/types.h>
  17. #include <dirent.h>
  18. #include <unistd.h>
  19. #ifndef WIN32
  20. #include <termios.h>
  21. #include <sys/stat.h>
  22. #include <fcntl.h>
  23. #ifndef O_CLOEXEC
  24. #define O_CLOEXEC 0
  25. #endif
  26. #else
  27. #include <windows.h>
  28. #include <io.h>
  29. #endif
  30. #include "elist.h"
  31. #include "miner.h"
  32. #include "fpgautils.h"
  33. #include "driver-avalon.h"
  34. #include "hexdump.c"
  35. static struct timeval history_sec = { HISTORY_SEC, 0 };
  36. static const char *MODE_DEFAULT_STR = "default";
  37. static const char *MODE_SHORT_STR = "short";
  38. static const char *MODE_LONG_STR = "long";
  39. static const char *MODE_VALUE_STR = "value";
  40. static const char *MODE_UNKNOWN_STR = "unknown";
  41. static int option_offset = -1;
  42. static struct AVALON_INFO **avalon_info;
  43. struct device_api avalon_api;
  44. static int avalon_init_task(struct avalon_task *at,
  45. uint8_t reset, uint8_t ff, uint8_t fan,
  46. uint8_t timeout, uint8_t chip_num, uint8_t miner_num)
  47. {
  48. static bool first = true;
  49. if (!at)
  50. return -1;
  51. memset(at, 0, sizeof(struct avalon_task));
  52. if (reset) {
  53. at->reset = 1;
  54. first = true;
  55. }
  56. at->flush_fifo = (ff ? 1 : 0);
  57. at->fan_eft = (fan ? 1 : 0);
  58. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_PWM);
  59. if (timeout || chip_num || miner_num) {
  60. at->timer_eft = 1;
  61. }
  62. if (first && !at->reset) {
  63. at->fan_eft = 1;
  64. at->timer_eft = 1;
  65. first = false;
  66. }
  67. at->timeout_data = (timeout ? timeout : AVALON_DEFAULT_TIMEOUT);
  68. at->chip_num = (chip_num ? chip_num : AVALON_DEFAULT_CHIP_NUM);
  69. at->miner_num = (miner_num ? miner_num : AVALON_DEFAULT_MINER_NUM);
  70. at->nonce_elf = 1;
  71. return 0;
  72. }
  73. static inline void avalon_create_task(struct avalon_task *at, struct work *work)
  74. {
  75. memcpy(at->midstate, work->midstate, 32);
  76. memcpy(at->data, work->data + 64, 12);
  77. }
  78. static int avalon_send_task(int fd, const struct avalon_task *at)
  79. {
  80. size_t ret;
  81. int full;
  82. struct timespec p;
  83. uint8_t *buf;
  84. int nr_len;
  85. nr_len = AVALON_WRITE_SIZE + 4 * at->chip_num;
  86. buf = calloc(1, AVALON_WRITE_SIZE + nr_len);
  87. if (!buf)
  88. return AVA_SEND_ERROR;
  89. memcpy(buf, at, AVALON_WRITE_SIZE);
  90. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  91. uint8_t tt = 0;
  92. tt = (buf[0] & 0x0f) << 4;
  93. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  94. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  95. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  96. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  97. buf[0] = tt;
  98. buf[4] = rev8(buf[4]);
  99. #endif
  100. if (opt_debug) {
  101. applog(LOG_DEBUG, "Avalon: Sent(%d):", nr_len);
  102. hexdump((uint8_t *)buf, nr_len);
  103. }
  104. ret = write(fd, buf, nr_len);
  105. free(buf);
  106. if (unlikely(ret != nr_len))
  107. return AVA_SEND_ERROR;
  108. p.tv_sec = 0;
  109. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  110. nanosleep(&p, NULL);
  111. full = avalon_buffer_full(fd);
  112. applog(LOG_DEBUG, "Avalon: Sent: Buffer full: %s",
  113. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  114. if (full == AVA_BUFFER_EMPTY)
  115. return AVA_SEND_BUFFER_EMPTY;
  116. return AVA_SEND_BUFFER_FULL;
  117. }
  118. static int avalon_gets(int fd, uint8_t *buf, int read_count,
  119. struct thr_info *thr, struct timeval *tv_finish)
  120. {
  121. ssize_t ret = 0;
  122. int rc = 0;
  123. int read_amount = AVALON_READ_SIZE;
  124. bool first = true;
  125. /* Read reply 1 byte at a time to get earliest tv_finish */
  126. while (true) {
  127. ret = read(fd, buf, 1);
  128. if (ret < 0)
  129. return AVA_GETS_ERROR;
  130. if (first && tv_finish != NULL)
  131. gettimeofday(tv_finish, NULL);
  132. if (ret >= read_amount)
  133. return AVA_GETS_OK;
  134. if (ret > 0) {
  135. buf += ret;
  136. read_amount -= ret;
  137. first = false;
  138. continue;
  139. }
  140. rc++;
  141. if (rc >= read_count) {
  142. if (opt_debug) {
  143. applog(LOG_ERR,
  144. "Avalon: No data in %.2f seconds",
  145. (float)rc/(float)TIME_FACTOR);
  146. }
  147. return AVA_GETS_TIMEOUT;
  148. }
  149. if (thr && thr->work_restart) {
  150. if (opt_debug) {
  151. applog(LOG_ERR,
  152. "Avalon: Work restart at %.2f seconds",
  153. (float)(rc)/(float)TIME_FACTOR);
  154. }
  155. return AVA_GETS_RESTART;
  156. }
  157. }
  158. }
  159. static int avalon_get_result(int fd, struct avalon_result *ar,
  160. struct thr_info *thr, struct timeval *tv_finish)
  161. {
  162. struct cgpu_info *avalon;
  163. struct AVALON_INFO *info;
  164. uint8_t result[AVALON_READ_SIZE];
  165. int ret, read_count = 16;
  166. if (thr) {
  167. avalon = thr->cgpu;
  168. info = avalon_info[avalon->device_id];
  169. read_count = info->read_count;
  170. }
  171. memset(result, 0, AVALON_READ_SIZE);
  172. ret = avalon_gets(fd, result, read_count, thr, tv_finish);
  173. if (ret == AVA_GETS_OK) {
  174. if (opt_debug) {
  175. applog(LOG_DEBUG, "Avalon: get:");
  176. hexdump((uint8_t *)result, AVALON_READ_SIZE);
  177. }
  178. memcpy((uint8_t *)ar, result, AVALON_READ_SIZE);
  179. }
  180. return ret;
  181. }
  182. static int avalon_decode_nonce(struct work **work, struct avalon_result *ar,
  183. uint32_t *nonce)
  184. {
  185. uint8_t data[12];
  186. int i;
  187. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  188. if (!work || !work[i])
  189. return -1;
  190. }
  191. *nonce = ar->nonce;
  192. #if !defined (__BIG_ENDIAN__) && !defined(MIPSEB)
  193. *nonce = swab32(*nonce);
  194. #endif
  195. memcpy(data, ar->data, 12);
  196. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  197. if (!memcmp(data, work[i]->data + 64, 12))
  198. break;
  199. }
  200. applog(LOG_DEBUG, "Avalon: match to work: %d", i);
  201. if (i == AVALON_GET_WORK_COUNT)
  202. return -1;
  203. i -= 1;
  204. return i;
  205. }
  206. static int avalon_reset(int fd)
  207. {
  208. struct avalon_task at;
  209. struct avalon_result ar;
  210. uint8_t *buf;
  211. int ret, i;
  212. struct timespec p;
  213. avalon_init_task(&at,
  214. 1,
  215. 0,
  216. AVALON_DEFAULT_FAN_PWM,
  217. AVALON_DEFAULT_TIMEOUT,
  218. AVALON_DEFAULT_CHIP_NUM,
  219. AVALON_DEFAULT_MINER_NUM);
  220. ret = avalon_send_task(fd, &at);
  221. if (ret == AVA_SEND_ERROR)
  222. return 1;
  223. avalon_get_result(fd, &ar, NULL, NULL);
  224. buf = (uint8_t *)&ar;
  225. for (i = 0; i < 11; i++)
  226. if (buf[i] != 0)
  227. break;
  228. /* FIXME: add more avalon info base on return */
  229. if (i != 11) {
  230. applog(LOG_ERR, "Avalon: Reset failed! not a Avalon?");
  231. return 1;
  232. }
  233. p.tv_sec = 1;
  234. p.tv_nsec = AVALON_SEND_WORK_PITCH;
  235. nanosleep(&p, NULL);
  236. applog(LOG_ERR, "Avalon: Reset succeeded");
  237. return 0;
  238. }
  239. static void do_avalon_close(struct thr_info *thr)
  240. {
  241. struct cgpu_info *avalon = thr->cgpu;
  242. avalon_close(avalon->device_fd);
  243. avalon->device_fd = -1;
  244. }
  245. static const char *timing_mode_str(enum timing_mode timing_mode)
  246. {
  247. switch(timing_mode) {
  248. case MODE_DEFAULT:
  249. return MODE_DEFAULT_STR;
  250. case MODE_SHORT:
  251. return MODE_SHORT_STR;
  252. case MODE_LONG:
  253. return MODE_LONG_STR;
  254. case MODE_VALUE:
  255. return MODE_VALUE_STR;
  256. default:
  257. return MODE_UNKNOWN_STR;
  258. }
  259. }
  260. static void set_timing_mode(int this_option_offset, struct cgpu_info *avalon)
  261. {
  262. struct AVALON_INFO *info = avalon_info[avalon->device_id];
  263. double Hs;
  264. char buf[BUFSIZ+1];
  265. char *ptr, *comma, *eq;
  266. size_t max;
  267. int i;
  268. if (opt_icarus_timing == NULL)
  269. buf[0] = '\0';
  270. else {
  271. ptr = opt_icarus_timing;
  272. for (i = 0; i < this_option_offset; i++) {
  273. comma = strchr(ptr, ',');
  274. if (comma == NULL)
  275. break;
  276. ptr = comma + 1;
  277. }
  278. comma = strchr(ptr, ',');
  279. if (comma == NULL)
  280. max = strlen(ptr);
  281. else
  282. max = comma - ptr;
  283. if (max > BUFSIZ)
  284. max = BUFSIZ;
  285. strncpy(buf, ptr, max);
  286. buf[max] = '\0';
  287. }
  288. info->Hs = 0;
  289. info->read_count = 0;
  290. if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
  291. info->Hs = AVALON_HASH_TIME;
  292. info->read_count = AVALON_READ_COUNT_TIMING;
  293. info->timing_mode = MODE_SHORT;
  294. info->do_avalon_timing = true;
  295. } else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
  296. info->Hs = AVALON_HASH_TIME;
  297. info->read_count = AVALON_READ_COUNT_TIMING;
  298. info->timing_mode = MODE_LONG;
  299. info->do_avalon_timing = true;
  300. } else if ((Hs = atof(buf)) != 0) {
  301. info->Hs = Hs / NANOSEC;
  302. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  303. if ((eq = strchr(buf, '=')) != NULL)
  304. info->read_count = atoi(eq+1);
  305. if (info->read_count < 1)
  306. info->read_count =
  307. (int)(info->fullnonce * TIME_FACTOR) - 1;
  308. if (unlikely(info->read_count < 1))
  309. info->read_count = 1;
  310. info->timing_mode = MODE_VALUE;
  311. info->do_avalon_timing = false;
  312. } else {
  313. /* Anything else in buf just uses DEFAULT mode */
  314. info->Hs = AVALON_HASH_TIME;
  315. info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
  316. if ((eq = strchr(buf, '=')) != NULL)
  317. info->read_count = atoi(eq+1);
  318. if (info->read_count < 1)
  319. info->read_count =
  320. (int)(info->fullnonce * TIME_FACTOR) - 1;
  321. info->timing_mode = MODE_DEFAULT;
  322. info->do_avalon_timing = false;
  323. }
  324. info->min_data_count = MIN_DATA_COUNT;
  325. applog(LOG_DEBUG, "Avalon: Init: %d mode=%s read_count=%d Hs=%e",
  326. avalon->device_id, timing_mode_str(info->timing_mode),
  327. info->read_count, info->Hs);
  328. }
  329. static uint32_t mask(int work_division)
  330. {
  331. char err_buf[BUFSIZ+1];
  332. uint32_t nonce_mask = 0x7fffffff;
  333. switch (work_division) {
  334. case 1:
  335. nonce_mask = 0xffffffff;
  336. break;
  337. case 2:
  338. nonce_mask = 0x7fffffff;
  339. break;
  340. case 4:
  341. nonce_mask = 0x3fffffff;
  342. break;
  343. case 8:
  344. nonce_mask = 0x1fffffff;
  345. break;
  346. default:
  347. sprintf(err_buf,
  348. "Invalid2 avalon-options for work_division (%d)"
  349. " must be 1, 2, 4 or 8", work_division);
  350. quit(1, err_buf);
  351. }
  352. return nonce_mask;
  353. }
  354. static void get_options(int this_option_offset, int *baud, int *work_division,
  355. int *asic_count)
  356. {
  357. char err_buf[BUFSIZ+1];
  358. char buf[BUFSIZ+1];
  359. char *ptr, *comma, *colon, *colon2;
  360. size_t max;
  361. int i, tmp;
  362. if (opt_icarus_options == NULL)
  363. buf[0] = '\0';
  364. else {
  365. ptr = opt_icarus_options;
  366. for (i = 0; i < this_option_offset; i++) {
  367. comma = strchr(ptr, ',');
  368. if (comma == NULL)
  369. break;
  370. ptr = comma + 1;
  371. }
  372. comma = strchr(ptr, ',');
  373. if (comma == NULL)
  374. max = strlen(ptr);
  375. else
  376. max = comma - ptr;
  377. if (max > BUFSIZ)
  378. max = BUFSIZ;
  379. strncpy(buf, ptr, max);
  380. buf[max] = '\0';
  381. }
  382. *baud = AVALON_IO_SPEED;
  383. *work_division = 2;
  384. *asic_count = 2;
  385. if (*buf) {
  386. colon = strchr(buf, ':');
  387. if (colon)
  388. *(colon++) = '\0';
  389. if (*buf) {
  390. tmp = atoi(buf);
  391. switch (tmp) {
  392. case 115200:
  393. *baud = 115200;
  394. break;
  395. case 57600:
  396. *baud = 57600;
  397. break;
  398. default:
  399. sprintf(err_buf,
  400. "Invalid avalon-options for baud (%s) "
  401. "must be 115200 or 57600", buf);
  402. quit(1, err_buf);
  403. }
  404. }
  405. if (colon && *colon) {
  406. colon2 = strchr(colon, ':');
  407. if (colon2)
  408. *(colon2++) = '\0';
  409. if (*colon) {
  410. tmp = atoi(colon);
  411. if (tmp == 1 || tmp == 2 ||
  412. tmp == 4 || tmp == 8) {
  413. *work_division = tmp;
  414. *asic_count = tmp;
  415. } else {
  416. sprintf(err_buf,
  417. "Invalid avalon-options for "
  418. "work_division (%s) must be 1,"
  419. " 2, 4 or 8", colon);
  420. quit(1, err_buf);
  421. }
  422. }
  423. if (colon2 && *colon2) {
  424. tmp = atoi(colon2);
  425. if (tmp > 0 && tmp <= *work_division)
  426. *asic_count = tmp;
  427. else {
  428. sprintf(err_buf,
  429. "Invalid avalon-options for "
  430. "asic_count (%s) must be >0 "
  431. "and <=work_division (%d)",
  432. colon2, *work_division);
  433. quit(1, err_buf);
  434. }
  435. }
  436. }
  437. }
  438. }
  439. static bool avalon_detect_one(const char *devpath)
  440. {
  441. struct AVALON_INFO *info;
  442. int fd, ret;
  443. int baud, work_division, asic_count;
  444. int this_option_offset = ++option_offset;
  445. get_options(this_option_offset, &baud, &work_division, &asic_count);
  446. applog(LOG_DEBUG, "Avalon Detect: Attempting to open %s", devpath);
  447. fd = avalon_open2(devpath, baud, true);
  448. if (unlikely(fd == -1)) {
  449. applog(LOG_ERR, "Avalon Detect: Failed to open %s", devpath);
  450. return false;
  451. }
  452. ret = avalon_reset(fd);
  453. avalon_close(fd);
  454. if (ret)
  455. return false;
  456. /* We have a real Avalon! */
  457. struct cgpu_info *avalon;
  458. avalon = calloc(1, sizeof(struct cgpu_info));
  459. avalon->api = &avalon_api;
  460. avalon->device_path = strdup(devpath);
  461. avalon->device_fd = -1;
  462. avalon->threads = AVALON_MINER_THREADS;
  463. add_cgpu(avalon);
  464. avalon_info = realloc(avalon_info,
  465. sizeof(struct AVALON_INFO *) *
  466. (total_devices + 1));
  467. applog(LOG_INFO, "Avalon Detect: Found at %s, mark as %d",
  468. devpath, avalon->device_id);
  469. applog(LOG_DEBUG,
  470. "Avalon: Init: %d baud=%d work_division=%d asic_count=%d",
  471. avalon->device_id, baud, work_division, asic_count);
  472. avalon_info[avalon->device_id] = (struct AVALON_INFO *)
  473. malloc(sizeof(struct AVALON_INFO));
  474. if (unlikely(!(avalon_info[avalon->device_id])))
  475. quit(1, "Failed to malloc AVALON_INFO");
  476. info = avalon_info[avalon->device_id];
  477. memset(info, 0, sizeof(struct AVALON_INFO));
  478. info->baud = baud;
  479. info->work_division = work_division;
  480. info->asic_count = asic_count;
  481. info->nonce_mask = mask(work_division);
  482. set_timing_mode(this_option_offset, avalon);
  483. return true;
  484. }
  485. static inline void avalon_detect()
  486. {
  487. serial_detect(&avalon_api, avalon_detect_one);
  488. }
  489. static bool avalon_prepare(struct thr_info *thr)
  490. {
  491. struct cgpu_info *avalon = thr->cgpu;
  492. struct timeval now;
  493. int fd;
  494. avalon->device_fd = -1;
  495. fd = avalon_open(avalon->device_path,
  496. avalon_info[avalon->device_id]->baud);
  497. if (unlikely(fd == -1)) {
  498. applog(LOG_ERR, "Avalon: Failed to open on %s",
  499. avalon->device_path);
  500. return false;
  501. }
  502. avalon_reset(fd);
  503. avalon->device_fd = fd;
  504. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  505. gettimeofday(&now, NULL);
  506. get_datestamp(avalon->init, &now);
  507. return true;
  508. }
  509. static void avalon_free_work(struct work **work)
  510. {
  511. int i;
  512. if (!work)
  513. return;
  514. /* FIXME: how do we do the free_work() if we buffer the 3 bulk taskes */
  515. for (i = 0; i < AVALON_GET_WORK_COUNT; i++)
  516. if (work[i])
  517. free_work(work[i++]);
  518. }
  519. static int64_t avalon_scanhash(struct thr_info *thr, struct work **bulk_work,
  520. __maybe_unused int64_t max_nonce)
  521. {
  522. struct cgpu_info *avalon;
  523. int fd;
  524. int ret;
  525. struct AVALON_INFO *info;
  526. struct avalon_task at;
  527. struct avalon_result ar;
  528. static struct work *bulk0[3] = {NULL, NULL, NULL};
  529. static struct work *bulk1[3] = {NULL, NULL, NULL};
  530. static struct work *bulk2[3] = {NULL, NULL, NULL};
  531. struct work **work = NULL;
  532. int full;
  533. uint32_t nonce;
  534. int64_t hash_count;
  535. int i, work_i0, work_i1, work_i2;
  536. int read_count;
  537. int count;
  538. struct timeval tv_start, tv_finish, elapsed;
  539. struct timeval tv_history_start, tv_history_finish;
  540. double Ti, Xi;
  541. int curr_hw_errors;
  542. bool was_hw_error;
  543. struct AVALON_HISTORY *history0, *history;
  544. double Hs, W, fullnonce;
  545. int64_t estimate_hashes;
  546. uint32_t values;
  547. int64_t hash_count_range;
  548. avalon = thr->cgpu;
  549. info = avalon_info[avalon->device_id];
  550. if (avalon->device_fd == -1)
  551. if (!avalon_prepare(thr)) {
  552. applog(LOG_ERR, "AVA%i: Comms error",
  553. avalon->device_id);
  554. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  555. /* fail the device if the reopen attempt fails */
  556. return -1;
  557. }
  558. fd = avalon->device_fd;
  559. #ifndef WIN32
  560. tcflush(fd, TCOFLUSH);
  561. #endif
  562. work = bulk_work;
  563. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  564. bulk0[i] = bulk1[i];
  565. bulk1[i] = bulk2[i];
  566. bulk2[i] = bulk_work[i];
  567. }
  568. i = 0;
  569. while (true) {
  570. avalon_init_default_task(&at);
  571. avalon_create_task(&at, work[i++]);
  572. ret = avalon_send_task(fd, &at);
  573. if (ret == AVA_SEND_ERROR) {
  574. avalon_free_work(bulk0);
  575. avalon_free_work(bulk1);
  576. avalon_free_work(bulk2);
  577. do_avalon_close(thr);
  578. applog(LOG_ERR, "AVA%i: Comms error",
  579. avalon->device_id);
  580. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  581. return 0; /* This should never happen */
  582. }
  583. if (ret == AVA_SEND_BUFFER_FULL) {
  584. break;
  585. }
  586. if (i == AVALON_GET_WORK_COUNT && ret != AVA_SEND_BUFFER_FULL) {
  587. return 0xffffffff;
  588. }
  589. }
  590. elapsed.tv_sec = elapsed.tv_usec = 0;
  591. gettimeofday(&tv_start, NULL);
  592. /* count may != AVALON_GET_WORK_COUNT */
  593. for (i = 0; i < AVALON_GET_WORK_COUNT; i++) {
  594. work[i]->blk.nonce = 0xffffffff;
  595. work_i0 = work_i1 = work_i2 = -1;
  596. ret = avalon_get_result(fd, &ar, thr, &tv_finish);
  597. if (ret == AVA_GETS_ERROR) {
  598. avalon_free_work(bulk0);
  599. avalon_free_work(bulk1);
  600. avalon_free_work(bulk2);
  601. do_avalon_close(thr);
  602. applog(LOG_ERR, "AVA%i: Comms error", avalon->device_id);
  603. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  604. return 0;
  605. }
  606. work_i0 = avalon_decode_nonce(bulk0, &ar, &nonce);
  607. if (work_i0 < 0)
  608. applog(LOG_DEBUG, "Avalon: can not match nonce to bulk0");
  609. work_i1 = avalon_decode_nonce(bulk1, &ar, &nonce);
  610. if (work_i1 < 0)
  611. applog(LOG_DEBUG, "Avalon: can not match nonce to bulk1");
  612. work_i2 = avalon_decode_nonce(bulk2, &ar, &nonce);
  613. if (work_i2 < 0)
  614. applog(LOG_DEBUG, "Avalon: can not match nonce to bulk2");
  615. /* aborted before becoming idle, get new work */
  616. if (ret == AVA_GETS_TIMEOUT || ret == AVA_GETS_RESTART) {
  617. timersub(&tv_finish, &tv_start, &elapsed);
  618. /* ONLY up to just when it aborted
  619. * We didn't read a reply so we don't subtract AVALON_READ_TIME */
  620. estimate_hashes = ((double)(elapsed.tv_sec) +
  621. ((double)(elapsed.tv_usec)) /
  622. ((double)1000000)) / info->Hs;
  623. /* If some Serial-USB delay allowed the full nonce range to
  624. * complete it can't have done more than a full nonce */
  625. if (unlikely(estimate_hashes > 0xffffffff))
  626. estimate_hashes = 0xffffffff;
  627. applog(LOG_DEBUG,
  628. "Avalon: no nonce = 0x%08llx hashes "
  629. "(%ld.%06lds)",
  630. estimate_hashes, elapsed.tv_sec, elapsed.tv_usec);
  631. avalon_free_work(bulk0);
  632. continue;
  633. //return estimate_hashes;
  634. }
  635. curr_hw_errors = avalon->hw_errors;
  636. if (work_i0 >= 0)
  637. submit_nonce(thr, bulk0[work_i0], nonce);
  638. if (work_i1 >= 0)
  639. submit_nonce(thr, bulk1[work_i1], nonce);
  640. if (work_i2 >= 0)
  641. submit_nonce(thr, bulk2[work_i2], nonce);
  642. was_hw_error = (curr_hw_errors > avalon->hw_errors);
  643. /* Force a USB close/reopen on any hw error */
  644. if (was_hw_error)
  645. do_avalon_close(thr);
  646. hash_count = (nonce & info->nonce_mask);
  647. hash_count++;
  648. hash_count *= info->asic_count;
  649. full = avalon_buffer_full(fd);
  650. applog(LOG_DEBUG, "Avalon: Buffer full: %s",
  651. ((full == AVA_BUFFER_FULL) ? "Yes" : "No"));
  652. if (full == AVA_BUFFER_EMPTY) {
  653. applog(LOG_DEBUG, "Avalon: Finished bulk task!");
  654. avalon_free_work(bulk0);
  655. }
  656. }
  657. avalon_free_work(bulk0);
  658. if (opt_debug || info->do_avalon_timing)
  659. timersub(&tv_finish, &tv_start, &elapsed);
  660. if (opt_debug) {
  661. applog(LOG_DEBUG,
  662. "Avalon: nonce = 0x%08x = 0x%08llx hashes "
  663. "(%ld.%06lds)",
  664. nonce, hash_count, elapsed.tv_sec, elapsed.tv_usec);
  665. }
  666. /* ignore possible end condition values ... and hw errors */
  667. if (info->do_avalon_timing
  668. && !was_hw_error
  669. && ((nonce & info->nonce_mask) > END_CONDITION)
  670. && ((nonce & info->nonce_mask) <
  671. (info->nonce_mask & ~END_CONDITION))) {
  672. gettimeofday(&tv_history_start, NULL);
  673. history0 = &(info->history[0]);
  674. if (history0->values == 0)
  675. timeradd(&tv_start, &history_sec, &(history0->finish));
  676. Ti = (double)(elapsed.tv_sec)
  677. + ((double)(elapsed.tv_usec))/((double)1000000)
  678. - ((double)AVALON_READ_TIME(info->baud));
  679. Xi = (double)hash_count;
  680. history0->sumXiTi += Xi * Ti;
  681. history0->sumXi += Xi;
  682. history0->sumTi += Ti;
  683. history0->sumXi2 += Xi * Xi;
  684. history0->values++;
  685. if (history0->hash_count_max < hash_count)
  686. history0->hash_count_max = hash_count;
  687. if (history0->hash_count_min > hash_count ||
  688. history0->hash_count_min == 0)
  689. history0->hash_count_min = hash_count;
  690. if (history0->values >= info->min_data_count
  691. && timercmp(&tv_start, &(history0->finish), >)) {
  692. for (i = INFO_HISTORY; i > 0; i--)
  693. memcpy(&(info->history[i]),
  694. &(info->history[i-1]),
  695. sizeof(struct AVALON_HISTORY));
  696. /* Initialise history0 to zero for summary calculation */
  697. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  698. /* We just completed a history data set
  699. * So now recalc read_count based on the
  700. * whole history thus we will
  701. * initially get more accurate until it
  702. * completes INFO_HISTORY
  703. * total data sets */
  704. count = 0;
  705. for (i = 1 ; i <= INFO_HISTORY; i++) {
  706. history = &(info->history[i]);
  707. if (history->values >= MIN_DATA_COUNT) {
  708. count++;
  709. history0->sumXiTi += history->sumXiTi;
  710. history0->sumXi += history->sumXi;
  711. history0->sumTi += history->sumTi;
  712. history0->sumXi2 += history->sumXi2;
  713. history0->values += history->values;
  714. if (history0->hash_count_max < history->hash_count_max)
  715. history0->hash_count_max = history->hash_count_max;
  716. if (history0->hash_count_min > history->hash_count_min || history0->hash_count_min == 0)
  717. history0->hash_count_min = history->hash_count_min;
  718. }
  719. }
  720. /* All history data */
  721. Hs = (history0->values*history0->sumXiTi - history0->sumXi*history0->sumTi)
  722. / (history0->values*history0->sumXi2 - history0->sumXi*history0->sumXi);
  723. W = history0->sumTi/history0->values - Hs*history0->sumXi/history0->values;
  724. hash_count_range = history0->hash_count_max - history0->hash_count_min;
  725. values = history0->values;
  726. /* Initialise history0 to zero for next data set */
  727. memset(history0, 0, sizeof(struct AVALON_HISTORY));
  728. fullnonce = W + Hs * (((double)0xffffffff) + 1);
  729. read_count = (int)(fullnonce * TIME_FACTOR) - 1;
  730. info->Hs = Hs;
  731. info->read_count = read_count;
  732. info->fullnonce = fullnonce;
  733. info->count = count;
  734. info->W = W;
  735. info->values = values;
  736. info->hash_count_range = hash_count_range;
  737. if (info->min_data_count < MAX_MIN_DATA_COUNT)
  738. info->min_data_count *= 2;
  739. else if (info->timing_mode == MODE_SHORT)
  740. info->do_avalon_timing = false;
  741. /* applog(LOG_WARNING, "Avalon %d Re-estimate: read_count=%d fullnonce=%fs history count=%d Hs=%e W=%e values=%d hash range=0x%08lx min data count=%u", avalon->device_id, read_count, fullnonce, count, Hs, W, values, hash_count_range, info->min_data_count);*/
  742. applog(LOG_WARNING, "Avalon %d Re-estimate: Hs=%e W=%e read_count=%d fullnonce=%.3fs",
  743. avalon->device_id, Hs, W, read_count, fullnonce);
  744. }
  745. info->history_count++;
  746. gettimeofday(&tv_history_finish, NULL);
  747. timersub(&tv_history_finish, &tv_history_start, &tv_history_finish);
  748. timeradd(&tv_history_finish, &(info->history_time), &(info->history_time));
  749. }
  750. return hash_count;
  751. }
  752. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  753. {
  754. struct api_data *root = NULL;
  755. struct AVALON_INFO *info = avalon_info[cgpu->device_id];
  756. /* Warning, access to these is not locked - but we don't really
  757. * care since hashing performance is way more important than
  758. * locking access to displaying API debug 'stats'
  759. * If locking becomes an issue for any of them, use copy_data=true also */
  760. root = api_add_int(root, "read_count", &(info->read_count), false);
  761. root = api_add_double(root, "fullnonce", &(info->fullnonce), false);
  762. root = api_add_int(root, "count", &(info->count), false);
  763. root = api_add_hs(root, "Hs", &(info->Hs), false);
  764. root = api_add_double(root, "W", &(info->W), false);
  765. root = api_add_uint(root, "total_values", &(info->values), false);
  766. root = api_add_uint64(root, "range", &(info->hash_count_range), false);
  767. root = api_add_uint64(root, "history_count", &(info->history_count),
  768. false);
  769. root = api_add_timeval(root, "history_time", &(info->history_time),
  770. false);
  771. root = api_add_uint(root, "min_data_count", &(info->min_data_count),
  772. false);
  773. root = api_add_uint(root, "timing_values", &(info->history[0].values),
  774. false);
  775. root = api_add_const(root, "timing_mode",
  776. timing_mode_str(info->timing_mode), false);
  777. root = api_add_bool(root, "is_timing", &(info->do_avalon_timing),
  778. false);
  779. root = api_add_int(root, "baud", &(info->baud), false);
  780. root = api_add_int(root, "work_division", &(info->work_division),
  781. false);
  782. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  783. return root;
  784. }
  785. static void avalon_shutdown(struct thr_info *thr)
  786. {
  787. do_avalon_close(thr);
  788. }
  789. struct device_api avalon_api = {
  790. .dname = "avalon",
  791. .name = "AVA",
  792. .api_detect = avalon_detect,
  793. .thread_prepare = avalon_prepare,
  794. .scanhash_queue = avalon_scanhash,
  795. .get_api_stats = avalon_api_stats,
  796. .thread_shutdown = avalon_shutdown,
  797. };