driver-avalon.c 41 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #include <time.h>
  22. #ifndef WIN32
  23. #include <sys/select.h>
  24. #include <termios.h>
  25. #include <sys/stat.h>
  26. #include <fcntl.h>
  27. #ifndef O_CLOEXEC
  28. #define O_CLOEXEC 0
  29. #endif
  30. #else
  31. #include "compat.h"
  32. #include <windows.h>
  33. #include <io.h>
  34. #endif
  35. #include "elist.h"
  36. #include "miner.h"
  37. #include "usbutils.h"
  38. #include "driver-avalon.h"
  39. #include "hexdump.c"
  40. #include "util.h"
  41. int opt_avalon_temp = AVALON_TEMP_TARGET;
  42. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  43. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  44. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  45. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  46. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  47. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  48. bool opt_avalon_auto;
  49. static int option_offset = -1;
  50. struct device_drv avalon_drv;
  51. static int avalon_init_task(struct avalon_task *at,
  52. uint8_t reset, uint8_t ff, uint8_t fan,
  53. uint8_t timeout, uint8_t asic_num,
  54. uint8_t miner_num, uint8_t nonce_elf,
  55. uint8_t gate_miner, int frequency)
  56. {
  57. uint16_t *lefreq16;
  58. uint8_t *buf;
  59. static bool first = true;
  60. if (unlikely(!at))
  61. return -1;
  62. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  63. return -1;
  64. memset(at, 0, sizeof(struct avalon_task));
  65. if (unlikely(reset)) {
  66. at->reset = 1;
  67. at->fan_eft = 1;
  68. at->timer_eft = 1;
  69. first = true;
  70. }
  71. at->flush_fifo = (ff ? 1 : 0);
  72. at->fan_eft = (fan ? 1 : 0);
  73. if (unlikely(first && !at->reset)) {
  74. at->fan_eft = 1;
  75. at->timer_eft = 1;
  76. first = false;
  77. }
  78. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  79. at->timeout_data = timeout;
  80. at->asic_num = asic_num;
  81. at->miner_num = miner_num;
  82. at->nonce_elf = nonce_elf;
  83. at->gate_miner_elf = 1;
  84. at->asic_pll = 1;
  85. if (unlikely(gate_miner)) {
  86. at-> gate_miner = 1;
  87. at->asic_pll = 0;
  88. }
  89. buf = (uint8_t *)at;
  90. buf[5] = 0x00;
  91. buf[8] = 0x74;
  92. buf[9] = 0x01;
  93. buf[10] = 0x00;
  94. buf[11] = 0x00;
  95. lefreq16 = (uint16_t *)&buf[6];
  96. *lefreq16 = htole16(frequency * 8);
  97. return 0;
  98. }
  99. static inline void avalon_create_task(struct avalon_task *at,
  100. struct work *work)
  101. {
  102. memcpy(at->midstate, work->midstate, 32);
  103. memcpy(at->data, work->data + 64, 12);
  104. }
  105. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  106. {
  107. int err, amount;
  108. err = usb_write(avalon, buf, len, &amount, ep);
  109. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  110. avalon->device_id, err);
  111. if (unlikely(err != 0)) {
  112. applog(LOG_WARNING, "usb_write error on avalon_write");
  113. return AVA_SEND_ERROR;
  114. }
  115. if (amount != len) {
  116. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  117. return AVA_SEND_ERROR;
  118. }
  119. return AVA_SEND_OK;
  120. }
  121. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  122. {
  123. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  124. int delay, ret, i, ep = C_AVALON_TASK;
  125. struct avalon_info *info;
  126. uint32_t nonce_range;
  127. size_t nr_len;
  128. if (at->nonce_elf)
  129. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  130. else
  131. nr_len = AVALON_WRITE_SIZE;
  132. memcpy(buf, at, AVALON_WRITE_SIZE);
  133. if (at->nonce_elf) {
  134. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  135. for (i = 0; i < at->asic_num; i++) {
  136. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  137. (i * nonce_range & 0xff000000) >> 24;
  138. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  139. (i * nonce_range & 0x00ff0000) >> 16;
  140. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  141. (i * nonce_range & 0x0000ff00) >> 8;
  142. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  143. (i * nonce_range & 0x000000ff) >> 0;
  144. }
  145. }
  146. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  147. uint8_t tt = 0;
  148. tt = (buf[0] & 0x0f) << 4;
  149. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  150. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  151. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  152. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  153. buf[0] = tt;
  154. tt = (buf[4] & 0x0f) << 4;
  155. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  156. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  157. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  158. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  159. buf[4] = tt;
  160. #endif
  161. info = avalon->device_data;
  162. delay = nr_len * 10 * 1000000;
  163. delay = delay / info->baud;
  164. if (at->reset) {
  165. ep = C_AVALON_RESET;
  166. nr_len = 1;
  167. }
  168. if (opt_debug) {
  169. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  170. hexdump(buf, nr_len);
  171. }
  172. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  173. delay += 4000;
  174. nusleep(delay);
  175. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", delay);
  176. return ret;
  177. }
  178. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  179. struct avalon_info *info, struct avalon_result *ar,
  180. struct work *work)
  181. {
  182. uint32_t nonce;
  183. info = avalon->device_data;
  184. info->matching_work[work->subid]++;
  185. nonce = htole32(ar->nonce);
  186. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  187. return submit_nonce(thr, work, nonce);
  188. }
  189. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  190. static void wait_avalon_ready(struct cgpu_info *avalon)
  191. {
  192. while (avalon_buffer_full(avalon)) {
  193. nmsleep(40);
  194. }
  195. }
  196. #define AVALON_CTS (1 << 4)
  197. static inline bool avalon_cts(char c)
  198. {
  199. return (c & AVALON_CTS);
  200. }
  201. static int avalon_read(struct cgpu_info *avalon, unsigned char *buf,
  202. size_t bufsize, int timeout, int ep)
  203. {
  204. size_t total = 0, readsize = bufsize + 2;
  205. char readbuf[AVALON_READBUF_SIZE];
  206. int err, amount, ofs = 2, cp;
  207. err = usb_read_once_timeout(avalon, readbuf, readsize, &amount, timeout, ep);
  208. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  209. avalon->drv->name, avalon->device_id, err);
  210. if (amount < 2)
  211. goto out;
  212. /* The first 2 of every 64 bytes are status on FTDIRL */
  213. while (amount > 2) {
  214. cp = amount - 2;
  215. if (cp > 62)
  216. cp = 62;
  217. memcpy(&buf[total], &readbuf[ofs], cp);
  218. total += cp;
  219. amount -= cp + 2;
  220. ofs += 64;
  221. }
  222. out:
  223. return total;
  224. }
  225. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  226. {
  227. struct avalon_result ar;
  228. int ret, i, spare;
  229. struct avalon_task at;
  230. uint8_t *buf, *tmp;
  231. struct timespec p;
  232. /* Send reset, then check for result */
  233. avalon_init_task(&at, 1, 0,
  234. AVALON_DEFAULT_FAN_MAX_PWM,
  235. AVALON_DEFAULT_TIMEOUT,
  236. AVALON_DEFAULT_ASIC_NUM,
  237. AVALON_DEFAULT_MINER_NUM,
  238. 0, 0,
  239. AVALON_DEFAULT_FREQUENCY);
  240. wait_avalon_ready(avalon);
  241. ret = avalon_send_task(&at, avalon);
  242. if (unlikely(ret == AVA_SEND_ERROR))
  243. return -1;
  244. if (!initial) {
  245. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  246. return 0;
  247. }
  248. ret = avalon_read(avalon, (unsigned char *)&ar, AVALON_READ_SIZE,
  249. AVALON_RESET_TIMEOUT, C_GET_AVALON_RESET);
  250. /* What do these sleeps do?? */
  251. p.tv_sec = 0;
  252. p.tv_nsec = AVALON_RESET_PITCH;
  253. nanosleep(&p, NULL);
  254. /* Look for the first occurrence of 0xAA, the reset response should be:
  255. * AA 55 AA 55 00 00 00 00 00 00 */
  256. spare = ret - 10;
  257. buf = tmp = (uint8_t *)&ar;
  258. if (opt_debug) {
  259. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  260. hexdump(tmp, AVALON_READ_SIZE);
  261. }
  262. for (i = 0; i <= spare; i++) {
  263. buf = &tmp[i];
  264. if (buf[0] == 0xAA)
  265. break;
  266. }
  267. i = 0;
  268. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  269. buf[2] == 0xAA && buf[3] == 0x55) {
  270. for (i = 4; i < 11; i++)
  271. if (buf[i] != 0)
  272. break;
  273. }
  274. if (i != 11) {
  275. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  276. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  277. i, buf[0], buf[1], buf[2], buf[3]);
  278. /* FIXME: return 1; */
  279. } else
  280. applog(LOG_WARNING, "%s%d: Reset succeeded",
  281. avalon->drv->name, avalon->device_id);
  282. return 0;
  283. }
  284. static int avalon_calc_timeout(int frequency)
  285. {
  286. return AVALON_TIMEOUT_FACTOR / frequency;
  287. }
  288. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  289. int *asic_count, int *timeout, int *frequency)
  290. {
  291. char buf[BUFSIZ+1];
  292. char *ptr, *comma, *colon, *colon2, *colon3, *colon4;
  293. bool timeout_default;
  294. size_t max;
  295. int i, tmp;
  296. if (opt_avalon_options == NULL)
  297. buf[0] = '\0';
  298. else {
  299. ptr = opt_avalon_options;
  300. for (i = 0; i < this_option_offset; i++) {
  301. comma = strchr(ptr, ',');
  302. if (comma == NULL)
  303. break;
  304. ptr = comma + 1;
  305. }
  306. comma = strchr(ptr, ',');
  307. if (comma == NULL)
  308. max = strlen(ptr);
  309. else
  310. max = comma - ptr;
  311. if (max > BUFSIZ)
  312. max = BUFSIZ;
  313. strncpy(buf, ptr, max);
  314. buf[max] = '\0';
  315. }
  316. if (!(*buf))
  317. return false;
  318. colon = strchr(buf, ':');
  319. if (colon)
  320. *(colon++) = '\0';
  321. tmp = atoi(buf);
  322. switch (tmp) {
  323. case 115200:
  324. *baud = 115200;
  325. break;
  326. case 57600:
  327. *baud = 57600;
  328. break;
  329. case 38400:
  330. *baud = 38400;
  331. break;
  332. case 19200:
  333. *baud = 19200;
  334. break;
  335. default:
  336. quit(1, "Invalid avalon-options for baud (%s) "
  337. "must be 115200, 57600, 38400 or 19200", buf);
  338. }
  339. if (colon && *colon) {
  340. colon2 = strchr(colon, ':');
  341. if (colon2)
  342. *(colon2++) = '\0';
  343. if (*colon) {
  344. tmp = atoi(colon);
  345. if (tmp > 0 && tmp <= AVALON_DEFAULT_MINER_NUM) {
  346. *miner_count = tmp;
  347. } else {
  348. quit(1, "Invalid avalon-options for "
  349. "miner_count (%s) must be 1 ~ %d",
  350. colon, AVALON_DEFAULT_MINER_NUM);
  351. }
  352. }
  353. if (colon2 && *colon2) {
  354. colon3 = strchr(colon2, ':');
  355. if (colon3)
  356. *(colon3++) = '\0';
  357. tmp = atoi(colon2);
  358. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  359. *asic_count = tmp;
  360. else {
  361. quit(1, "Invalid avalon-options for "
  362. "asic_count (%s) must be 1 ~ %d",
  363. colon2, AVALON_DEFAULT_ASIC_NUM);
  364. }
  365. timeout_default = false;
  366. if (colon3 && *colon3) {
  367. colon4 = strchr(colon3, ':');
  368. if (colon4)
  369. *(colon4++) = '\0';
  370. if (tolower(*colon3) == 'd')
  371. timeout_default = true;
  372. else {
  373. tmp = atoi(colon3);
  374. if (tmp > 0 && tmp <= 0xff)
  375. *timeout = tmp;
  376. else {
  377. quit(1, "Invalid avalon-options for "
  378. "timeout (%s) must be 1 ~ %d",
  379. colon3, 0xff);
  380. }
  381. }
  382. if (colon4 && *colon4) {
  383. tmp = atoi(colon4);
  384. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  385. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  386. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  387. }
  388. *frequency = tmp;
  389. if (timeout_default)
  390. *timeout = avalon_calc_timeout(*frequency);
  391. }
  392. }
  393. }
  394. }
  395. return true;
  396. }
  397. char *set_avalon_fan(char *arg)
  398. {
  399. int val1, val2, ret;
  400. ret = sscanf(arg, "%d-%d", &val1, &val2);
  401. if (ret < 1)
  402. return "No values passed to avalon-fan";
  403. if (ret == 1)
  404. val2 = val1;
  405. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  406. return "Invalid value passed to avalon-fan";
  407. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  408. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  409. return NULL;
  410. }
  411. char *set_avalon_freq(char *arg)
  412. {
  413. int val1, val2, ret;
  414. ret = sscanf(arg, "%d-%d", &val1, &val2);
  415. if (ret < 1)
  416. return "No values passed to avalon-freq";
  417. if (ret == 1)
  418. val2 = val1;
  419. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  420. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  421. val2 < val1)
  422. return "Invalid value passed to avalon-freq";
  423. opt_avalon_freq_min = val1;
  424. opt_avalon_freq_max = val2;
  425. return NULL;
  426. }
  427. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  428. {
  429. int i;
  430. wait_avalon_ready(avalon);
  431. /* Send idle to all miners */
  432. for (i = 0; i < info->miner_count; i++) {
  433. struct avalon_task at;
  434. if (unlikely(avalon_buffer_full(avalon)))
  435. break;
  436. info->idle++;
  437. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  438. info->asic_count, info->miner_count, 1, 1,
  439. info->frequency);
  440. avalon_send_task(&at, avalon);
  441. }
  442. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  443. wait_avalon_ready(avalon);
  444. }
  445. static void avalon_initialise(struct cgpu_info *avalon)
  446. {
  447. int err, interface;
  448. if (avalon->usbinfo.nodev)
  449. return;
  450. interface = avalon->usbdev->found->interface;
  451. // Reset
  452. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  453. FTDI_VALUE_RESET, interface, C_RESET);
  454. applog(LOG_DEBUG, "%s%i: reset got err %d",
  455. avalon->drv->name, avalon->device_id, err);
  456. if (avalon->usbinfo.nodev)
  457. return;
  458. // Set latency
  459. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  460. AVALON_LATENCY, interface, C_LATENCY);
  461. applog(LOG_DEBUG, "%s%i: latency got err %d",
  462. avalon->drv->name, avalon->device_id, err);
  463. if (avalon->usbinfo.nodev)
  464. return;
  465. // Set data
  466. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  467. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  468. applog(LOG_DEBUG, "%s%i: data got err %d",
  469. avalon->drv->name, avalon->device_id, err);
  470. if (avalon->usbinfo.nodev)
  471. return;
  472. // Set the baud
  473. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  474. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  475. C_SETBAUD);
  476. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  477. avalon->drv->name, avalon->device_id, err);
  478. if (avalon->usbinfo.nodev)
  479. return;
  480. // Set Modem Control
  481. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  482. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  483. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  484. avalon->drv->name, avalon->device_id, err);
  485. if (avalon->usbinfo.nodev)
  486. return;
  487. // Set Flow Control
  488. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  489. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  490. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  491. avalon->drv->name, avalon->device_id, err);
  492. if (avalon->usbinfo.nodev)
  493. return;
  494. /* Avalon repeats the following */
  495. // Set Modem Control
  496. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  497. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  498. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  499. avalon->drv->name, avalon->device_id, err);
  500. if (avalon->usbinfo.nodev)
  501. return;
  502. // Set Flow Control
  503. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  504. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  505. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  506. avalon->drv->name, avalon->device_id, err);
  507. }
  508. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  509. {
  510. uint8_t buf[2];
  511. int err;
  512. if (usb_ident(avalon) == IDENT_BTB) {
  513. buf[0] = (uint8_t)core_voltage;
  514. buf[1] = (uint8_t)(core_voltage >> 8);
  515. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  516. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  517. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  518. if (unlikely(err < 0)) {
  519. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  520. avalon->drv->name, avalon->device_id, err);
  521. return false;
  522. } else {
  523. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  524. avalon->drv->name, avalon->device_id,
  525. core_voltage);
  526. }
  527. return true;
  528. }
  529. return false;
  530. }
  531. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  532. {
  533. uint8_t buf[2];
  534. int err;
  535. int amount;
  536. if (usb_ident(avalon) == IDENT_BTB) {
  537. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  538. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  539. (char *)buf, sizeof(buf), &amount,
  540. C_BB_GET_VOLTAGE);
  541. if (unlikely(err != 0 || amount != 2)) {
  542. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  543. avalon->drv->name, avalon->device_id, err, amount);
  544. return 0;
  545. } else {
  546. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  547. }
  548. } else {
  549. return 0;
  550. }
  551. }
  552. static bool avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  553. {
  554. int baud, miner_count, asic_count, timeout, frequency;
  555. int this_option_offset = ++option_offset;
  556. struct avalon_info *info;
  557. struct cgpu_info *avalon;
  558. bool configured;
  559. int ret;
  560. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  561. baud = AVALON_IO_SPEED;
  562. miner_count = AVALON_DEFAULT_MINER_NUM;
  563. asic_count = AVALON_DEFAULT_ASIC_NUM;
  564. timeout = AVALON_DEFAULT_TIMEOUT;
  565. frequency = AVALON_DEFAULT_FREQUENCY;
  566. configured = get_options(this_option_offset, &baud, &miner_count,
  567. &asic_count, &timeout, &frequency);
  568. if (!usb_init(avalon, dev, found))
  569. goto shin;
  570. /* Even though this is an FTDI type chip, we want to do the parsing
  571. * all ourselves so set it to std usb type */
  572. avalon->usbdev->usb_type = USB_TYPE_STD;
  573. avalon->usbdev->PrefPacketSize = AVALON_USB_PACKETSIZE;
  574. /* We have a real Avalon! */
  575. avalon_initialise(avalon);
  576. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  577. if (unlikely(!(avalon->device_data)))
  578. quit(1, "Failed to calloc avalon_info data");
  579. info = avalon->device_data;
  580. if (configured) {
  581. info->baud = baud;
  582. info->miner_count = miner_count;
  583. info->asic_count = asic_count;
  584. info->timeout = timeout;
  585. info->frequency = frequency;
  586. } else {
  587. info->baud = AVALON_IO_SPEED;
  588. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  589. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  590. info->timeout = AVALON_DEFAULT_TIMEOUT;
  591. info->frequency = AVALON_DEFAULT_FREQUENCY;
  592. }
  593. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  594. info->temp_max = 0;
  595. /* This is for check the temp/fan every 3~4s */
  596. info->temp_history_count = (4 / (float)((float)info->timeout * ((float)1.67/0x32))) + 1;
  597. if (info->temp_history_count <= 0)
  598. info->temp_history_count = 1;
  599. info->temp_history_index = 0;
  600. info->temp_sum = 0;
  601. info->temp_old = 0;
  602. if (!add_cgpu(avalon))
  603. goto unshin;
  604. ret = avalon_reset(avalon, true);
  605. if (ret && !configured)
  606. goto unshin;
  607. update_usb_stats(avalon);
  608. avalon_idle(avalon, info);
  609. applog(LOG_DEBUG, "Avalon Detected: %s "
  610. "(miner_count=%d asic_count=%d timeout=%d frequency=%d)",
  611. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  612. info->frequency);
  613. if (usb_ident(avalon) == IDENT_BTB) {
  614. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  615. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  616. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  617. opt_bitburner_core_voltage,
  618. BITBURNER_MIN_COREMV,
  619. BITBURNER_MAX_COREMV);
  620. } else
  621. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  622. }
  623. return true;
  624. unshin:
  625. usb_uninit(avalon);
  626. shin:
  627. free(avalon->device_data);
  628. avalon->device_data = NULL;
  629. avalon = usb_free_cgpu(avalon);
  630. return false;
  631. }
  632. static void avalon_detect(void)
  633. {
  634. usb_detect(&avalon_drv, avalon_detect_one);
  635. }
  636. static void avalon_init(struct cgpu_info *avalon)
  637. {
  638. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  639. }
  640. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  641. {
  642. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  643. (char *)ar->data, 64, 12);
  644. }
  645. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  646. struct avalon_result *ar);
  647. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  648. {
  649. applog(LOG_INFO, "%s%d: No matching work - HW error",
  650. thr->cgpu->drv->name, thr->cgpu->device_id);
  651. inc_hw_errors(thr);
  652. info->no_matching_work++;
  653. }
  654. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  655. struct thr_info *thr, char *buf, int *offset)
  656. {
  657. int i, spare = *offset - AVALON_READ_SIZE;
  658. bool found = false;
  659. for (i = 0; i <= spare; i++) {
  660. struct avalon_result *ar;
  661. struct work *work;
  662. ar = (struct avalon_result *)&buf[i];
  663. work = avalon_valid_result(avalon, ar);
  664. if (work) {
  665. bool gettemp = false;
  666. found = true;
  667. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  668. mutex_lock(&info->lock);
  669. if (!info->nonces++)
  670. gettemp = true;
  671. info->auto_nonces++;
  672. mutex_unlock(&info->lock);
  673. } else if (opt_avalon_auto) {
  674. mutex_lock(&info->lock);
  675. info->auto_hw++;
  676. mutex_unlock(&info->lock);
  677. }
  678. free_work(work);
  679. if (gettemp)
  680. avalon_update_temps(avalon, info, ar);
  681. break;
  682. }
  683. }
  684. if (!found) {
  685. spare = *offset - AVALON_READ_SIZE;
  686. /* We are buffering and haven't accumulated one more corrupt
  687. * work result. */
  688. if (spare < (int)AVALON_READ_SIZE)
  689. return;
  690. avalon_inc_nvw(info, thr);
  691. } else {
  692. spare = AVALON_READ_SIZE + i;
  693. if (i) {
  694. if (i >= (int)AVALON_READ_SIZE)
  695. avalon_inc_nvw(info, thr);
  696. else
  697. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  698. }
  699. }
  700. *offset -= spare;
  701. memmove(buf, buf + spare, *offset);
  702. }
  703. static void avalon_running_reset(struct cgpu_info *avalon,
  704. struct avalon_info *info)
  705. {
  706. avalon_reset(avalon, false);
  707. avalon_idle(avalon, info);
  708. avalon->results = 0;
  709. info->reset = false;
  710. }
  711. static void *avalon_get_results(void *userdata)
  712. {
  713. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  714. struct avalon_info *info = avalon->device_data;
  715. int offset = 0, read_delay = 0, ret = 0;
  716. const int rsize = AVALON_FTDI_READSIZE;
  717. char readbuf[AVALON_READBUF_SIZE];
  718. struct thr_info *thr = info->thr;
  719. struct timeval tv_start, tv_end;
  720. char threadname[24];
  721. snprintf(threadname, 24, "ava_recv/%d", avalon->device_id);
  722. RenameThread(threadname);
  723. while (likely(!avalon->shutdown)) {
  724. unsigned char buf[rsize];
  725. struct timeval tv_diff;
  726. int us_diff;
  727. if (offset >= (int)AVALON_READ_SIZE)
  728. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  729. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  730. /* This should never happen */
  731. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  732. offset = 0;
  733. }
  734. if (unlikely(info->reset)) {
  735. avalon_running_reset(avalon, info);
  736. /* Discard anything in the buffer */
  737. offset = 0;
  738. }
  739. /* As the usb read returns after just 1ms, sleep long enough
  740. * to leave the interface idle for writes to occur, but do not
  741. * sleep if we have been receiving data, and we do not yet have
  742. * a full result as more may be coming. */
  743. if (ret < 1 || offset == 0) {
  744. cgtime(&tv_end);
  745. timersub(&tv_end, &tv_start, &tv_diff);
  746. /* Assume it has not been > 1 second so ignore tv_sec */
  747. us_diff = tv_diff.tv_usec;
  748. read_delay = AVALON_READ_TIMEOUT * 1000 - us_diff;
  749. if (likely(read_delay >= 1000))
  750. nusleep(read_delay);
  751. }
  752. cgtime(&tv_start);
  753. ret = avalon_read(avalon, buf, rsize, AVALON_READ_TIMEOUT,
  754. C_AVALON_READ);
  755. if (ret < 1)
  756. continue;
  757. if (opt_debug) {
  758. applog(LOG_DEBUG, "Avalon: get:");
  759. hexdump((uint8_t *)buf, ret);
  760. }
  761. memcpy(&readbuf[offset], &buf, ret);
  762. offset += ret;
  763. }
  764. return NULL;
  765. }
  766. static void avalon_rotate_array(struct cgpu_info *avalon)
  767. {
  768. avalon->queued = 0;
  769. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  770. avalon->work_array = 0;
  771. }
  772. static void bitburner_rotate_array(struct cgpu_info *avalon)
  773. {
  774. avalon->queued = 0;
  775. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  776. avalon->work_array = 0;
  777. }
  778. static void avalon_set_timeout(struct avalon_info *info)
  779. {
  780. info->timeout = avalon_calc_timeout(info->frequency);
  781. }
  782. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  783. {
  784. struct avalon_info *info = avalon->device_data;
  785. info->frequency = frequency;
  786. if (info->frequency > opt_avalon_freq_max)
  787. info->frequency = opt_avalon_freq_max;
  788. if (info->frequency < opt_avalon_freq_min)
  789. info->frequency = opt_avalon_freq_min;
  790. avalon_set_timeout(info);
  791. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  792. avalon->drv->name, avalon->device_id,
  793. info->frequency, info->timeout);
  794. }
  795. static void avalon_inc_freq(struct avalon_info *info)
  796. {
  797. info->frequency += 2;
  798. if (info->frequency > opt_avalon_freq_max)
  799. info->frequency = opt_avalon_freq_max;
  800. avalon_set_timeout(info);
  801. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  802. info->frequency, info->timeout);
  803. }
  804. static void avalon_dec_freq(struct avalon_info *info)
  805. {
  806. info->frequency -= 1;
  807. if (info->frequency < opt_avalon_freq_min)
  808. info->frequency = opt_avalon_freq_min;
  809. avalon_set_timeout(info);
  810. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  811. info->frequency, info->timeout);
  812. }
  813. static void avalon_reset_auto(struct avalon_info *info)
  814. {
  815. info->auto_queued =
  816. info->auto_nonces =
  817. info->auto_hw = 0;
  818. }
  819. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  820. {
  821. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  822. mutex_lock(&info->lock);
  823. if (!info->optimal) {
  824. if (info->fan_pwm >= opt_avalon_fan_max) {
  825. applog(LOG_WARNING,
  826. "%s%i: Above optimal temperature, throttling",
  827. avalon->drv->name, avalon->device_id);
  828. avalon_dec_freq(info);
  829. }
  830. } else if (info->auto_nonces >= (AVALON_AUTO_CYCLE * 19 / 20) &&
  831. info->auto_nonces <= (AVALON_AUTO_CYCLE * 21 / 20)) {
  832. int total = info->auto_nonces + info->auto_hw;
  833. /* Try to keep hw errors < 2% */
  834. if (info->auto_hw * 100 < total)
  835. avalon_inc_freq(info);
  836. else if (info->auto_hw * 66 > total)
  837. avalon_dec_freq(info);
  838. }
  839. avalon_reset_auto(info);
  840. mutex_unlock(&info->lock);
  841. }
  842. }
  843. static void *avalon_send_tasks(void *userdata)
  844. {
  845. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  846. struct avalon_info *info = avalon->device_data;
  847. const int avalon_get_work_count = info->miner_count;
  848. char threadname[24];
  849. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  850. RenameThread(threadname);
  851. while (likely(!avalon->shutdown)) {
  852. int start_count, end_count, i, j, ret;
  853. struct timespec ts_start, ts_end;
  854. struct avalon_task at;
  855. bool idled = false;
  856. int64_t us_timeout;
  857. while (avalon_buffer_full(avalon))
  858. nmsleep(40);
  859. avalon_adjust_freq(info, avalon);
  860. /* A full nonce range */
  861. us_timeout = 0x100000000ll / info->asic_count / info->frequency;
  862. us_to_timespec(&ts_end, us_timeout);
  863. clock_gettime(CLOCK_MONOTONIC, &ts_start);
  864. timeraddspec(&ts_end, &ts_start);
  865. mutex_lock(&info->qlock);
  866. start_count = avalon->work_array * avalon_get_work_count;
  867. end_count = start_count + avalon_get_work_count;
  868. for (i = start_count, j = 0; i < end_count; i++, j++) {
  869. if (avalon_buffer_full(avalon)) {
  870. applog(LOG_INFO,
  871. "%s%i: Buffer full after only %d of %d work queued",
  872. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  873. break;
  874. }
  875. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  876. avalon_init_task(&at, 0, 0, info->fan_pwm,
  877. info->timeout, info->asic_count,
  878. info->miner_count, 1, 0, info->frequency);
  879. avalon_create_task(&at, avalon->works[i]);
  880. info->auto_queued++;
  881. } else {
  882. int idle_freq = info->frequency;
  883. if (!info->idle++)
  884. idled = true;
  885. if (unlikely(info->overheat && opt_avalon_auto))
  886. idle_freq = AVALON_MIN_FREQUENCY;
  887. avalon_init_task(&at, 0, 0, info->fan_pwm,
  888. info->timeout, info->asic_count,
  889. info->miner_count, 1, 1, idle_freq);
  890. /* Reset the auto_queued count if we end up
  891. * idling any miners. */
  892. avalon_reset_auto(info);
  893. }
  894. ret = avalon_send_task(&at, avalon);
  895. if (unlikely(ret == AVA_SEND_ERROR)) {
  896. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  897. avalon->drv->name, avalon->device_id);
  898. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  899. info->reset = true;
  900. break;
  901. }
  902. }
  903. avalon_rotate_array(avalon);
  904. pthread_cond_signal(&info->qcond);
  905. mutex_unlock(&info->qlock);
  906. if (unlikely(idled)) {
  907. applog(LOG_WARNING, "%s%i: Idled %d miners",
  908. avalon->drv->name, avalon->device_id, idled);
  909. }
  910. /* Sleep how long it would take to complete a full nonce range
  911. * at the current frequency using the clock_nanosleep function
  912. * timed from before we started loading new work so it will
  913. * fall short of the full duration. */
  914. do {
  915. ret = clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &ts_end, NULL);
  916. } while (ret == EINTR);
  917. }
  918. return NULL;
  919. }
  920. static void *bitburner_send_tasks(void *userdata)
  921. {
  922. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  923. struct avalon_info *info = avalon->device_data;
  924. const int avalon_get_work_count = info->miner_count;
  925. char threadname[24];
  926. snprintf(threadname, 24, "ava_send/%d", avalon->device_id);
  927. RenameThread(threadname);
  928. while (likely(!avalon->shutdown)) {
  929. int start_count, end_count, i, j, ret;
  930. struct avalon_task at;
  931. bool idled = false;
  932. while (avalon_buffer_full(avalon))
  933. nmsleep(40);
  934. avalon_adjust_freq(info, avalon);
  935. /* Give other threads a chance to acquire qlock. */
  936. i = 0;
  937. do {
  938. nmsleep(40);
  939. } while (!avalon->shutdown && i++ < 15
  940. && avalon->queued < avalon_get_work_count);
  941. mutex_lock(&info->qlock);
  942. start_count = avalon->work_array * avalon_get_work_count;
  943. end_count = start_count + avalon_get_work_count;
  944. for (i = start_count, j = 0; i < end_count; i++, j++) {
  945. while (avalon_buffer_full(avalon))
  946. nmsleep(40);
  947. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  948. avalon_init_task(&at, 0, 0, info->fan_pwm,
  949. info->timeout, info->asic_count,
  950. info->miner_count, 1, 0, info->frequency);
  951. avalon_create_task(&at, avalon->works[i]);
  952. info->auto_queued++;
  953. } else {
  954. int idle_freq = info->frequency;
  955. if (!info->idle++)
  956. idled = true;
  957. if (unlikely(info->overheat && opt_avalon_auto))
  958. idle_freq = AVALON_MIN_FREQUENCY;
  959. avalon_init_task(&at, 0, 0, info->fan_pwm,
  960. info->timeout, info->asic_count,
  961. info->miner_count, 1, 1, idle_freq);
  962. /* Reset the auto_queued count if we end up
  963. * idling any miners. */
  964. avalon_reset_auto(info);
  965. }
  966. ret = avalon_send_task(&at, avalon);
  967. if (unlikely(ret == AVA_SEND_ERROR)) {
  968. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  969. avalon->drv->name, avalon->device_id);
  970. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  971. info->reset = true;
  972. break;
  973. }
  974. }
  975. bitburner_rotate_array(avalon);
  976. pthread_cond_signal(&info->qcond);
  977. mutex_unlock(&info->qlock);
  978. if (unlikely(idled)) {
  979. applog(LOG_WARNING, "%s%i: Idled %d miners",
  980. avalon->drv->name, avalon->device_id, idled);
  981. }
  982. }
  983. return NULL;
  984. }
  985. static bool avalon_prepare(struct thr_info *thr)
  986. {
  987. struct cgpu_info *avalon = thr->cgpu;
  988. struct avalon_info *info = avalon->device_data;
  989. int array_size = AVALON_ARRAY_SIZE;
  990. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  991. if (usb_ident(avalon) == IDENT_BTB) {
  992. array_size = BITBURNER_ARRAY_SIZE;
  993. write_thread_fn = bitburner_send_tasks;
  994. }
  995. free(avalon->works);
  996. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  997. array_size);
  998. if (!avalon->works)
  999. quit(1, "Failed to calloc avalon works in avalon_prepare");
  1000. info->thr = thr;
  1001. mutex_init(&info->lock);
  1002. mutex_init(&info->qlock);
  1003. if (unlikely(pthread_cond_init(&info->qcond, NULL)))
  1004. quit(1, "Failed to pthread_cond_init avalon qcond");
  1005. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  1006. quit(1, "Failed to create avalon read_thr");
  1007. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  1008. quit(1, "Failed to create avalon write_thr");
  1009. avalon_init(avalon);
  1010. return true;
  1011. }
  1012. static void do_avalon_close(struct thr_info *thr)
  1013. {
  1014. struct cgpu_info *avalon = thr->cgpu;
  1015. struct avalon_info *info = avalon->device_data;
  1016. pthread_join(info->read_thr, NULL);
  1017. pthread_join(info->write_thr, NULL);
  1018. avalon_running_reset(avalon, info);
  1019. info->no_matching_work = 0;
  1020. }
  1021. static inline void record_temp_fan(struct avalon_info *info, struct avalon_result *ar, float *temp_avg)
  1022. {
  1023. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1024. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1025. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1026. info->temp0 = ar->temp0;
  1027. info->temp1 = ar->temp1;
  1028. info->temp2 = ar->temp2;
  1029. if (ar->temp0 & 0x80) {
  1030. ar->temp0 &= 0x7f;
  1031. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1032. }
  1033. if (ar->temp1 & 0x80) {
  1034. ar->temp1 &= 0x7f;
  1035. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1036. }
  1037. if (ar->temp2 & 0x80) {
  1038. ar->temp2 &= 0x7f;
  1039. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1040. }
  1041. *temp_avg = info->temp2 > info->temp1 ? info->temp2 : info->temp1;
  1042. if (info->temp0 > info->temp_max)
  1043. info->temp_max = info->temp0;
  1044. if (info->temp1 > info->temp_max)
  1045. info->temp_max = info->temp1;
  1046. if (info->temp2 > info->temp_max)
  1047. info->temp_max = info->temp2;
  1048. }
  1049. static void temp_rise(struct avalon_info *info, int temp)
  1050. {
  1051. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1052. info->fan_pwm = AVALON_PWM_MAX;
  1053. return;
  1054. }
  1055. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1056. info->fan_pwm += 10;
  1057. else if (temp > opt_avalon_temp)
  1058. info->fan_pwm += 5;
  1059. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1060. info->fan_pwm += 1;
  1061. else
  1062. return;
  1063. if (info->fan_pwm > opt_avalon_fan_max)
  1064. info->fan_pwm = opt_avalon_fan_max;
  1065. }
  1066. static void temp_drop(struct avalon_info *info, int temp)
  1067. {
  1068. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1069. info->fan_pwm = opt_avalon_fan_min;
  1070. return;
  1071. }
  1072. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1073. info->fan_pwm -= 10;
  1074. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1075. info->fan_pwm -= 5;
  1076. else if (temp < opt_avalon_temp)
  1077. info->fan_pwm -= 1;
  1078. if (info->fan_pwm < opt_avalon_fan_min)
  1079. info->fan_pwm = opt_avalon_fan_min;
  1080. }
  1081. static inline void adjust_fan(struct avalon_info *info)
  1082. {
  1083. int temp_new;
  1084. temp_new = info->temp_sum / info->temp_history_count;
  1085. if (temp_new > info->temp_old)
  1086. temp_rise(info, temp_new);
  1087. else if (temp_new < info->temp_old)
  1088. temp_drop(info, temp_new);
  1089. else {
  1090. /* temp_new == info->temp_old */
  1091. if (temp_new > opt_avalon_temp)
  1092. temp_rise(info, temp_new);
  1093. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1094. temp_drop(info, temp_new);
  1095. }
  1096. info->temp_old = temp_new;
  1097. if (info->temp_old <= opt_avalon_temp)
  1098. info->optimal = true;
  1099. else
  1100. info->optimal = false;
  1101. }
  1102. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1103. struct avalon_result *ar)
  1104. {
  1105. record_temp_fan(info, ar, &(avalon->temp));
  1106. applog(LOG_INFO,
  1107. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1108. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %dC",
  1109. info->fan0, info->fan1, info->fan2,
  1110. info->temp0, info->temp1, info->temp2, info->temp_max);
  1111. info->temp_history_index++;
  1112. info->temp_sum += avalon->temp;
  1113. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1114. info->temp_history_index, info->temp_history_count, info->temp_old);
  1115. if (usb_ident(avalon) == IDENT_BTB) {
  1116. info->core_voltage = bitburner_get_core_voltage(avalon);
  1117. }
  1118. if (info->temp_history_index == info->temp_history_count) {
  1119. adjust_fan(info);
  1120. info->temp_history_index = 0;
  1121. info->temp_sum = 0;
  1122. }
  1123. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1124. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1125. info->overheat = true;
  1126. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1127. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1128. info->overheat = false;
  1129. }
  1130. }
  1131. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1132. {
  1133. struct avalon_info *info = avalon->device_data;
  1134. int lowfan = 10000;
  1135. if (usb_ident(avalon) == IDENT_BTB) {
  1136. tailsprintf(buf, bufsiz, "%2d/%3dC %4dmV | ", info->temp0, info->temp2, info->core_voltage);
  1137. } else {
  1138. /* Find the lowest fan speed of the ASIC cooling fans. */
  1139. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1140. lowfan = info->fan1;
  1141. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1142. lowfan = info->fan2;
  1143. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR | ", info->temp0, info->temp2, lowfan);
  1144. }
  1145. }
  1146. /* We use a replacement algorithm to only remove references to work done from
  1147. * the buffer when we need the extra space for new work. */
  1148. static bool avalon_fill(struct cgpu_info *avalon)
  1149. {
  1150. struct avalon_info *info = avalon->device_data;
  1151. int subid, slot, mc;
  1152. struct work *work;
  1153. bool ret = true;
  1154. mc = info->miner_count;
  1155. mutex_lock(&info->qlock);
  1156. if (avalon->queued >= mc)
  1157. goto out_unlock;
  1158. work = get_queued(avalon);
  1159. if (unlikely(!work)) {
  1160. ret = false;
  1161. goto out_unlock;
  1162. }
  1163. subid = avalon->queued++;
  1164. work->subid = subid;
  1165. slot = avalon->work_array * mc + subid;
  1166. if (likely(avalon->works[slot]))
  1167. work_completed(avalon, avalon->works[slot]);
  1168. avalon->works[slot] = work;
  1169. if (avalon->queued < mc)
  1170. ret = false;
  1171. out_unlock:
  1172. mutex_unlock(&info->qlock);
  1173. return ret;
  1174. }
  1175. static int64_t avalon_scanhash(struct thr_info *thr)
  1176. {
  1177. struct cgpu_info *avalon = thr->cgpu;
  1178. struct avalon_info *info = avalon->device_data;
  1179. const int miner_count = info->miner_count;
  1180. struct timeval now, then, tdiff;
  1181. int64_t hash_count, us_timeout;
  1182. struct timespec abstime;
  1183. /* Half nonce range */
  1184. us_timeout = 0x80000000ll / info->asic_count / info->frequency;
  1185. us_to_timeval(&tdiff, us_timeout);
  1186. cgtime(&now);
  1187. timeradd(&now, &tdiff, &then);
  1188. timeval_to_spec(&abstime, &then);
  1189. /* Wait until avalon_send_tasks signals us that it has completed
  1190. * sending its work or a full nonce range timeout has occurred */
  1191. mutex_lock(&info->qlock);
  1192. pthread_cond_timedwait(&info->qcond, &info->qlock, &abstime);
  1193. mutex_unlock(&info->qlock);
  1194. mutex_lock(&info->lock);
  1195. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1196. avalon->results += info->nonces + info->idle;
  1197. if (avalon->results > miner_count)
  1198. avalon->results = miner_count;
  1199. if (!info->reset)
  1200. avalon->results--;
  1201. info->nonces = info->idle = 0;
  1202. mutex_unlock(&info->lock);
  1203. /* Check for nothing but consecutive bad results or consistently less
  1204. * results than we should be getting and reset the FPGA if necessary */
  1205. if (usb_ident(avalon) != IDENT_BTB) {
  1206. if (avalon->results < -miner_count && !info->reset) {
  1207. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1208. avalon->drv->name, avalon->device_id);
  1209. info->reset = true;
  1210. }
  1211. }
  1212. if (unlikely(avalon->usbinfo.nodev)) {
  1213. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1214. avalon->drv->name, avalon->device_id);
  1215. avalon->shutdown = true;
  1216. }
  1217. /* This hashmeter is just a utility counter based on returned shares */
  1218. return hash_count;
  1219. }
  1220. static void avalon_flush_work(struct cgpu_info *avalon)
  1221. {
  1222. struct avalon_info *info = avalon->device_data;
  1223. mutex_lock(&info->qlock);
  1224. /* Will overwrite any work queued */
  1225. avalon->queued = 0;
  1226. pthread_cond_signal(&info->qcond);
  1227. mutex_unlock(&info->qlock);
  1228. }
  1229. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1230. {
  1231. struct api_data *root = NULL;
  1232. struct avalon_info *info = cgpu->device_data;
  1233. int i;
  1234. root = api_add_int(root, "baud", &(info->baud), false);
  1235. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1236. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1237. root = api_add_int(root, "timeout", &(info->timeout), false);
  1238. root = api_add_int(root, "frequency", &(info->frequency), false);
  1239. root = api_add_int(root, "fan1", &(info->fan0), false);
  1240. root = api_add_int(root, "fan2", &(info->fan1), false);
  1241. root = api_add_int(root, "fan3", &(info->fan2), false);
  1242. root = api_add_int(root, "temp1", &(info->temp0), false);
  1243. root = api_add_int(root, "temp2", &(info->temp1), false);
  1244. root = api_add_int(root, "temp3", &(info->temp2), false);
  1245. root = api_add_int(root, "temp_max", &(info->temp_max), false);
  1246. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1247. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1248. for (i = 0; i < info->miner_count; i++) {
  1249. char mcw[24];
  1250. sprintf(mcw, "match_work_count%d", i + 1);
  1251. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1252. }
  1253. return root;
  1254. }
  1255. static void avalon_shutdown(struct thr_info *thr)
  1256. {
  1257. do_avalon_close(thr);
  1258. }
  1259. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1260. {
  1261. int val;
  1262. if (strcasecmp(option, "help") == 0) {
  1263. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1264. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1265. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1266. return replybuf;
  1267. }
  1268. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1269. if (usb_ident(avalon) != IDENT_BTB) {
  1270. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1271. return replybuf;
  1272. }
  1273. if (!setting || !*setting) {
  1274. sprintf(replybuf, "missing millivolts setting");
  1275. return replybuf;
  1276. }
  1277. val = atoi(setting);
  1278. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1279. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1280. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1281. return replybuf;
  1282. }
  1283. if (bitburner_set_core_voltage(avalon, val))
  1284. return NULL;
  1285. else {
  1286. sprintf(replybuf, "Set millivolts failed");
  1287. return replybuf;
  1288. }
  1289. }
  1290. if (strcasecmp(option, "freq") == 0) {
  1291. if (!setting || !*setting) {
  1292. sprintf(replybuf, "missing freq setting");
  1293. return replybuf;
  1294. }
  1295. val = atoi(setting);
  1296. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1297. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1298. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1299. return replybuf;
  1300. }
  1301. avalon_set_freq(avalon, val);
  1302. return NULL;
  1303. }
  1304. sprintf(replybuf, "Unknown option: %s", option);
  1305. return replybuf;
  1306. }
  1307. struct device_drv avalon_drv = {
  1308. .drv_id = DRIVER_AVALON,
  1309. .dname = "avalon",
  1310. .name = "AVA",
  1311. .drv_detect = avalon_detect,
  1312. .thread_prepare = avalon_prepare,
  1313. .hash_work = hash_queued_work,
  1314. .queue_full = avalon_fill,
  1315. .scanwork = avalon_scanhash,
  1316. .flush_work = avalon_flush_work,
  1317. .get_api_stats = avalon_api_stats,
  1318. .get_statline_before = get_avalon_statline_before,
  1319. .set_device = avalon_set_device,
  1320. .reinit_device = avalon_init,
  1321. .thread_shutdown = avalon_shutdown,
  1322. };