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@@ -147,9 +147,9 @@ static bool cairnsmore_init(struct thr_info *thr)
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CAIRNSMORE1_DEFAULT_CLOCK, CAIRNSMORE1_MINIMUM_CLOCK, CAIRNSMORE1_MAXIMUM_CLOCK
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CAIRNSMORE1_DEFAULT_CLOCK, CAIRNSMORE1_MINIMUM_CLOCK, CAIRNSMORE1_MAXIMUM_CLOCK
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);
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);
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// The dynamic-clocking firmware connects each FPGA as its own device
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// The dynamic-clocking firmware connects each FPGA as its own device
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- if (!(info->user_set & 1)) {
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+ if (!(info->user_set & IUS_WORK_DIVISION)) {
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info->work_division = 1;
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info->work_division = 1;
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- if (!(info->user_set & 2))
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+ if (!(info->user_set & IUS_FPGA_COUNT))
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info->fpga_count = 1;
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info->fpga_count = 1;
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}
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}
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} else {
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} else {
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