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@@ -0,0 +1,520 @@
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+/*
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+ * Copyright 2015 John Stefanopoulos
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+ * Copyright 2014-2015 Luke Dashjr
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the Free
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+ * Software Foundation; either version 3 of the License, or (at your option)
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+ * any later version. See COPYING for more details.
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+ */
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+
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+
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+#include "config.h"
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+
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+#include <stdbool.h>
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+#include <stdint.h>
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+#include <stdlib.h>
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+#include <string.h>
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+#include <unistd.h>
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+#include <stdio.h>
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+#include <libusb.h>
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+#include "deviceapi.h"
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+#include "logging.h"
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+#include "lowlevel.h"
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+#include "lowl-vcom.h"
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+#include "util.h"
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+
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+
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+static const uint8_t futurebit_max_chips = 0x01;
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+#define FUTUREBIT_DEFAULT_FREQUENCY 104
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+#define FUTUREBIT_MIN_CLOCK 104
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+#define FUTUREBIT_MAX_CLOCK 400
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+// Number of seconds chip of 54 cores @ 352mhz takes to scan full range
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+#define FUTUREBIT_HASH_SPEED 4090.0
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+#define FUTUREBIT_MAX_NONCE 0xffffffff
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+#define FUTUREBIT_READ_SIZE 8
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+#define futurebit_max_clusters_per_chip 6
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+#define futurebit_max_cores_per_cluster 9
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+static const uint8_t futurebit_g_head[] = {
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+ 0xd4, 0x59, 0x2d, 0x01, 0x1d, 0x01, 0x8e, 0xa7, 0x4e, 0xbb, 0x17, 0xb8, 0x06, 0x6b, 0x2a, 0x75,
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+ 0x83, 0x99, 0xd5, 0xf1, 0x9b, 0x5c, 0x60, 0x73, 0xd0, 0x9b, 0x50, 0x0d, 0x92, 0x59, 0x82, 0xad,
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+ 0xc4, 0xb3, 0xed, 0xd3, 0x52, 0xef, 0xe1, 0x46, 0x67, 0xa8, 0xca, 0x9f, 0x27, 0x9f, 0x63, 0x30,
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+ 0xcc, 0xbb, 0xb9, 0x10, 0x3b, 0x9e, 0x3a, 0x53, 0x50, 0x76, 0x50, 0x52, 0x08, 0x1d, 0xdb, 0xae,
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+ 0x89, 0x8f, 0x1e, 0xf6, 0xb8, 0xc6, 0x4f, 0x3b, 0xce, 0xf7, 0x15, 0xf6, 0, 0, 0, 1,
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+ 0, 0, 0, 1, 0x8e, 0xa7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0
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+};
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+
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+
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+BFG_REGISTER_DRIVER(futurebit_drv)
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+
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+static const struct bfg_set_device_definition futurebit_set_device_funcs_probe[];
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+
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+struct futurebit_chip {
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+ uint8_t chipid;
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+ uint8_t global_reg[8];
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+ uint16_t chip_mask[futurebit_max_clusters_per_chip];
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+ uint32_t clst_offset[futurebit_max_clusters_per_chip];
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+ unsigned active_cores;
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+ unsigned freq;
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+};
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+
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+static
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+void futurebit_chip_init(struct futurebit_chip * const chip, const uint8_t chipid)
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+{
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+ *chip = (struct futurebit_chip){
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+ .chipid = chipid,
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+ .global_reg = {0, 4, 0x40, 0, 0, 0, 0, 1},
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+ .chip_mask = {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
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+ .clst_offset = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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+ .active_cores = 54,
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+ .freq = FUTUREBIT_DEFAULT_FREQUENCY,
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+ };
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+}
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+
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+static
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+void futurebit_reset_board(const int fd)
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+{
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+
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+ if(set_serial_rts(fd, BGV_HIGH) == BGV_ERROR)
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+ applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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+
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+ cgsleep_ms(100);
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+
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+ if(set_serial_rts(fd, BGV_LOW) == BGV_ERROR)
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+ applog(LOG_DEBUG, "IOCTL RTS RESET FAILED");
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+}
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+
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+static
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+void futurebit_set_diag_mode(struct futurebit_chip * const chip, bool diag_enable)
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+{
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+ if (diag_enable)
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+ chip->global_reg[1] |= 1;
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+ else
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+ chip->global_reg[1] &= ~1;
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+}
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+
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+static
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+bool futurebit_write_global_reg(const int fd, const struct futurebit_chip * const chip)
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+{
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+ uint8_t buf[112];
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+ memset(&buf, 0, 102);
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+ memcpy(&buf[102], &chip->global_reg[0], 8);
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+ buf[110] = 0;
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+ buf[111] = 0xff;
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+
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+ if (write(fd, buf, sizeof(buf)) != sizeof(buf))
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+ return false;
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+ return true;
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+}
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+
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+static
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+bool futurebit_write_cluster_reg(const int fd, const struct futurebit_chip * const chip, const uint16_t cores_active, const uint32_t offset, const uint8_t clstid)
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+{
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+ uint8_t buf[112];
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+ memset(&buf, 0, 104);
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+ pk_u16be(buf, 104, cores_active);
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+ pk_u32be(buf, 106, offset);
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+ buf[110] = clstid;
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+ buf[111] = 0xfe;
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+ //applog(LOG_DEBUG, " %u: %u: %u : %u", buf[106], buf[107], buf[108], buf[109]);
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+ if (write(fd, buf, sizeof(buf)) != sizeof(buf))
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+ return false;
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+ return true;
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+}
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+
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+
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+static
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+bool futurebit_init_pll(const int fd, struct futurebit_chip * const chip)
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+{
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+ unsigned freq = chip->freq;
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+ uint8_t bytes1;
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+ uint8_t bytes2;
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+ uint8_t divider;
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+
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+ if (freq <= 200){
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+ divider = (freq - 8)/8;
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+ divider <<= 1;
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+ bytes1 = 0x70 | ((divider & 0xf0) >> 4);
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+ bytes2 = 0x30 | ((divider & 0xf0) >> 4);
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+
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+ }else {
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+ divider = (freq - 16)/16;
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+ divider <<= 1;
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+ bytes1 = 0x60 | ((divider & 0xf0) >> 4);
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+ bytes2 = 0x20 | ((divider & 0xf0) >> 4);
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+ }
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+
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+ uint8_t bytes3 = 0x00 | ((divider & 0x0f) << 4);
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+
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+ pk_u16be(chip->global_reg, 2, 0x4000);
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+ chip->global_reg[1] |= 0xc;
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+ if (!futurebit_write_global_reg(fd, chip))
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+ return false;
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+
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+ chip->global_reg[2] = bytes1;
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+ chip->global_reg[3] = bytes3;
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+ cgsleep_ms(50);
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+ if (!futurebit_write_global_reg(fd, chip))
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+ return false;
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+
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+ chip->global_reg[2] = bytes2;
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+ chip->global_reg[1] &= ~8;
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+ cgsleep_ms(50);
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+ if (!futurebit_write_global_reg(fd, chip))
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+ return false;
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+
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+ chip->global_reg[1] &= ~4;
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+ cgsleep_ms(50);
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+ if (!futurebit_write_global_reg(fd, chip))
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+ return false;
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+
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+ return true;
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+}
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+
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+static
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+bool futurebit_send_golden(const int fd, const struct futurebit_chip * const chip, const void * const data, const void * const target_p)
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+{
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+ uint8_t buf[112];
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+ const uint8_t * const target = target_p;
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+
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+ memcpy(buf, data, 80);
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+ if (target && !target[0x1f])
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+ memcpy(&buf[80], target, 0x20);
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+ else
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+ {
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+ memset(&buf[80], 0xff, 0x1f);
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+ buf[111] = 0;
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+ }
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+
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+ //char output[(sizeof(buf) * 2) + 1];
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+ //bin2hex(output, buf, sizeof(buf));
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+ //applog(LOG_DEBUG, "GOLDEN OUTPUT %s", output);
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+
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+ if (write(fd, buf, sizeof(buf)) != sizeof(buf))
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+ return false;
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+ return true;
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+}
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+
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+static
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+bool futurebit_send_work(const struct thr_info * const thr, struct work * const work)
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+{
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+ struct cgpu_info *device = thr->cgpu;
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+ uint8_t buf[112];
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+ uint8_t cmd[112];
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+ const uint8_t * const target = work->target;
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+
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+ unsigned char swpdata[80];
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+
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+ //buf[0] = 0;
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+ //memset(&buf[1], 0xff, 0x1f);
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+ memset(&buf[0], 0, 0x18);
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+ memcpy(&buf[24], &target[24], 0x8);
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+
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+ swap32tobe(swpdata, work->data, 80/4);
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+ memcpy(&buf[32], swpdata, 80);
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+
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+ for (int i = 0; i<112; i++) {
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+ cmd[i] = buf[111 - i];
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+ }
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+
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+ if (write(device->device_fd, cmd, sizeof(cmd)) != sizeof(cmd))
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+ return false;
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+
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+ work->blk.nonce = FUTUREBIT_MAX_NONCE;
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+
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+ return true;
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+}
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+
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+static
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+bool futurebit_detect_one(const char * const devpath)
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+{
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+ struct futurebit_chip *chips = NULL;
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+ unsigned total_cores = 0;
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+
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+ const int fd = serial_open(devpath, 115200, 1, true);
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+ if (fd < 0)
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+ return_via_applog(err, , LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Failed to open", devpath);
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+
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+ applog(LOG_DEBUG, "%s: %s %s", futurebit_drv.dname, "Successfully opened", devpath);
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+
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+ futurebit_reset_board(fd);
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+
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+ // Init chips, setup PLL, and scan for good cores
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+ chips = malloc(futurebit_max_chips * sizeof(*chips));
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+
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+ struct futurebit_chip * const dummy_chip = &chips[0];
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+ futurebit_chip_init(dummy_chip, 0);
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+
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+ // pick up any user-defined settings passed in via --set
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+ drv_set_defaults(&futurebit_drv, futurebit_set_device_funcs_probe, dummy_chip, devpath, detectone_meta_info.serial, 1);
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+
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+ unsigned freq = dummy_chip->freq;
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+
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+ applog(LOG_DEBUG, "%s: %s %u mhz", futurebit_drv.dname, "Core clock set to", freq);
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+
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+ {
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+ uint8_t buf[8];
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+ for (unsigned i = 0; i < futurebit_max_chips; ++i)
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+ {
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+ struct futurebit_chip * const chip = &chips[i];
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+ futurebit_chip_init(chip, i);
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+ chip->freq = freq;
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+
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+ //chip->global_reg[1] = 0x05;
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+ //if (!futurebit_write_global_reg(fd, chip))
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+ // return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
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+ //cgsleep_ms(50);
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+ futurebit_set_diag_mode(chip, true);
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+ if (!futurebit_init_pll(fd, chip))
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+ return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
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+ cgsleep_ms(50);
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+ if (!futurebit_send_golden(fd, chip, futurebit_g_head, NULL))
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+ return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send scan job", devpath);
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+
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+ while (serial_read(fd, buf, 8) == 8)
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+ {
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+
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+ const uint8_t clsid = buf[7];
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+ if (clsid >= futurebit_max_clusters_per_chip)
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+ applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "cluster", clsid, devpath, i);
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+ const uint8_t coreid = buf[6];
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+ if (coreid >= futurebit_max_cores_per_cluster)
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+ applog(LOG_DEBUG, "%s: Bad %s id (%u) during scan of %s chip %u", futurebit_drv.dname, "core", coreid, devpath, i);
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+
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+ if (buf[0] != 0xd9 || buf[1] != 0xeb || buf[2] != 0x86 || buf[3] != 0x63) {
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+ //chips[i].chip_good[clsid][coreid] = false;
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+ applog(LOG_DEBUG, "%s: Bad %s at core (%u) during scan of %s chip %u cluster %u", futurebit_drv.dname, "nonce", coreid, devpath, i, clsid);
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+ } else {
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+ ++total_cores;
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+ chips[i].chip_mask[clsid] |= (1 << coreid);
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+ }
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+ }
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+ }
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+ }
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+
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+ applog(LOG_DEBUG, "%s: Identified %d cores on %s", futurebit_drv.dname, total_cores, devpath);
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+
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+ if (total_cores == 0)
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+ goto err;
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+
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+ futurebit_reset_board(fd);
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+
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+ // config nonce ranges per cluster based on core responses
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+ unsigned mutiple = FUTUREBIT_MAX_NONCE / total_cores;
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+ uint32_t n_offset = 0x00000000;
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+
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+ for (unsigned i = 0; i < futurebit_max_chips; ++i)
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+ {
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+ struct futurebit_chip * const chip = &chips[i];
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+
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+ chips[i].active_cores = total_cores;
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+
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+ //chip->global_reg[1] = 0x04;
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+ //if (!futurebit_write_global_reg(fd, chip))
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+ //return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "global", devpath);
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+ //cgsleep_ms(50);
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+ futurebit_set_diag_mode(chip, false);
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+ if (!futurebit_init_pll(fd, chip))
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+ return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "init PLL", devpath);
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+ cgsleep_ms(50);
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+
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+ for (unsigned x = 0; x < futurebit_max_clusters_per_chip; ++x) {
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+ unsigned gc = 0;
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+
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+ uint16_t core_mask = chips[i].chip_mask[x];
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+ chips[i].clst_offset[x] = n_offset;
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+
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+ applog(LOG_DEBUG, "OFFSET %u MASK %u CHIP %u CLUSTER %u", n_offset, core_mask, i, x);
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+
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+ if (!futurebit_write_cluster_reg(fd, chip, core_mask, n_offset, x))
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+ return_via_applog(err, , LOG_DEBUG, "%s: Failed to (%s) %s", futurebit_drv.dname, "send config register", devpath);
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+
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+ for (unsigned z = 0; z < 15; ++z) {
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+ if (core_mask & 0x0001)
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+ gc += 1;
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+ core_mask >>= 1;
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+ }
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+
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+ n_offset += mutiple * gc;
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+
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+ cgsleep_ms(50);
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+ }
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+ }
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+
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+ if (serial_claim_v(devpath, &futurebit_drv))
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+ goto err;
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+
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+ //serial_close(fd);
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+ struct cgpu_info * const cgpu = malloc(sizeof(*cgpu));
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+ *cgpu = (struct cgpu_info){
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+ .drv = &futurebit_drv,
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+ .device_path = strdup(devpath),
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+ .deven = DEV_ENABLED,
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+ .procs = 1,
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+ .threads = 1,
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+ .device_data = chips,
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+ };
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+ // NOTE: Xcode's clang has a bug where it cannot find fields inside anonymous unions (more details in fpgautils)
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+ cgpu->device_fd = fd;
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+
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+ return add_cgpu(cgpu);
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+
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+err:
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+ if (fd >= 0)
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+ serial_close(fd);
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+ free(chips);
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * scanhash mining loop
|
|
|
+ */
|
|
|
+
|
|
|
+static
|
|
|
+void futurebit_submit_nonce(struct thr_info * const thr, const uint8_t buf[8], struct work * const work, struct timeval const start_tv)
|
|
|
+{
|
|
|
+ struct cgpu_info *device = thr->cgpu;
|
|
|
+ struct futurebit_chip *chips = device->device_data;
|
|
|
+
|
|
|
+ uint32_t nonce = *(uint32_t *)buf;
|
|
|
+ nonce = bswap_32(nonce);
|
|
|
+
|
|
|
+ submit_nonce(thr, work, nonce);
|
|
|
+
|
|
|
+ // hashrate calc
|
|
|
+
|
|
|
+ const uint8_t clstid = buf[7];
|
|
|
+ uint32_t range = chips[0].clst_offset[clstid];
|
|
|
+
|
|
|
+ struct timeval now_tv;
|
|
|
+ timer_set_now(&now_tv);
|
|
|
+ int elapsed_ms = ms_tdiff(&now_tv, &start_tv);
|
|
|
+
|
|
|
+ double total_hashes = ((nonce - range)/9.0) * chips[0].active_cores;
|
|
|
+ double hashes_per_ms = total_hashes/elapsed_ms;
|
|
|
+ uint64_t hashes = hashes_per_ms * ms_tdiff(&now_tv, &thr->_tv_last_hashes_done_call);
|
|
|
+
|
|
|
+ if(hashes_per_ms < 1500 && hashes < 100000000)
|
|
|
+ hashes_done2(thr, hashes, NULL);
|
|
|
+ else
|
|
|
+ hashes_done2(thr, 100000, NULL);
|
|
|
+}
|
|
|
+
|
|
|
+// send work to the device
|
|
|
+static
|
|
|
+int64_t futurebit_scanhash(struct thr_info *thr, struct work *work, int64_t __maybe_unused max_nonce)
|
|
|
+{
|
|
|
+ struct cgpu_info *device = thr->cgpu;
|
|
|
+ int fd = device->device_fd;
|
|
|
+ struct futurebit_chip *chips = device->device_data;
|
|
|
+ struct timeval start_tv, nonce_range_tv;
|
|
|
+
|
|
|
+ // amount of time it takes this device to scan a nonce range:
|
|
|
+ uint32_t nonce_full_range_sec = FUTUREBIT_HASH_SPEED * 352.0 / FUTUREBIT_DEFAULT_FREQUENCY * 54.0 / chips[0].active_cores;
|
|
|
+ // timer to break out of scanning should we close in on an entire nonce range
|
|
|
+ // should break out before the range is scanned, so we are doing 95% of the range
|
|
|
+ uint64_t nonce_near_range_usec = (nonce_full_range_sec * 1000000. * 0.95);
|
|
|
+ timer_set_delay_from_now(&nonce_range_tv, nonce_near_range_usec);
|
|
|
+
|
|
|
+ // start the job
|
|
|
+ timer_set_now(&start_tv);
|
|
|
+
|
|
|
+ if (!futurebit_send_work(thr, work)) {
|
|
|
+ applog(LOG_DEBUG, "Failed to start job");
|
|
|
+ dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
|
+ }
|
|
|
+
|
|
|
+ uint8_t buf[8];
|
|
|
+ int read = 0;
|
|
|
+ bool range_nearly_scanned = false;
|
|
|
+
|
|
|
+ while (!thr->work_restart // true when new work is available (miner.c)
|
|
|
+ && ((read = serial_read(fd, buf, 8)) >= 0) // only check for failure - allow 0 bytes
|
|
|
+ && !(range_nearly_scanned = timer_passed(&nonce_range_tv, NULL))) // true when we've nearly scanned a nonce range
|
|
|
+ {
|
|
|
+ if (read == 0)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ if (read == 8) {
|
|
|
+ futurebit_submit_nonce(thr, buf, work, start_tv);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ applog(LOG_ERR, "%"PRIpreprv": Unrecognized response", device->proc_repr);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (read == -1)
|
|
|
+ {
|
|
|
+ applog(LOG_ERR, "%s: Failed to read result", device->dev_repr);
|
|
|
+ dev_error(device, REASON_DEV_COMMS_ERROR);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * setup & shutdown
|
|
|
+ */
|
|
|
+
|
|
|
+static
|
|
|
+bool futurebit_lowl_probe(const struct lowlevel_device_info * const info)
|
|
|
+{
|
|
|
+ return vcom_lowl_probe_wrapper(info, futurebit_detect_one);
|
|
|
+}
|
|
|
+
|
|
|
+static
|
|
|
+void futurebit_thread_shutdown(struct thr_info *thr)
|
|
|
+{
|
|
|
+ struct cgpu_info *device = thr->cgpu;
|
|
|
+
|
|
|
+ futurebit_reset_board(device->device_fd);
|
|
|
+
|
|
|
+ serial_close(device->device_fd);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * specify settings / options via RPC or command line
|
|
|
+ */
|
|
|
+
|
|
|
+// support for --set
|
|
|
+// must be set before probing the device
|
|
|
+
|
|
|
+// for setting clock and chips during probe / detect
|
|
|
+
|
|
|
+static
|
|
|
+const char *futurebit_set_clock(struct cgpu_info * const device, const char * const option, const char * const setting, char * const replybuf, enum bfg_set_device_replytype * const success)
|
|
|
+{
|
|
|
+ struct futurebit_chip * const chip = device->device_data;
|
|
|
+ int val = atoi(setting);
|
|
|
+
|
|
|
+ if (val < FUTUREBIT_MIN_CLOCK || val > FUTUREBIT_MAX_CLOCK || (val%8)) {
|
|
|
+ sprintf(replybuf, "invalid clock: '%s' valid range %d-%d. Clock must be a mutiple of 8 between 104-200mhz, and a mutiple of 16 between 208-400mhz",
|
|
|
+ setting, FUTUREBIT_MIN_CLOCK, FUTUREBIT_MAX_CLOCK);
|
|
|
+ return replybuf;
|
|
|
+ } else
|
|
|
+ chip->freq = val;
|
|
|
+
|
|
|
+ return NULL;
|
|
|
+}
|
|
|
+
|
|
|
+static
|
|
|
+const struct bfg_set_device_definition futurebit_set_device_funcs_probe[] = {
|
|
|
+ { "clock", futurebit_set_clock, NULL },
|
|
|
+ { NULL },
|
|
|
+};
|
|
|
+
|
|
|
+struct device_drv futurebit_drv = {
|
|
|
+ .dname = "futurebit",
|
|
|
+ .name = "MLD",
|
|
|
+ .drv_min_nonce_diff = common_scrypt_min_nonce_diff,
|
|
|
+ // detect device
|
|
|
+ .lowl_probe = futurebit_lowl_probe,
|
|
|
+ // specify mining type - scanhash
|
|
|
+ .minerloop = minerloop_scanhash,
|
|
|
+
|
|
|
+ // scanhash mining hooks
|
|
|
+ .scanhash = futurebit_scanhash,
|
|
|
+
|
|
|
+ // teardown device
|
|
|
+ .thread_shutdown = futurebit_thread_shutdown,
|
|
|
+};
|
jstefanop